The present invention relates to voltage regulators, particularly low-dropout voltage regulators.

Low-dropout (or LDO) voltage regulators are linear DC voltage regulators that are capable of operating with very low input-output differential voltages. Such regulators are usually chosen because they have a low minimum operating voltage, relatively high power efficiency compared to some other linear regulators, and low heat dissipation. These properties together with their linear behaviour and low voltage dropout make typical LDO voltage regulators a popular choice for supplying or "sourcing" current to on-chip loads. An LDO voltage regulator is typically constructed from an error amplifier (an operational transconductance amplifier or "OTA"), a pass field-effect-transistor (FET) or "pass-FET", and a feedback network. The load current is sourced to the load through the pass-FET and the output voltage is regulated through the feedback network, assuming that the loop including the error amplifier, the pass- FET, and the feedback network provides sufficient loop gain. The output voltage is equal to the reference voltage multiplied by the reciprocal of the attenuation of the feedback network if the loop gain is sufficiently high.

Conventional LDO voltage regulators may also be able to absorb or "sink" a small amount of current from the output node. The feedback network typically provides a path from the regulated output node to ground. However, the Applicant has appreciated that this typically works only if the current to be sinked is orders of magnitude smaller than the quiescent current of the feedback network. According to a first aspect, the present invention provides a voltage regulator arranged to receive an input voltage and produce a regulated output voltage, the voltage regulator comprising:

a current source transistor and a current sink transistor arranged to provide the output voltage at a node therebetween; a first error amplifier arranged to compare a feedback voltage to a reference voltage and apply a first control voltage to a gate terminal of the current source transistor, wherein said first control voltage is dependent on a difference between the feedback voltage and the reference voltage;

a second error amplifier arranged in parallel to the first error amplifier, said second error amplifier being arranged to compare the feedback voltage to the reference voltage and apply a second control voltage to a gate terminal of the current sink transistor, wherein said second control voltage is dependent on a difference between the feedback voltage and the reference voltage;

wherein said feedback voltage is derived from the output voltage.

Thus it will be appreciated by those skilled in the art that in accordance with the present invention an LDO voltage regulator may have two separate error amplifiers in parallel and two separate pass-FETs. These two pass-FETs may be arranged such that the current source transistor is able to source current to the output when made to conduct by the first error amplifier, while the current sink transistor is able to sink current from the output when made to conduct by the second error amplifier. Embodiments of the present invention are advantageously capable of sinking currents from the output that are orders of magnitude greater than the quiescent current of the feedback path while maintaining the desired value of the regulated output voltage. Embodiments of the present invention are also advantageously able to allow voltage regulating with a very low bias current during normal operation - i.e. during current sourcing as opposed to current sinking. The present invention may be particularly advantageous, by way of non-limiting example only, in circuits provided with multiple voltage regulators which are used under different operating conditions. For example an LDO voltage regulator in accordance with embodiments of the present invention may be provided alongside a further voltage regulator (e.g. a high power LDO voltage regulator) and a DC-DC buck converter. This further voltage regulator and buck converter may leak current (e.g. up to 10 μΑ) when powered down, typically due to leakage current associated with a pass-FET within the further regulator or power switches within the buck converter. This leakage current is then seen as a constant DC current sinked into the output of the LDO voltage regulator. ln some embodiments, the voltage regulator comprises a feedback network arranged to provide the feedback voltage which depends on the output voltage. While the feedback network or networks may be constructed using passive components such as resistors, inductors and capacitors or using a digital controller, in at least some embodiments, the feedback network(s) comprise(s) a ladder of diode-connected metal-oxide-semiconductor field-effect-transistors.

It should be appreciated that the reference voltages used by the first and second error amplifiers should be the same or at least substantially the same. Similarly, the feedback voltages used by the first and second error amplifiers should also be the same or at least substantially the same. The term "substantially the same" as used herein with respect to the reference and feedback voltages means that they are the same for each error amplifier, except for process variations. The reference voltage and/or feedback voltage could theoretically be changed in value (e.g. using a potential divider) before being used by one of the error amplifiers which would make the local value entering the two error amplifiers different despite being derived from the same voltage originally, but this is not preferred as it would require

corresponding changes within the affected error amplifier to accommodate this and may lead to unnecessary sources of error and undesirable increases in chip area and power consumption.

In some embodiments, the current source transistor comprises a p-channel metal- oxide-semiconductor field-effect-transistor (pMOSFET). In some potentially overlapping embodiments, the current sink transistor comprises an n-channel metal-oxide-semiconductor field-effect-transistor (nMOSFET).

In some embodiments, the source terminal of the current source transistor is connected to the input voltage. In some potentially overlapping embodiments, the source terminal of the current sink transistor is connected to ground.

In some embodiments, the respective drain terminals of the current source transistor and the current sink transistor are connected together at the node arranged to provide the output voltage. It will be appreciated by those skilled in the art that in accordance with such embodiments, the current source and sink transistors may form a "push-pull" pair. While it will be appreciated that there are a number of error amplifier topologies known in the art per se, in some embodiments the first error amplifier comprises first and second differential nMOSFETs, wherein the gate terminal of the first differential nMOSFET is connected to the feedback voltage, the gate terminal of the second differential nMOSFET is connected to the reference voltage.

In some potentially overlapping embodiments, the first error amplifier further comprises a constant current source. In the set of embodiments wherein the first error amplifier comprises first and second differential nMOSFETs, the constant current source may be connected to the source terminals of said first and second differential nMOSFETs. This constant current source provides a constant bias current to the first error amplifier such that it can vary the conductivity of the current source transistor during normal operation.

In a set of potentially overlapping embodiments, the first error amplifier further comprises a first current mirror comprising first and second mirror pMOSFETs arranged such that:

the gate and drain terminals of the first mirror pMOSFET are connected to the gate terminal of the second mirror pMOSFET and the drain terminal of the first differential nMOSFET;

the drain terminal of the second mirror pMOSFET is connected to the drain terminal of the second differential nMOSFET; and

the source terminals of the first and second mirror pMOSFETs are connected to the input voltage. Those skilled in the art will appreciate that this provides a current mirror load to the first error amplifier.

In some such embodiments, the second error amplifier further comprises a tail transistor arranged such that its drain terminal is connected to the respective source terminals of the first and second differential pMOSFETs and its gate terminal is connected to the gate and drain terminals of the first mirror pMOSFET. In a set of embodiments, the tail transistor is a pMOSFET.

In a potentially overlapping set of embodiments, the second error amplifier comprises first and second differential pMOSFETs, wherein the gate terminal of the first differential pMOSFET is connected to the feedback voltage, and the gate terminal of the second differential pMOSFET is connected to the reference voltage. In some embodiments described above, the bias current of the second error amplifier can be controlled by the first error amplifier, reducing the overall current consumption of the LDO voltage regulator when the current sinking feature is not required. More generally, in a set of embodiments, the first error amplifier is arranged to vary a bias current provided to the second error amplifier.

In a set of potentially overlapping embodiments, the second error amplifier further comprises a second current mirror comprising first and second mirror nMOSFETs arranged such that:

the gate and drain terminals of the first mirror nMOSFET are connected to the gate terminal of the second mirror nMOSFET and the drain terminal of the first differential pMOSFET;

the drain terminal of the second mirror nMOSFET is connected to the drain terminal of the second differential pMOSFET; and

the source terminals of the first and second mirror nMOSFETs are connected to ground.

Certain embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings in which:

Fig. 1 is a circuit diagram of a low-dropout voltage regulator in accordance with an embodiment of the present invention;

Fig. 2 is a simulated graph illustrating the behaviour of the circuit shown in Fig. 1 when sinking current; and

Fig. 3 is a simulated graph further illustrating the behaviour across a range of values of a current being sinked into the circuit shown in Fig. 1.

Fig. 1 shows a low-dropout (LDO) voltage regulator 2 in accordance with an embodiment of the present invention. While it will be appreciated that the LDO voltage regulator 2 itself comprises the components in the "on-chip" domain 4, Fig. 1 also shows the bond wire domain 6 and the off-chip domain 8. The LDO voltage regulator 2 comprises: a first error amplifier 10; a second error amplifier 12; a feedback network 14; a current source transistor M _S0U rce; and a current sink transistor M _sink . The LDO voltage regulator 2 is arranged to receive an input voltage V _in and generate a regulated output voltage V _ou t-

The feedback network 14 may comprise a ladder of diode-connected pMOS transistors arranged to generate a feedback voltage ν _¾ which is input to the first and second error amplifiers 10, 12. This feedback voltage is derived from the output voltage V _ou t and is compared to a reference voltage V _re f via each of the error amplifiers 10, 12. It will be appreciated that while the two error amplifiers 10, 12 could utilise different local feedback voltages each derived from the output voltage Vout, this may lead to undesirable "mismatch" errors together with an increase in circuit area and power consumption and so it is preferred that each error amplifier 10, 12 receives the same feedback voltage ν _¾ . It is also preferred that the reference voltage used by each error amplifier 10, 12 is the same for analogous reasons.

The first error amplifier 10 comprises a differential pair of nMOS transistors M, , M ₂ and a current mirror load constructed from two pMOS transistors M ₃ , M ₄ . The differential pair transistors M, , M ₂ are arranged such that their respective source terminals are connected to ground 26 via a current source 16 which provides the differential pair with a constant bias current. The gate terminal of the first nMOS differential pair transistor is connected to the output of the feedback network 14 such that the feedback voltage ν _¾ is applied to the gate terminal of M, . The gate terminal of the second nMOS differential pair transistor M ₂ is connected to the reference voltage V _re f. The drain terminal of is connected at a node 18 to the drain terminal of M ₃ and the gate terminals of both M ₃ and M ₄ . The drain terminal of M ₂ is connected at a node 20 to the drain terminal of M ₄ and to the gate terminal of the current source transistor M _S0U rce- The respective source terminals of the pMOS mirror transistors M ₃ , M ₄ are connected to the input voltage V _in . The second error amplifier 12 comprises a differential pair of pMOS transistors M ₅ , M ₆ and a current mirror load comprising a pair of nMOS mirror transistors M ₇ , M ₈ . The gate terminal of the first pMOS differential transistor M ₅ is connected to the output of the feedback network 14 such that the feedback voltage ν _¾ is applied to the gate terminal of M ₅ while the gate terminal of M ₆ is connected to the reference voltage V _ref . The drain terminal of M ₅ is connected to the drain terminal of M ₇ and the respective gate terminals of M ₇ and M ₈ . The drain terminal of M ₆ is connected to the drain terminal of M ₈ and to the gate terminal of the current sink transistor M _sink . The respective source terminals of M ₇ , M ₈ , M _sink are connected to ground 26.

The respective source terminals of the pMOS differential pair transistors M ₅ , M ₆ are connected to the drain terminal of a pMOS tail transistor M ₉ , which has its respective source terminal connected to the input voltage V _in and its gate terminal connected to the node 18 and thus the respective drain terminals of and M ₃ within the first error amplifier 10.

While not a part of the voltage regulator 2, the inductance and resistance of the bond wire 6 are depicted in Fig. 1 as L _ond and R _ond respectively. A load capacitance C| _0ad and equivalent series resistance FVESR are shown connected to the output of the voltage regulator 2, i.e. the output voltage V _ou t is applied across these in the off-chip domain 8.

The technical operation of the LDO voltage regulator 2 shown in Fig. 1 will now be described. When sourcing load current in normal use, the conductance of the source transistor M _S0U rce is high enough that current flows from the input voltage V _in to the output of the LDO voltage regulator 2. The feedback network 14 varies the feedback voltage ν _¾ in order to regulate the output voltage V _ou t, assuming that each loop including the error amplifier 10, 12, the corresponding pass-FET M _S0U rce, _sink , and the feedback network 14 provides sufficient gain, in a manner known per se. Fig. 2 illustrates the behaviour of a number of voltages and currents in the LDO voltage regulator 2 in response to a load current l _sink (shown in Fig. 1 as a current source 22) being abruptly sunk into the output of the LDO voltage regulator 2. Assuming that the abrupt sinking occurs a time ti , the output voltage V _ou t is seen thereafter to increase linearly due to the charging of the load capacitance (i.e. svout _ smk_ ^ _{t t} - _{me o} j. gj-^up† _C |- _|an g _e j _n current, the capacitor is the lowest impedance path and thus the path along which the current is sinked. This results in an increase of the feedback voltage which subsequently deviates from the reference voltage V _ref which, due to the behaviour of the differential pair comprising Mi and M ₂ , decreases the voltage at the node 18 between the respective drain terminals of I ^ and M ₃ . The decreased voltage at this node 18 increases the bias current provided to the second error amplifier 12 due to the increased conductance of the pMOS tail transistor M ₉ . The current l _C | _0a d through the load capacitance C| _0a d undergoes a sharp increase in response to the increased current l _sink sunk into the output, but eventually reduces to zero when the feedback voltage reaches its final value.

This deviation of the feedback voltage from the reference voltage V _ref also causes the voltage at the node 24 between the respective drain terminals of M ₆ and M ₈ to increase which, due to its connection to the gate terminal of the current sinking transistor M _S ink, increases the conductivity of the sinking transistor M _S ink thus providing a direct path to ground 26 from the current source 22, i.e. the current l _MS ink through the sinking transistor M _S ink increases. This prevents the charging of the load capacitance C| _0a d and as a result limits the increase in the output voltage V _ou t due to the current being sunk into the output of the LDO voltage regulator 2.

It will be appreciated that the second error amplifier 12 provides a parallel feedback loop that only operates when a current is sunk into the output of the LDO voltage regulator 2, allowing the LDO voltage regulator 2 to continue regulating the output voltage V _ou t even under such circumstances while requiring very low bias current during normal operation (i.e. current sourcing operation) due to the connection between the pMOS tail transistor M ₉ and the node 18 in the first error amplifier 10.

Fig. 3 illustrates the behaviour of a number of voltages and currents in the LDO voltage regulator 2 in response to different values of load current l _sink (shown in Fig. 1 as a current source 22) being sunk into the output of the LDO voltage regulator 2. The various plots shown in Fig. 3 are a function of the current l _sink on a logarithmic scale. The uppermost plot simply shows a plot of the load current l _sink on a linear scale (in microamps).

The second plot shows the voltage at the node 18, the third plot shows the current l _M 9 through the pMOS tail transistor M ₉ , the fourth plot shows the current l _Ms ource through M _S0U rce, and the fifth plot shows the output voltage Vout, and all four plots are shown as a function of the current l _sink . As the sinking current l _sink increases, the current l _Ms ource through M _S0U rce decreases non-linearly until a particular threshold current phold, after which M _S0U rce is fully disabled and the current l _Ms ource falls to 0 A. When the current l _sink sinked into the output of the LDO voltage regulator 2 exceeds this value (i.e. I _sink is larger than the threshold current l _t hreshoid) , the feedback voltage Vfb increases due to the capacitor C| _0a d and thus deviates from the reference voltage V _ref as described previously. This decreases the voltage at the node 18 between the respective drain terminals of and M ₃ which increases the current l _M g through the pMOS tail transistor M ₉ . This increase in the current l _M g biases the second differential amplifier 12 which, due to the difference between the voltages and V _r ef applied to the respective gate terminals of M ₅ and M ₆ , causes M _S ink to conduct and sink the current l _sink as described previously. The increase in the conductivity of the sinking transistor M _S ink provides a direct path to ground 26 from the current source 22, which prevents the charging of the load capacitance C| _0a d and limits the increase in the output voltage V _ou t due to the current being sunk into the output of the LDO voltage regulator 2.

Thus it will be seen that embodiments of the present invention provide an improved low-dropout voltage regulator that is arranged such that a current can be sunk from the output, for example when the regulator receives leakage current from another regulator. The current that can be sunk may be orders of magnitude greater than the quiescent current of the feedback path while maintaining the desired value of the regulated output voltage. It will be appreciated by those skilled in the art that the embodiments described above are merely exemplary and are not limiting on the scope of the invention.