Title:
WAFER INSPECTION AND ANALYSIS METHOD
Document Type and Number:
WIPO Patent Application WO/2017/065445
Kind Code:
A1
Abstract:
A wafer inspection and analysis method of one embodiment comprises: a step (a) of finding a defect area by applying a first voltage having a first-range level to a wafer having a pattern; a step (b) of finding, within the found defect area, a defect point where a defect occurred by applying, to the wafer, a second voltage having a second-range level that is lower than the first-range level; and a step of obtaining defect information on at least one among defect type or defect degree through at least one among a cross-sectional or planar form of the defect point where the defect occurred, wherein the defect type comprises a deformation of the thickness of a layer forming the pattern, and in step (a) and step (b) respectively, the maximum application level of the first and the second voltages respectively is determined within a range in which the defect form of the wafer is maintained.
Inventors:
LEE WOO SUNG (KR)
Application Number:
PCT/KR2016/011117
Publication Date:
April 20, 2017
Filing Date:
October 05, 2016
Export Citation:
Assignee:
LG SILTRON INC (KR)
International Classes:
H01L21/66
Foreign References:
| KR20090071994A | 2009-07-02 | |||
| JP2005150208A | 2005-06-09 | |||
| KR19990006180A | 1999-01-25 | |||
| KR20090059237A | 2009-06-11 | |||
| KR20060079479A | 2006-07-06 |
Attorney, Agent or Firm:
PARK, Young Bok et al. (KR)
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