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Patent Searching and Data


Title:
WAFER LEVEL PACKAGE SYSTEM IN PACKAGE METHOD AND PACKAGE STRUCTURE
Document Type and Number:
WIPO Patent Application WO/2019/210617
Kind Code:
A1
Abstract:
A wafer level package system in package method and a package structure, the method comprising: providing a device wafer, comprising a first front surface (12) integrated with a plurality of first chips (11) and a first back surface (13) opposite to the first front surface (12); providing a plurality of second chips (31); forming an adhesive layer on the first front surface; patterning the adhesive layer; in the adhesive layer, forming a plurality of first via holes exposing the first front surface; disposing the second chips on the remainder of the adhesive layer, the second chips being in one-to-one correspondence with the first via holes and covering top portions of the first via holes, such that the device wafer and the second chips are bonded; etching the first back surface; in the device wafer, forming second via holes that penetrate the first via holes, the second via holes and the first via holes constituting first conductive via holes; in the first conductive via holes, forming first conductive pillars that are electrically connected to the second chips. By means of first forming the first via holes and then forming the second via holes, the problem in which the opening size of the first via holes is larger than the opening size of the second via holes is avoided, thereby improving the electrical connection performance of the first conductive pillars.

Inventors:
LIU MENGBIN (CN)
LUO HAILONG (CN)
Application Number:
PCT/CN2018/101763
Publication Date:
November 07, 2019
Filing Date:
August 22, 2018
Export Citation:
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Assignee:
NINGBO SEMICONDUCTOR INT CORP (CN)
International Classes:
H01L21/768; H01L23/538
Foreign References:
CN105140213A2015-12-09
CN105977222A2016-09-28
CN202394963U2012-08-22
CN101840871A2010-09-22
CN104600058A2015-05-06
US20080079152A12008-04-03
Attorney, Agent or Firm:
INTEBRIGHT LLP (CN)
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