Title:
WAFER-LEVEL PACKAGING METHOD FOR SEMICONDUCTOR AND SEMICONDUCTOR PACKAGE
Document Type and Number:
WIPO Patent Application WO/2020/000183
Kind Code:
A1
Abstract:
A wafer-level packaging method for a semiconductor and a semiconductor package. The wafer-level packaging method for the semiconductor comprises: providing a first wafer having one or more memory chip units, each memory chip unit having a memory array circuit and a peripheral circuit, a first scribe line being provided between adjacent memory chip units; providing a second wafer having one or more logic chip units, the area of each logic chip unit corresponding to the area of N memory chip units, N being a natural number greater than or equal to one, and a second scribe line being provided between adjacent logic chip units, the second scribe line matching the first scribe line at the periphery of the N memory chip units; and bonding the first wafer and the second wafer to correspondingly match the logic chip units with N memory chip units. The wafer-level packaging method for the semiconductor expands the application range of a package of a memory wafer.
Inventors:
ZHAO LIXIN (CN)
Application Number:
PCT/CN2018/092885
Publication Date:
January 02, 2020
Filing Date:
June 26, 2018
Export Citation:
Assignee:
GALAXYCORE SHANGHAI LTD CORP (CN)
International Classes:
H01L21/60; H01L25/16
Foreign References:
| CN103985648A | 2014-08-13 | |||
| CN102117800A | 2011-07-06 | |||
| CN205723498U | 2016-11-23 |
Attorney, Agent or Firm:
KING & WOOD MALLESONS (CN)
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