Title:
WAFER POLISHING METHOD AND WAFER POLISHING APPARATUS
Document Type and Number:
WIPO Patent Application WO/2017/077691
Kind Code:
A1
Abstract:
A wafer polishing method of the present invention is characterized by having: a measuring step for measuring the depth PDt of a recessed section of a template after taking out a polishing-completed wafer, said measuring step being to be performed after an unloading step and prior to a loading step for holding a wafer to be polished next; a calculating step for calculating a difference ∆PD between the thus measured depth PDt of the recessed section, and the depth PD0 of the recessed section of the template before the template is used in the polishing; and an adjusting step for adjusting, in accordance with the thus calculated difference ∆PD, the polishing conditions of the wafer to be polished next. Consequently, the wafer polishing method and a wafer polishing apparatus, whereby wafer flatness fluctuation due to numerical value fluctuation of the pocket depth of the template can be adjusted, are provided.
Inventors:
SATO KAZUYA (JP)
HASHIMOTO HIROMASA (JP)
KAMIHAMA NAOKI (JP)
HASHIMOTO HIROMASA (JP)
KAMIHAMA NAOKI (JP)
Application Number:
PCT/JP2016/004596
Publication Date:
May 11, 2017
Filing Date:
October 17, 2016
Export Citation:
Assignee:
SHINETSU HANDOTAI KK (JP)
International Classes:
B24B37/34; B24B49/12; H01L21/304
Foreign References:
| JP2012076157A | 2012-04-19 | |||
| JP2004239718A | 2004-08-26 | |||
| JP2014004675A | 2014-01-16 | |||
| JP2014184511A | 2014-10-02 |
Attorney, Agent or Firm:
YOSHIMIYA, Mikio et al. (JP)
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