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Title:
WAFER-SCALE MANUFACTURING OF JOSEPHSON JUNCTIONS FOR QUBITS
Document Type and Number:
WIPO Patent Application WO/2019/117929
Kind Code:
A1
Abstract:
One aspect of the present disclosure proposes a method of fabricating quantum circuit assemblies that include Josephson Junctions. The method is based on providing an opening in a stack that includes an upper layer of a substrate, a layer of a first conductive material thereon, and a support layer over the conductive layer. The method further includes depositing a liner of a tunnel barrier material within the opening and providing a layer of a second conductive material within at least a portion of the opening lined with the liner. In this way, a Josephson Junction is formed, where the first conductive material forms the first electrode, the second conductive material forms the second electrode, and a portion of the liner forms the tunnel barrier. Such a method may be efficiently used in large-scale manufacturing and may result in Josephson Junctions having an improved performance compared to Josephson Junctions fabricated using existing techniques.

Inventors:
GEORGE, Hubert C. (7016 NW Eleanor Avenue, Portland, Oregon, 97229, US)
LAMPERT, Lester (17564 NW Springville Rd, Unit 4Portland, Oregon, 97229, US)
CLARKE, James S. (5676 NW 204th Place, Portland, Oregon, 97229, US)
PILLARISETTY, Ravi (1330 SW 3rd Ave, Apt. 1103Portland, Oregon, 97201, US)
YOSCOVITS, Zachary R. (16145 NW Schendel Ave, Unit 21BBeaverton, Oregon, 97006, US)
THOMAS, Nicole K. (1125 NW 12th Ave, Apt. 309Portland, Oregon, 97209, US)
ROBERTS, Jeanette M. (17898 NW Pumpkin Ridge Road, North Plains, Oregon, 97133, US)
CAUDILLO, Roman (2305 SE 16th Avenue, Portland, Oregon, 97214, US)
SINGH, Kanwaljit (Wierdsmaplein 41, 3072 MJ Rotterdam, Rotterdam, NL)
MICHALAK, David J. (1511 SW Park Ave, Apt. 811Portland, Oregon, 97201, US)
Application Number:
US2017/066551
Publication Date:
June 20, 2019
Filing Date:
December 15, 2017
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
INTEL CORPORATION (2200 Mission College Boulevard, Santa Clara, California, 95054-1549, US)
International Classes:
H01L39/22; H01L39/02; H01L39/24
Domestic Patent References:
WO2017131831A22017-08-03
Foreign References:
JPS59124781A1984-07-18
US20080051292A12008-02-28
US6384424B12002-05-07
US6004907A1999-12-21
Attorney, Agent or Firm:
HARTMANN, Natalya (Patent Capital Group, 2816 Lago Vista LaneRockwall, Texas, 75032, US)
Download PDF:
Claims:
Claims:

1. A quantum circuit assembly comprising:

a Josephson Junction over a substrate, the Josephson Junction comprising a first electrode, a second electrode, and a tunnel barrier layer between the first electrode and the second electrode, wherein the tunnel barrier layer is at an angle less than 50 degrees from a plane

perpendicular to the substrate.

2. The quantum circuit assembly according to claim 1, wherein the Josephson Junction is a first Josephson Junction and the quantum circuit assembly further comprises a second Josephson Junction comprising a first electrode, a second electrode, and a tunnel barrier layer between the first electrode and the second electrode.

3. The quantum circuit assembly according to claim 2, wherein the tunnel barrier layer of the second Josephson Junction and the tunnel barrier layer of the first Josephson Junction are symmetric with respect to a plane that is perpendicular to the substrate and is in the middle between the tunnel barrier layer of the second Josephson Junction and the tunnel barrier layer of the first Josephson Junction.

4. The quantum circuit assembly according to claim 2, wherein the tunnel barrier layer of the second Josephson Junction is at an angle less than 50 degrees from the plane perpendicular to the substrate.

5. The quantum circuit assembly according to claim 2, wherein the first Josephson Junction and the second Josephson Junction form a superconducting quantum interference device (SQUID).

6. The quantum circuit assembly according to any one of claims 2-5, wherein the second electrode of the first Josephson Junction is electrically isolated from the second electrode of the second Josephson Junction.

7. The quantum circuit assembly according to any one of claims 2-5, wherein the second electrode of the first Josephson Junction and the second electrode of the second Josephson Junction is a single electrode.

8. The quantum circuit assembly according to claim 7, wherein the tunnel barrier layer of the first Josephson Junction is adjacent to a first sidewall of the single electrode.

9. The quantum circuit assembly according to claim 7, wherein the tunnel barrier layer of the second Josephson Junction is adjacent to a second sidewall of the single electrode.

10. The quantum circuit assembly according to any one of claims 1-5, wherein the first electrode is a portion of a layer of an electrically conductive material, the layer being parallel to the substrate.

11. The quantum circuit assembly according to any one of claims 1-5, wherein a thickness of the tunnel barrier layer is between 1 and 8 nanometers.

12. A method of fabricating a quantum circuit assembly comprising a Josephson Junction that includes a first electrode, a second electrode, and a tunnel barrier layer between the first electrode and the second electrode, the method comprising:

providing a first layer over a substrate, the first layer comprising a first electrically conductive material;

providing a support layer over the first layer;

forming an opening in the support layer, the opening extending through the first layer; depositing a liner of a tunnel barrier material within the opening; and

providing a second electrically conductive material within at least a portion of the opening having the liner,

wherein the first electrically conductive material forms the first electrode, the second electrically conductive material forms the second electrode, and a portion of the liner forms the tunnel barrier layer of the Josephson Junction.

13. The method according to claim 12, wherein the opening extends past the first layer by a depth of at least 10% of a thickness of the support layer.

14. The method according to claim 12, wherein a depth of the opening is between 40 and 400 nanometers.

15. The method according to claim 12, wherein a width of the opening is between 20 and 300 nanometers.

16. The method according to claim 12, wherein the opening is a trench, and a length of the trench is between 20 and 300 nanometers.

17. The method according to any one of claims 12-16, wherein a thickness of the first layer is between 2 and 40 nanometers.

18. The method according to any one of claims 12-16, wherein the first layer is patterned into a strip, where a width of the strip of the first layer is between 5 and 40 nanometers.

19. The method according to any one of claims 12-16, wherein a thickness of the support layer is between 10 and 300 nanometers.

20. The method according to any one of claims 12-16, wherein depositing the liner comprises performing atomic layer deposition to conformally deposit the tunnel barrier material within the opening.

21. The method according to any one of claims 12-16, wherein a thickness of the liner is between 1 and 8 nanometers.

22. A quantum integrated circuit (1C) package, comprising:

a qubit die comprising: a substrate, and

one or more qubits, where at least one qubit comprises a Josephson Junction over the substrate, the Josephson Junction comprising a first electrode, a second electrode, and a tunnel barrier layer between the first electrode and the second electrode, and where the tunnel barrier layer is at an angle less than 50 degrees from a plane perpendicular to the substrate; and

a further 1C element, where the qubit die is coupled to the further 1C element by one or more first-level interconnects.

23. The quantum 1C package according to claim 22, wherein the further 1C element is one of an interposer, a circuit board, a flexible board, or a package substrate.

24. The quantum 1C package according to claims 22 or 23, wherein the one or more qubits comprise a plurality of superconducting qubits, and wherein at least of a first and a second of the plurality of superconducting qubits are coupled by a coupling resonator.

25. The quantum 1C package according to claims 22 or 23, wherein the Josephson Junction is a first Josephson Junction and the quantum circuit assembly further comprises a second Josephson Junction comprising a first electrode, a second electrode, and a tunnel barrier layer between the first electrode and the second electrode, and wherein the first Josephson Junction and the second Josephson Junction form a superconducting quantum interference device (SQUID).

Description:
WAFER-SCALE MANUFACTURING OF JOSEPHSON JUNCTIONS FOR QUBITS

Technical Field

[0001] This disclosure relates generally to the field of quantum computing, and more specifically, to Josephson Junctions for use in quantum circuits and to methods of fabrication thereof.

Background

[0002] Quantum computing refers to the field of research related to computation systems that use quantum-mechanical phenomena to manipulate data. These quantum-mechanical phenomena, such as superposition (in which a quantum variable can simultaneously exist in multiple different states) and entanglement (in which multiple quantum variables have related states irrespective of the distance between them in space or time), do not have analogs in the world of classical computing.

[0003] Quantum computers use so-called quantum bits, referred to as qubits (both terms "bits" and "qubits" often interchangeably refer to the values that they hold as well as to the actual devices that store the values). Similar to a bit of a classical computer, at any given time, a qubit can be either 0 or 1. However, in contrast to a bit of a classical computer, a qubit can also be 0 and 1 at the same time, which is a result of superposition of quantum states - a uniquely quantum-mechanical phenomenon. Entanglement also contributes to the unique nature of qubits in that input data to a quantum processor can be spread out among entangled qubits, allowing manipulation of that data to be spread out as well: providing input data to one qubit results in that data being shared to other qubits with which the first qubit is entangled.

[0004] Compared to well-established and thoroughly researched classical computers, quantum computing is still in its infancy, with the highest number of qubits in a solid-state quantum processor currently being below 100. One of the main challenges resides in protecting qubits from

decoherence so that they can stay in their information-holding states long enough to perform the necessary calculations and read out the results.

Brief Description of the Drawings

[0005] Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.

[0006] FIG. 1 provides a schematic illustration of an exemplary superconducting quantum circuit, according to some embodiments of the present disclosure.

[0007] FIGS. 2A-2C provide a schematic illustration of a photoresist mask provided over a substrate for fabricating a Josephson Junction using a double-angle shadow evaporation approach. [0008] FIGS. 3A-3C provide a schematic illustration of fabricating Josephson Junctions using a conventional double-angle shadow evaporation approach.

[0009] FIG. 4 provides a flow chart of a trench method for fabricating Josephson Junctions for quantum circuit assemblies, according to some embodiments of the present disclosure.

[0010] FIGS. 5A-5FI are cross-sections illustrating various exemplary stages in the manufacture of a quantum circuit assembly using the trench method of FIG. 4, in accordance with various embodiments of the present disclosure.

[0011] FIGS. 6A and 6B are top views of a wafer and dies that may include one or more of quantum circuit assemblies disclosed herein.

[0012] FIG. 7 is a cross-sectional side view of a device assembly that may include one or more of quantum circuit assemblies disclosed herein.

[0013] FIG. 8 is a block diagram of an exemplary quantum computing device that may include one or more of quantum circuit assemblies disclosed herein, in accordance with various embodiments.

Detailed Description

Overview

[0014] As briefly described above, quantum computing, or quantum information processing, refers to the field of research related to computation systems that use quantum-mechanical phenomena to manipulate data. One example of quantum-mechanical phenomena is the principle of quantum superposition, which asserts that any two or more quantum states can be added together, i.e. superposed, to produce another valid quantum state, and that any quantum state can be represented as a sum of two or more other distinct states. Quantum entanglement is another example of quantum-mechanical phenomena. Entanglement refers to groups of particles being generated or interacting in such a way that the state of one particle becomes intertwined with that of the others. Furthermore, the quantum state of each particle cannot be described independently. Instead, the quantum state is given for the group of entangled particles as a whole. Yet another example of quantum-mechanical phenomena is sometimes described as a "collapse" because it asserts that when we observe (measure) particles, we unavoidably change their properties in that, once observed, the particles cease to be in a state of superposition or entanglement (i.e. by trying to ascertain anything about the particles, we collapse their state).

[0015] Put simply, superposition postulates that a given particle can be simultaneously in two states, entanglement postulates that two particles can be related in that they are able to instantly coordinate their states irrespective of the distance between them in space and time, and collapse postulates that when one observes a particle, one unavoidably changes the state of the particle and its' entanglement with other particles. These unique phenomena make manipulation of data in quantum computers significantly different from that of classical computers (i.e. computers that use phenomena of classical physics). Therefore, both the industry and the academics continue to focus on a search for new and improved physical systems whose functionality could approach that expected of theoretically designed qubits.

[0016] Physical systems for implementing qubits that have been explored until now include e.g. superconducting qubits, single trapped ion qubits, Silicon (Si) quantum dot qubits, photon polarization qubits, etc.

[0017] Out of the various physical implementations of qubits listed above, superconducting qubits are promising candidates for building a quantum computer. All of superconducting qubits operate based on the Josephson effect, which refers to a macroscopic quantum phenomenon of supercurrent, i.e. a current that, due to zero electrical resistance, flows indefinitely long without any voltage applied, across a device known as a Josephson Junction.

[0018] In general, a Josephson Junction includes two superconductors coupled by a so-called weak link that weakens the superconductivity between the two superconductors. In conventional qubit scenarios, a weak link of a Josephson Junction is implemented by providing a thin layer of an insulating material, typically referred to as a "barrier" or a "tunnel barrier," sandwiched, in a stack like arrangement, between two layers of superconductor, which two superconductors typically referred to, respectively, as a "bottom/base electrode" and a "top electrode" of the Josephson Junction. Josephson Junction provides a non-linear inductive element to the circuit and allows the qubit to become an anharmonic oscillator. The anharmonicity is determined by the ratio of the charging energy, which stems from the total capacitance between a first and second element of the qubit, and the Josephson energy of the non-linear inductive element (e.g., Josephson Junction). The anharmonicity is what allows the state of the qubit to be controlled to a high level of fidelity. In addition to controlling the anharmonicity, the charging and Josephson energies also control the qubit frequency.

[0019] A conventional method for fabricating such Josephson Junctions for quantum circuits is a so- called "double-angle shadow evaporation" method (also sometimes referred to as a "hanging resist" method), where the name of the method reflects the fact that the method involves metal deposition, typically carried out by metal evaporation, at two different angles of incidence with respect to the substrate (hence, double-angle). The name further reflects the fact that metal deposition is performed through a hanging photoresist mask which casts a shadow on at least a part of the substrate, obscuring metal deposition on that part (hence, shadow evaporation/evaporation). While this method may be adequate for fabricating qubit devices with Josephson Junctions in a lab environment, the method includes steps which are not suitable for manufacturing on the larger wafer sizes used in the semiconductor industry.

[0020] Josephson Junctions are integral building blocks in superconducting quantum circuits where they form the basis of quantum circuit elements that can approximate functionality of theoretically designed qubits. Therefore, improvements with respect to fabricating Josephson Junctions for use in quantum circuit assemblies are always desirable. In particular, it would be desirable to have methods for fabricating Josephson Junctions that have adequate performance and can be manufactured using wafer-scale manufacturing techniques.

[0021] Embodiments of the present disclosure propose methods of fabricating quantum circuit assemblies that include Josephson Junctions, as well as qubit devices comprising Josephson

Junctions. In one aspect of the present disclosure, a method of fabricating a quantum circuit assembly with at least one Josephson Junction is disclosed. The disclosed method proposes building a Josephson Junction based on an opening in a stack that includes an upper layer of a substrate, a layer of a first electrically conductive, preferably superconductive, material thereon, and a support layer over the conductive layer. In some implementations, the opening can be trench-like, thus giving rise to the name "trench method" used herein to describe this method. The trench method further includes depositing a liner of a tunnel barrier material within the opening and providing a layer of a second electrically conductive, preferably superconductive, material (which can be the same or different from the first) within at least a portion of the opening lined with the liner. In this way, a Josephson Junction is formed, where the first conductive/superconductive material forms the first electrode, the second conductive/superconductive material forms the second electrode, and a portion of the liner forms the tunnel barrier. Such a method may be efficiently used in large-scale manufacturing, providing a substantial improvement with respect to conventional approaches, such as e.g. double-angle shadow evaporation approach, which include fabrications steps which are not suitable for implementing with larger wafer sizes used by leading edge device manufactures. In addition, such a method may result in Josephson Junctions having an improved performance compared to Josephson Junctions fabricated using existing techniques, e.g. because it may help decrease amount of spurious (i.e. unintentional and undesirable) two-level systems (TLS's), thought to be the dominant source of superconducting qubit decoherence, in the vicinity of Josephson Junctions. Another advantage of this method is that it offers improved control of the Josephson Junction's dimensions: the atomic control of tunnel junction liner, and the thickness and width of the first conductive electrode layer which define the area of the junction.

[0022] In order to provide substantially lossless connectivity to, from, and between the qubits, some or all of the electrically conductive portions of various quantum circuit elements described herein (e.g. electrodes of Josephson Junctions and leads to such electrodes) may be made from one or more superconductive materials. However, some or all of these electrically conductive portions could be made from electrically conductive materials which are not superconductive. In the following, unless specified otherwise, reference to an electrically conductive material or circuit element implies that a superconductive material can be used, and vice versa (i.e. reference to a superconductor implies that a conductive material which is not superconductive may be used). Furthermore, any material described herein as a "superconductive/superconducting material" may refer to one or more materials, including alloys of materials, which exhibit superconducting behavior at typical qubit operating conditions (e.g. materials which exhibit superconducting behavior at very low temperatures at which qubits typically operate), but which may not exhibit such behavior at higher temperatures (e.g. at room temperatures). Examples of such materials include aluminum (Al), niobium (Nb), niobium nitride (NbN), titanium nitride (TiN), niobium titanium nitride (NbTiN), indium (In), and molybdenum rhenium (MoRe), all of which are particular types of superconductors at qubit operating temperatures, as well as their alloys.

[0023] While some descriptions are provided with reference to superconducting qubits, in particular to transmons, a particular class of superconducting qubits, at least some teachings of the present disclosure may be applicable to implementations of any qubits, including superconducting qubits other than transmons and/or including qubits other than superconducting qubits, which may employ non-linear inductive elements, such as Josephson Junctions, all of which implementations are within the scope of the present disclosure. For example, the quantum circuit device assemblies described herein may be used in hybrid semiconducting-superconducting quantum circuits.

[0024] In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.

[0025] In the drawings, some schematic illustrations of exemplary structures of various devices and assemblies described herein may be shown with precise right angles and straight lines, but it is to be understood that such schematic illustrations may not reflect real-life process limitations which may cause the features to not look so "ideal" when any of the structures described herein are examined using e.g. scanning electron microscopy (SEM) images or transmission electron microscope (TEM) images. In such images of real structures, possible processing defects could also be visible, such as e.g. not-perfectly straight edges of materials, tapered vias or other openings, inadvertent rounding of corners or variations in thicknesses of different material layers, occasional screw, edge, or combination dislocations within the crystalline region, and/or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but that are common within the field of device fabrication.

[0026] Various operations may be described as multiple discrete actions or operations in turn in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment.

Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.

[0027] For the purposes of the present disclosure, the phrase "A and/or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term "between," when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. As used herein, the notation "A/B/C" means (A), (B), and/or (C).

[0028] The description uses the phrases "in an embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as "above," "below," "top," "bottom," and "side"; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. The accompanying drawings are not necessarily drawn to scale. Unless otherwise specified, the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

[0029] The terms "over," "under," "between," and "on" as used herein refer to a relative position of one material layer or component with respect to other layers or components. For example, one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer "on" a second layer is in direct contact with that second layer. Similarly, unless explicitly stated otherwise, one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers. [0030] In the following detailed description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. For example, the terms "oxide," "carbide," "nitride," etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, etc. The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- 20% of a target value based on the context of a particular value as described herein or as known in the art. Similarly, terms indicating orientation of various elements, such as e.g. "coplanar," "perpendicular,"

"orthogonal," "parallel," or any other angle between the elements, generally refer to being within +/- 5-10% of a target value based on the context of a particular value as described herein or as known in the art. Furthermore, as used herein, terms indicating what may be considered an idealized behavior, such as e.g. "superconducting" or "lossless", are intended to cover functionality that may not be exactly ideal but is within acceptable margins for a given application. For example, a certain level of loss, either in terms of non-zero electrical resistance or non-zero amount of spurious TLS's may be acceptable such that the resulting materials and structures may still be referred to by these "idealized" terms. Specific values associated with an acceptable level of loss are expected to change over time as fabrication precision will improve and as fault-tolerant schemes may become more tolerant of higher losses, all of which are within the scope of the present disclosure.

[0031] Still further, while the present disclosure may include references to microwave signals, this is done only because current qubits are designed to work with such signals because the energy in the microwave range is higher than thermal excitations at the temperature that qubits are typically operated at. In addition, techniques for the control and measurement of microwaves are well known. For these reasons, typical frequencies of qubits are in 1-10 GFIz, e.g. in 4-10 GFIz, range, in order to be higher than thermal excitations, but low enough for ease of microwave engineering. Flowever, advantageously, because excitation energy of qubits is controlled by the circuit elements, qubits can be designed to have any frequency. Therefore, in general, qubits could be designed to operate with signals in other ranges of electromagnetic spectrum and embodiments of the present disclosure could be modified accordingly. All of these alternative implementations are within the scope of the present disclosure.

Quantum computing and Josephson Junctions

[0032] FIG. 1 provides a schematic illustration of an exemplary superconducting quantum circuit 100 that may include any of the quantum circuit assemblies described herein.

[0033] As shown in FIG. 1, an exemplary superconducting quantum circuit 100 may include two or more qubits 102 (reference numerals following after a dash, such as e.g. qubit 102-1 and 102-2 indicate different instances of the same or analogous element). Each of the superconducting qubits 102 may include one or more Josephson Junctions 104 electrically connected to one or more other circuit elements 106, which, in combination with the Josephson Junction(s) 104, form a non-linear circuit providing a unique two-level quantum state for the qubit.

[0034] Typically, when a qubit employs only one Josephson Junction, a frequency of the qubit cannot be changed substantially beyond what is defined by the design unless one of the qubit capacitive elements is tunable. Employing two or more Josephson Junctions 104, e.g. arranged in a so-called superconducting quantum interference device (SQUID), allows controlling the frequency of the qubit, which, in turn, allows greater control as to whether and when the qubit interacts with other components of a quantum circuit, e.g. with other qubits. In general, a SQUID of a

superconducting qubit includes a pair of Josephson Junctions and a loop of a conductive, typically superconductive material (i.e. a superconducting loop), connecting a pair of Josephson Junctions. Applying a net magnetic field in a certain orientation to the SQUID loop of a superconducting qubit allows controlling the frequency of the qubit. In particular, applying magnetic field to the SQUID region of a superconducting qubit is generally referred to as a "flux control" of a qubit, and the magnetic field is generated by providing direct current (DC) or a pulse of current through an electrically conductive or superconductive line generally referred to as a "flux bias line" (also known as a "flux line" or a "flux coil line"). By providing flux bias lines sufficiently close to SQUIDs, magnetic fields generated as a result of currents running through the flux bias lines extend to the SQUIDs, thus tuning qubit frequencies.

[0035] Turning back to FIG. 1, within each qubit 102, the one or more Josephson Junctions 104 may be directly electrically connected to one or more other circuit elements 106, which, in combination with the Josephson Junction(s) 104, form a non-linear oscillator circuit providing multi-level quantum system where the first two to three levels define the qubit under normal operation. The circuit elements 106 could be e.g. shunt capacitors, superconducting loops of a SQUID, electrodes for setting an overall capacitance of a qubit, or/and ports for capacitively coupling the qubit to one or more of a readout resonator, a coupling resonator, and a direct microwave drive line, or electromagnetically coupling the qubit to a flux bias line.

[0036] As also shown in FIG. 1, an exemplary quantum circuit 100 typically includes a plurality of non-resonant transmission lines 108, and a plurality of resonators 110. The non-resonant transmission lines 108 are typically used for providing microwave signals to different quantum circuit elements and components, such as e.g. various control lines for various qubits, and may be considered to implement external control of qubits. For example, for superconducting qubits, examples of the non-resonant transmission lines 108 include flux bias lines, microwave lines, and readout lines. On the other hand, the resonators 110 may be viewed as implementing internal control lines for qubit. For superconducting qubits, examples of the resonators 110 include coupling and readout resonators.

[0037] In general, a resonator 110 of a quantum circuit differs from a non-resonant microwave transmission line 108 in that a resonator is deliberately designed to support resonant oscillations (i.e. resonance), under certain conditions. In contrast, non-resonant transmission lines may be similar to conventional microwave transmission lines in that they are designed to avoid resonances, especially resonances at frequencies/wavelengths close to the resonant frequencies/wavelengths of any resonant object used in the quantum computing circuits, e.g., qubits, bus resonators, or readout resonators in the proximity of such non-resonant lines. Once non-resonant transmission lines are manufactured, some of them may inadvertently support some resonances, but, during its design, efforts are taken to minimize resonances, standing waves, and reflected signals as much as possible, so that all of the signals can be transmitted through these lines without, or with as little resonance as possible.

[0038] On-chip capacitive coupling between quantum or control elements can be achieved either through use of coupling components such as a coupling component on a neighboring qubit, a lumped element capacitor, a lumped element resonator, or a transmission line segment. A transmission line segment is a resonator that is made by employing fixed boundary conditions, and these boundary conditions control the frequencies/wavelengths which will resonate within a given transmission line segment used to implement a resonator. In order to satisfy boundary conditions for resonance, each end of a transmission line segment resonator can be either a node, if it is shorted to ground (e.g. where one end of the transmission line segment structure is electrically connected to a ground plane), or an antinode, if it is capacitively or inductively coupled to ground or to another quantum circuit element. Thus, resonators 110 differ from non-resonant microwave transmission lines 108 in how these lines are terminated at the relevant ends. A line used to route a signal on a substrate, i.e. one of the non-resonant transmission lines 108, typically extends from a specific source, e.g. a bonding pad or another type of electrical connection to a source, to a specific load (e.g. a short circuit proximate to SQUID loop, a quantum dot device, another bonding pad, or another electrical connection to a load). In other words, non-resonant transmission lines 108 terminate with direct electrical connections to sources, ground sinks, and/or loads. On the other hand, a transmission line resonator is typically composed of a piece of transmission line terminated with either two open circuits (in case of a half-wavelength resonator) or an open and a short circuit (in case of a quarter-wavelength resonator). In this case, for a desired resonant frequency, transmission line length may e.g. be a multiple of a microwave wavelength divided by 2 or 4, respectively. However, other terminations are possible, for example capacitive or inductive, and in this case the required line length to support resonance will be different from that identified above. For example, capacitive terminations may be used for resonators which are coupled to qubits, to a feedline, line, or to another resonator by a capacitive interaction.

[0039] Besides line termination by capacitive or inductive coupling or a short circuit, in order to support resonant oscillations, transmission line segments of the resonators 110 need to be of a specific length that can support such oscillations. That is why, often times, resonators 110 may be laid out on a substrate longer than the actual distance would require (i.e. a non-resonant transmission line would typically be laid out to cover the distance in the most compact manner possible, e.g. without any curves, wiggles, or excess length, while a resonator may need to have curves, wiggles, and be longer than the shortest distance between the two elements the resonator is supposed to couple in order to be sufficiently long to support resonance).

[0040] One type of the resonators 110 used with superconducting qubits are so-called coupling resonators (also known as "bus resonators"), which allow one method to couple different qubits together in order to realize quantum logic gates. These types of resonators are analogous in concept and have analogous underlying physics as readout resonators, except that a coupling or "bus" resonator involves only capacitive couplings between two or more qubits whereas a readout resonator involves capacitive coupling between two or more qubits and a feedline. A coupling resonator may be implemented as a microwave transmission line segment that includes capacitive or inductive connections to ground on both sides (e.g. a half-wavelength resonator), which results in oscillations (resonance) within the transmission line. While the ends of a coupling resonator have open circuits to the ground, each side of a coupling resonator is coupled, either capacitively or inductively, to a respective (i.e. different) qubit by being in the appropriate location and sufficient proximity to the qubit. Because different regions of a coupling resonator have coupling with a respective different qubit, the two qubits are coupled together through the coupling resonator.

Thus, coupling resonators may be employed for implementing logic gates.

[0041] Another type of the resonators 110 used with superconducting qubits are so-called readout resonators, which may be used to read the state(s) of qubits. In some embodiments, a

corresponding readout resonator may be provided for each qubit. A readout resonator, similar to the bus coupling resonator, is a transmission line segment. On one end it may have an open circuit connection to ground as well as any capacitively or inductively coupled connections to other quantum elements or a non-resonant microwave feedline. On the other end, a readout resonator may either have a capacitive connection to ground (for a half-wavelength resonator) or may have a short circuit to the ground (for a quarter-wavelength resonator), which also results in oscillations within the transmission line, with the resonant frequency of the oscillations being close to the frequency of the qubit. A readout resonator is coupled to a qubit by being in the appropriate location and sufficient proximity to the qubit, again, either through capacitive or inductive coupling. Due to a coupling between a readout resonator and a qubit, changes in the state of the qubit result in changes of the resonant frequency of the readout resonator. In turn, changes in the resonant frequency of the readout resonator can be read externally via connections which lead to external electronics e.g. wire or solder bonding pads.

[0042] For the non-resonant transmission lines 108, some descriptions of flux bias lines were provided above and, in the interests of brevity are not repeated here. In general, running a current through a flux bias line, provided e.g. from a wirebonding pads or any other connection element, allows tuning (i.e. changing) the frequency of a corresponding qubit 102 to which a given flux bias line is connected. As a result of running the current in a given flux bias line, magnetic field is created around the line. If such a magnetic field is in sufficient proximity to a given qubit 102, e.g. by a portion of the flux bias line being provided next (sufficiently close) to the qubit 102, the magnetic field couples to the qubit, thereby changing the spacing between the energy levels of the qubit.

This, in turn, changes the frequency of the qubit since the frequency is directly related to the spacing between the energy levels via the equation E=hv (Planck's equation), where E is the energy (in this case the energy difference between energy levels of a qubit), h is the Planck's constant and v is the frequency (in this case the frequency of the qubit). As this equation illustrates, if E changes, then v changes. Different currents and pulses of currents can be sent down each of the flux lines allowing for independent tuning of the various qubits.

[0043] Typically, the qubit frequency may be controlled in order to bring the frequency either closer to or further away from another resonant item, for example a coupling resonator or a coupled neighbor qubit, to implement multi-qubit interactions, as may be desired in a particular setting.

[0044] For example, if it is desirable that a first qubit 102-1 and a second qubit 102-2 interact, via a coupling resonator (i.e. an example of the resonators 110) connecting these qubits, then both qubits 102 may need to be tuned to be at nearly the same frequency or a detuning equal, or nearly equal, to the anharmonicity. One way in which such two qubits could interact is that, if the frequency of the first qubit 102-1 is tuned very close to the resonant frequency of the coupling resonator, the first qubit can, when in the excited state, relax back down to the ground state by emitting a photon (similar to how an excited atom would relax) that would resonate within the coupling resonator. If the second qubit 102-2 is also at this energy (i.e. if the frequency of the second qubit is also tuned very close to the resonant frequency of the coupling resonator), then it can absorb the photon emitted from the first qubit, via the coupling resonator coupling these two qubits, and be excited from its ground state to an excited state. Thus, the two qubits interact, or are entangled, in that a state of one qubit is controlled by the state of another qubit. In other scenarios, two qubits could interact via exchange of virtual photons, where these three elements do not have to be tuned to be at the same frequency with one another. In general, two or more qubits could be configured to interact with one another by tuning their frequencies to specific values or ranges.

[0045] On the other hand, it may sometimes be desirable that two qubits coupled by a coupling resonator do not interact, i.e. the qubits are independent. In this case, by applying magnetic flux, by means of controlling the current in the appropriate flux bias line, to one qubit it is possible to cause the frequency of the qubit to change enough so that the photon it could emit no longer has the right frequency to resonate on the coupling resonator or on the neighboring qubit via a virtual photon transfer through the bus. If there is nowhere for such a frequency-detuned photon to go, the qubit will be better isolated from its surroundings and will live longer in its current state. Thus, in general, two or more qubits could be configured to reduce interactions with one another by tuning their frequencies to specific values or ranges.

[0046] The state(s) of each qubit 102 may be read by way of its corresponding readout resonator of the resonators 110. As explained below, the state of qubit 102 induces a shift in the resonant frequency in the associated readout resonator. This shift in resonant frequency can then be read out using its coupling to a feedline. To that end, an individual readout resonator may be provided for each qubit. As described above, a readout resonator may be a transmission line segment that includes a capacitive connection to ground on one side and is either shorted to the ground on the other side (for a quarter-wavelength resonator) or has a capacitive connection to ground (for a half wavelength resonator), which results in oscillations within the transmission line (resonance) that depends upon the state of a proximal qubit. A readout resonator may be coupled to its

corresponding qubit 102 by being in an appropriate location and sufficient proximity to the qubit, more specifically in an appropriate location and sufficient proximity to a first element (or "island) of the qubit 102 that capacitively couples to the readout resonator, when the qubit is implemented as a transmon. Due to a coupling between the readout resonator and the qubit, changes in the state of the qubit result in changes of the resonant frequency of the readout resonator. In turn, by ensuring that the readout resonator is in sufficient proximity to a corresponding microwave feedline, changes in the resonant frequency of the readout resonator induce changes in the transmission coefficients of the microwave feedline, detected externally.

[0047] A coupling resonator, or, more generally, a coupling component, allows coupling different qubits together, e.g. as described above, in order to realize quantum logic gates. A coupling component could be comprised of a coupling component on a neighboring qubit, a lumped element capacitor, a lumped element resonator, or a coupling transmission line segment. A coupling transmission line segment (e.g., coupling resonator or bus resonator) is similar to a readout resonator in that it is a transmission line segment that includes capacitive connections to various objects (e.g., qubits, ground, etc.) on both sides (i.e. a half-wavelength resonator), which also results in oscillations within the coupling resonator. Each side/end of a coupling component is coupled (again, either capacitively or inductively) to a respective qubit by being in appropriate location and sufficient proximity to the qubit, namely in sufficient proximity to a first element (or "island") of the qubit that capacitively couples to the coupling component, when the qubit is implemented as a transmon. Because each side of a given coupling component has coupling with a respective different qubit, the two qubits are coupled together through the coupling component. Thus, coupling components may be employed in order to implement multi-qubit interactions.

[0048] In some implementations, a microwave line may be used to not only readout the state of the qubits as described above, but also to control the state of the qubits. When a single microwave line is used for this purpose, the line operates in a half-duplex mode where, at some times, it is configured to readout the state of the qubits, and, at other times, it is configured to control the state of the qubits. In other implementations, microwave lines may be used to only readout the state of the qubits as described above, while separate drive lines, may be used to control the state of the qubits. In such implementations, microwave lines used for readout may be referred to as readout lines, while microwave lines used for controlling the state of the qubits may be referred to as drive lines. Drive lines may control the state of their respective qubits 102 by providing to the qubits a microwave pulse at the qubit frequency, which in turn stimulates (i.e. triggers) a transition between the states of the qubit. By varying the length of this pulse, a partial transition can be stimulated, giving a superposition of the states of the qubit.

[0049] Flux bias lines, microwave lines, readout lines, drive lines, coupling components, and readout resonators, such as e.g. those described above, together form interconnects for supporting propagation of microwave signals. Further, any other connections for providing direct electrical interconnection between different quantum circuit elements and components, such as e.g.

connections from electrodes of Josephson Junctions to plates of the capacitors or to

superconducting loops of SQUIDs or connections between two ground lines of a particular transmission line for equalizing electrostatic potential on the two ground lines, may also be referred to as interconnects. Still further, the term "interconnect" may also be used to refer to elements providing electrical interconnections between quantum circuit elements and components and non quantum circuit elements, which may also be provided in a quantum circuit, as well as to electrical interconnections between various non-quantum circuit elements provided in a quantum circuit. Examples of non-quantum circuit elements which may be provided in a quantum circuit may include various analog and/or digital systems, e.g. analog to digital converters, mixers, multiplexers, amplifiers, etc.

[0050] In various embodiments, various conductive circuit elements of supporting circuitry included in a quantum circuit such as the quantum circuit 100 could have different shapes and layouts. In general, the term "line" as used herein in context of signal lines or transmission lines does not imply straight lines, unless specifically stated so. For example, some resonant or non-resonant transmission lines or parts thereof (e.g. conductor strips of resonant or non-resonant transmission lines) may comprise more curves, wiggles, and turns while other resonant or non-resonant transmission lines or parts thereof may comprise less curves, wiggles, and turns, and some transmission lines or parts thereof may comprise substantially straight lines. At least some of the Josephson Junctions 104 included within the qubits 102 shown in FIG. 1 may be fabricated according to various embodiments of the improved method described herein.

[0051] The qubits 102, the non-resonant transmission lines 108, and the resonators 110 of the quantum circuit 100 may be provided on, over, or at least partially embedded in a substrate (not shown in FIG. 1). The substrate may be any substrate suitable for realizing quantum circuit assemblies described herein. In one implementation, the substrate may be a crystalline substrate such as, but not limited to a silicon or a sapphire substrate, and may be provided as a wafer or a portion thereof. In other implementations, the substrate may be non-crystalline. In general, any material that provides sufficient advantages (e.g. sufficiently good electrical isolation and/or ability to apply known fabrication and processing techniques) to outweigh the possible disadvantages (e.g. negative effects of spurious TLS's), and that may serve as a foundation upon which a quantum circuit may be built, falls within the spirit and scope of the present disclosure, e.g. high-resistance silicon. Additional examples of substrates include silicon-on-insulator (SOI) substrates, lll-V substrates, and quartz substrates.

[0052] In various embodiments, quantum circuits such as the one shown in FIG. 1 may be used to implement components associated with a quantum integrated circuit (1C). Such components may include those that are mounted on or embedded in a quantum 1C, or those connected to a quantum 1C. The quantum 1C may be either analog or digital and may be used in a number of applications within or associated with quantum systems, such as e.g. quantum processors, quantum amplifiers, quantum sensors, etc., depending on the components associated with the 1C. The 1C may be employed as part of a chipset for executing one or more related functions in a quantum system. Josephson Junctions fabricated using double-angle shadow evaporation

[0053] In order to highlight the advantages offered by novel quantum circuit assemblies fabricated using the trench method proposed herein, it would be helpful to first explain how Josephson Junctions are fabricated using the double-angle shadow evaporation method in conventional quantum circuits.

[0054] FIGS. 2A-2C provide a schematic illustration of one example of a photoresist mask 200 provided over a substrate 202 for fabricating Josephson Junctions using a double-angle shadow evaporation approach. Each of FIGS. 2A-2C provides a view of the same photoresist mask 200 over the substrate 202, but perspectives of these views are different. FIG. 2A provides a top down view (i.e. a view from a point above the substrate 202). FIG. 2B provides a cross-sectional view with a cross-section of the structure of FIG. 2A taken along a horizontal dashed line shown in FIG. 2A.

Finally, FIG. 2C provides a cross-sectional view with a cross-section of the structure of FIG. 2A taken along a vertical dashed line shown in FIG. 2A. A legend provided within a dashed box at the bottom of FIGS. 2A-2C illustrates patterns used to indicate different elements shown in FIGS. 2A-2C, so that the FIGs are not cluttered by many reference numerals.

[0055] Josephson Junctions may be created by a double-angle shadow evaporation approach using a two-layer photoresist mask 200 that includes a bottom photoresist layer 204 and a top photoresist layer 206 as shown in FIGS. 2A-2C. The bottom layer 204 is undercut from the top layer 206 in that some portions of the top layer 206 hang, or are suspended, over the bottom layer 204. The bottom layer 204 is undercut in such a manner that the top layer 206 of photoresist forms a suspended bridge 208, known as a Dolan bridge, over a section of the substrate 202. Ways for fabricating such undercuts in photoresist are well known in the art of photolithographic processing and, therefore, are not described here in detail.

[0056] In order to form a Josephson Junction, metals are then deposited through the photoresist mask 200 with the suspended bridge. Conventionally, this is done as illustrated in FIGS. 3A-3C.

[0057] Each of FIGS. 3A-3C illustrates a result of different subsequent fabrication steps. FIG. 3C provides two views of the same structure. The view on the right side of FIG. 3C is a top down view (i.e. a view similar to that shown in FIG. 2A). The view on the left side of FIG. 3C is a cross-sectional view with a cross-section of the structure of FIG. 3C taken along a horizontal dashed line shown in FIG. 3C (i.e. a view similar to that shown in FIG. 2B). Each of FIGS. 3A and 3B only provide a cross- sectional view similar to that of the left side of FIG. 3C but at an earlier fabrication step. Similar to FIGS. 2A-2C, a legend provided within a dashed box at the bottom of FIGS. 3A-3C illustrates patterns used in the figures to indicate different elements shown in FIGS. 3A-3C. Moreover, similar reference numerals in FIGS. 2A-2C and FIGS. 3A-3C are used to illustrate analogous elements in the figures. For example, reference numerals 202 and 302, shown, respectively, in FIGS. 2 and 3 refer to a substrate, reference numerals 204 and 304 - to a bottom mask layer, and so on. When provided with reference to one of the FIGS. 2A-2C and FIGS. 3A-3C, discussions of these elements are applicable to other figures, unless stated otherwise. Thus, in the interests of brevity, discussions of similar elements are not repeated for each of the figures but, rather, the differences between the figures are described.

[0058] As previously described herein, a Josephson Junction may include a thin layer of dielectric sandwiched between two layers of superconductors, the dielectric layer acting as the barrier in a superconducting tunnel junction. According to the double-angle shadow evaporation approach, such a device is conventionally fabricated by, first, depositing a layer of a first superconductor 310 on the substrate 302, as shown in FIG. 3A, through the two-layer mask such as e.g. the one shown in FIGS. 2A-2C. The first superconductor is deposited at an angle with respect to the substrate 302, as shown in FIG. 3A with an angle Q1. Slanted dotted-dashed lines in FIG. 3A illustrate the direction of deposition of the first superconductor 310. A layer of the first superconductor 310 may have a thickness between e.g. about 10 and 200 nanometers (nm), e.g. between about 30 and 100 nm.

[0059] The first superconductor 310 forms a bottom (base) electrode of the future Josephson Junction. A layer of insulator 311 (also referred to herein as a "dielectric layer 311" or a "dielectric 311"), shown in FIGS. 3B and 3C, is then provided over the first superconductor 310 to form a tunnel barrier of the future Josephson Junction. The tunnel barrier is formed by oxidizing the first superconductor 310, thus creating a layer of first superconductor oxide on its surface. Such an oxide may have a thickness between e.g. about 1 and 5 nm, typically for qubit applications between about 1 and 2 nm.

[0060] The fact that the choice of a tunnel barrier in a double-angle shadow evaporation method is constrained to an oxide of the base electrode superconductor limits the choice of the

superconductor used as the first superconductor 310 in that the superconductor must be such that a controlled layer of oxide may be created on it. In practice, aluminum oxide is the only controlled oxide that may be formed from a metal. Therefore, currently aluminum is the only superconducting metal that is used for the base electrode of Josephson Junctions fabricated using the double-angle shadow evaporation technique.

[0061] After the layer of dielectric 311 is provided on the first superconductor 310, a second superconductor 312 is deposited through the mask but at a different angle with respect to the substrate 302 than Q1. FIG. 3B illustrates the second angle as an angle Q2 and slanted dotted- dashed lines in FIG. 3B illustrate the direction of deposition of the second superconductor 312. In some embodiments, the first and the second superconductors 310, 312 are deposited at the opposite angles, if measured with respect to a normal to the substrate 302. Conventionally, the second superconductor 320 is aluminum because the first superconductor must be aluminum, as described above. A layer of the second superconductor 312 may have a thickness between e.g. about 10 and 200 nm, typically between about 30 and 100 nm. The second superconductor 312 forms a counter electrode (i.e. counter to the bottom electrode formed by the first superconductor 310) of the future Josephson Junction, typically referred to as a "top" electrode.

[0062] The first and second superconductors 310, 312 are usually deposited using a non-conformal process, such as e.g. evaporative deposition. After deposition of the second superconductor 312, the deposition mask is removed, removing with it any first and/or second superconductor 310, 312 deposited on top of it.

[0063] In general, the above-described process of creating patterned structures of one or more target materials (in this case, structures made of the first and second superconductors 310, 312) on the surface of a substrate using a sacrificial material such as photoresist is referred to as a lift-off method. Lift-off is a type of an additive technique, as opposed to subtracting techniques like etching, and may be applied in cases where a direct etching of structural material would have undesirable effects on one or more layers below.

[0064] After the deposition mask is removed, the resulting Josephson Junction is left on the substrate 302 as shown in FIG. 3C as a Josephson Junction 314. The Josephson Junction 314 is formed by the small region of overlap under the photoresist bridge 308 (i.e. the area under the bridge 308 where the first superconductor 310, covered with a layer of a thin insulating material is overlapped by the second superconductor 312). Dimensions of the Josephson Junction 314 along x- axis and y-axis, shown in FIG. 3C as d x and d v , respectively, are typically between about 50 and 1000 nm for any of d x and d v .

[0065] As a result of performing the double-angle shadow evaporation as described above, junctions of the first and second superconductors may also form on each side of the Josephson Junction 314, such junctions shown in FIGS. 3B and 3C as junctions 316. Flowever, because these junctions are of much larger dimensions than the Josephson Junction 314, e.g. measured several thousands of nm in the x-direction and hundreds of nm or more in the y-direction, they are essentially infinite for the Josephson effect to take place and, therefore, act as superconductors rather than Josephson Junctions.

[0066] One problem with the fabrication approach described above is that it includes steps which are not suitable for manufacturing on the larger wafer sizes used in the semiconductor industry. For example, angled metal deposition step does not produce a uniform film across the wafer and would prohibit uniform qubit performance across large area. Moreover, the fabrication approach described above relies on lift-off of metal films to produce wires remaining on the wafer. The lift-off technique is not amenable to the chemical waste systems of wafer cleaning tools and would not facilitate high volume manufacturing or even an extension to many qubits on a single wafer.

[0067] Another problem is that it limits materials which may be employed in forming Josephson Junctions. As described above, Josephson Junctions fabricated the double-angle shadow

evaporation approach can only use Al as the superconductor for the base electrode. This may be problematic because interconnects in quantum circuits are typically made from other

superconducting materials such as e.g. Nb, TiN and NbTiN and interfaces between the different superconducting materials used for Josephson Junctions and interconnects connected thereto present yet another source of losses. Any losses are especially significant in context of quantum circuits where, sometimes, energy as small as that of a single photon is to be transmitted, making loss tolerance very low.

[0068] A trench method disclosed herein may improve on at least some of these problems.

Josephson Junctions fabricated based on an ooenina/trench

[0069] FIG. 4 provides a flow chart of a trench method 400 for fabricating Josephson Junctions for quantum circuit assemblies, according to some embodiments of the present disclosure.

[0070] Although the operations of the method 400 are illustrated in FIG. 4 once each and in a particular order, the operations may be performed in any suitable order and repeated as desired.

For example, one or more operations may be performed in parallel to manufacture multiple quantum circuit assemblies as described herein substantially simultaneously. In another example, the operations may be performed in a different order to reflect the architecture of a particular quantum circuit component in which one or more quantum circuit assemblies with Josephson Junctions fabricated according to the trench method are to be included.

[0071] In addition, the exemplary manufacturing method 400 may include other operations not specifically shown in FIG. 4, such as e.g. various cleaning or planarization operations as known in the art. For example, in some embodiments, the substrate may be cleaned prior to or/and after any of the processes of the method 400 described herein, e.g. to remove surface-bound organic and metallic contaminants, as well as subsurface contamination. In some embodiments, cleaning may be carried out using e.g. a chemical solutions (such as peroxide), and/or with ultraviolet (UV) radiation combined with ozone, and/or oxidizing the surface (e.g., using thermal oxidation) then removing the oxide (e.g. using hydrofluoric acid (HF)). In another examples, the structures/assemblies described herein may be planarized prior to or/and after any of the processes of the method 400 described herein, e.g. to remove overburden or excess materials. In some embodiments, planarization may be carried out using either wet or dry planarization processes, e.g. planarization be a chemical mechanical planarization (CMP), which may be understood as a process that utilizes a polishing surface, an abrasive and a slurry to remove the overburden and planarize the surface.

[0072] Various operations of the method 400 may be illustrated with reference to exemplary embodiments shown in FIGS. 5A-5H, but the method 400 may be used to manufacture any suitable quantum circuit assemblies with Josephson Junctions according to any embodiments of the present disclosure. FIGS. 5A-5FI are cross-sections illustrating various example stages in the manufacture of a quantum circuit assembly using the trench method of FIG. 4 in accordance with some

embodiments of the present disclosure. Each one of FIGS. 5A-5FI illustrates a cross-sectional view (top illustration in each of FIGS. 5A-5FI) along the z-y plane of the coordinate system indicated in these FIGS., and a top down view (bottom illustration in each of FIGS. 5A-5FI) of the x-y plane. Thus, the top down view shown in FIGS. 5A-5FI is the view looking down from a plane indicted in FIGS. 5A- 5H as a plane AA, and the cross-sectional view is a cross-section along a plane indicted in FIGS. 5A-5FI as a plane BB (i.e. the top illustration of each of FIGS. 5A-5FI is a cross-section along the plane BB and the bottom illustration - a top view looking down from the plane AA). In FIGS. 5A-5FI, same reference numerals refer to the same or analogous elements/materials shown.

[0073] The method 400 may begin with providing, over a substrate, which could be any of the substrates described above, a layer of an electrically conductive material shaped to form a first electrode for the future Josephson Junction (process 402 shown in FIG. 4, a result of which is illustrated with an assembly 502 shown in FIG. 5A). The assembly 502 illustrates a substrate 522, which could be any of the substrates described above, with a first electrode 524 provided over the substrate.

[0074] In various embodiments, the electrically conductive material forming the first electrode provided in the process 402 may include any conducting or superconducting material suitable for providing electrical connectivity in a quantum circuit, such as e.g. Al, Nb, NbN, NbTiN, TiN, MoRe, etc., or any alloy of two or more superconducting/conducting materials. A thickness of the first electrode (i.e. a dimension measured along the z-axis of the coordinate system as shown in FIGS. 5A- 5H) provided in the process 402 may be between about 2 and 40 nm, including all values and ranges therein, e.g. between about 4 and 30 nm, or between about 6 and 20 nm, while the width of the first electrode (i.e. a dimension measured along the x-axis of the coordinate system as shown in FIGS. 5A- 5H), which electrode may be formed into a strip as shown in FIG. 5A, may be between about 5 and 40 nm, including all values and ranges therein, e.g. between about 7 and 30 nm, or between about 10 and 20 nm.

[0075] In various embodiments, any suitable deposition and patterning techniques may be used for providing the first electrode 524 in the process 402. Examples of deposition techniques for depositing a layer of an electrically conductive material for forming the first electrode 524 include atomic layer deposition (ALD), physical vapor deposition (PVD) (e.g. evaporative deposition, magnetron sputtering, or e-beam deposition), chemical vapor deposition (CVD), or electroplating. Examples of patterning techniques include photolithographic or electron-beam (e-beam) patterning, possibly in conjunction with a dry etch, such as e.g. radio frequency (RF) reactive ion etch (RIE) or inductively coupled plasma (ICP) RIE, to pattern the layer of an electrically conductive material into the first electrode 524 of the specified geometries for a given implementation.

[0076] The method may then proceed with providing a layer referred to herein as a "support layer" over the first electrode 524 (process 404 shown in FIG. 4, a result of which is illustrated with an assembly 504 shown in FIG. 5B). The assembly 504 illustrates a support layer 526 provided over the first electrode 524 provided over the substrate 522. The two horizontal dotted lines shown in the bottom view of FIG. 5B illustrate the perimeter of the first electrode 524 underneath the support layer 526.

[0077] The layer 526 is referred to as a "support layer" because, in a later process 406, it will serve to support formation of an opening/trench therein, which opening/trench will be used to form the tunnel barrier and the second electrode of the future Josephson Junction. Therefore, in various embodiments, the material of the support layer 526 may include any suitable material in which such an opening may be formed. For example, in some embodiments the support layer 526 may be, or include, a dielectric material such as e.g. one or more of a silicon oxide (i.e. a compound comprising silicon and oxygen, e.g. Si02), a hafnium oxide (i.e. a compound comprising hafnium and oxygen, e.g. Flf02), a silicon nitride (i.e. a compound comprising silicon and nitrogen, e.g. SiN), a silicon oxynitride (i.e. a compound comprising silicon, oxygen, and nitrogen, e.g. SiON), an aluminum oxide (i.e. a compound comprising aluminum and oxygen, e.g. AI203), an aluminum hafnium oxide (i.e. a compound comprising aluminum, hafnium, and oxygen, e.g. AIHfO), a carbon-doped oxide (i.e. a compound comprising carbon and oxygen), organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. Examples of techniques which may be used to provide the support layer 526 over the first electrode 524 include ALD, CVD, PVD, spin-coating, and dip-coating.

[0078] In various embodiments, a thickness of the support layer (i.e. a dimension measured along the z-axis of the coordinate system as shown in FIGS. 5A-5FI) provided in the process 404 may be between about 10 and 300 nm, including all values and ranges therein, e.g. between about 20 and 100 nm, or between about 40 and 80 nm.

[0079] The method 400 may then continue with providing an opening in a stack that includes an upper layer of the substrate, the first electrode material, and the support layer (process 406 shown in FIG. 4, a result of which is illustrated with an assembly 506 shown in FIG. 5C), i.e. forming an opening in the support layer, which opening extends through and past (i.e. extending further/deeper than) than the conductive material of the first electrode. The assembly 506 illustrates a stack 527 which includes an upper layer of the substrate 522, the conductive material 524 of the first electrode, and the support layer 526, and further illustrates an opening 529 formed in the stack 527. The assembly 506, as well as the assemblies illustrated in subsequent FIGS., illustrate the opening 529 as having a so-called "non-re-entrant" profile, where the width at the top of the opening is larger than the width at the bottom of the opening because this is typical for real-world

implementations. Flowever, in other embodiments, the opening 529 may have straight walls perpendicular to the substrate, or may have a so-called "re-entrant" profile, where the width at the top of the opening is smaller than the width at the bottom of the opening. While the opening 529 is shown in the top view of FIG. 5C as a rectangular opening, other shapes may be used in other embodiments, e.g. the opening 529 may be substantially circular, oval, polygonal, or irregularly shaped.

[0080] Various dimensions of the opening 529 will now be discussed, where various embodiments of the present disclosure may implement an opening of the process 406 according to one or more of these dimensions. Thus, in some embodiments, a depth of the opening 529 (i.e. a dimension measured along the z-axis of the coordinate system shown in FIGS. 5A-5FI and indicated in FIG. 5C as "dl") may be between about 40 and 400 nm, including all values and ranges therein, e.g. between about 60 and 200 nm, or between about 80 and 100 nm. In some embodiments, a width of the opening 529 in the plane of the first electrode 524 (i.e. a dimension measured along the y-axis of the coordinate system shown in FIGS. 5A-5FI and indicated in FIG. 5C as "d2") may be between about 20 and 300 nm, including all values and ranges therein, e.g. between about 40 and 200 nm, or between about 50 and 150 nm. In some embodiments the opening 529 may be a trench, and a length of the trench (i.e. a dimension measured along the x-axis of the coordinate system shown in FIGS. 5A-5FI and indicated in FIG. 5C as "d3") may be between about 20 and 300 nm, including all values and ranges therein, e.g. between about 40 and 200 nm, or between about 50 and 100 nm. In some embodiments, the area of the opening 529 in the plane of the first electrode 524 (i.e. a dimension measured in the x-y plane of the coordinate system as shown in FIGS. 5A-5FI, in the plane of the first electrode 524) may be between about 400 and 90,000 nm 2 , including all values and ranges therein, e.g. between about 1,600 and 40,000 nm 2 , or between about 2,500 and 15,000 nm 2 . In some embodiments, the opening 529 may extend past the first electrode 524 (i.e. a dimension measured along the z-axis of the coordinate system shown in FIGS. 5A-5FI and indicated in FIG. 5C as "d4") by a depth of at least about 10 percent (%) of the thickness of the support layer 526, including all values and ranges therein, e.g. at least about 30%, or at least about 50% of the thickness of the support layer 526.

[0081] In various embodiments, any suitable techniques may be used for providing the opening 529 in the process 406, such as those known in conventional semiconductor processing.

[0082] Turning back to FIG. 4, the method 400 next includes depositing a tunnel barrier material on sidewalls and bottom of the opening provided in the process 406 (process 408 shown in FIG. 4, a result of which is illustrated with an assembly 508 shown in FIG. 5D). The assembly 508 illustrates that the opening 529 of the assembly 506 is now lined with a liner of a tunnel barrier material 528, thus resulting in a smaller opening 531. One or more portions of the tunnel barrier material 528 adjacent to the first electrode material 524, indicated in FIG. 5D as portions 533, can later form tunnel barriers of the respective Josephson Junctions.

[0083] Selection of the thickness and the type of the material deposited in the process 408 should be based on the consideration that the one or more portions 533 of the tunnel barrier liner 528 will later serve as a tunnel barrier of the future Josephson Junction. In various embodiments, a thickness of the tunnel barrier material 528 in the plane of the first electrode 524 (i.e. a dimension measured along the y-axis of the coordinate system as shown in FIGS. 5A-5FI and indicated in FIG. 5D as a distance "d5") may be between about 1 and 8 nm, including all values and ranges therein, e.g.

between about 1 and 4 nm, or between about 1 and 2 nm. In some embodiments, the tunnel barrier material 528 could be selected as any dielectric material of sufficiently high quality (i.e. low losses in terms of spurious TLS's), such as e.g. silicon oxide, hafnium oxide, or aluminum oxide, while, in other embodiments, the tunnel barrier material 528 could be selected as a suitable

semiconductor material.

[0084] In various embodiments, a liner of the tunnel barrier material 528 may be deposited on sidewalls and bottom of the opening 529 in the process 408 using any suitable techniques for conformally depositing materials onto selected surfaces, such as e.g. ALD, CVD, plasma enhanced CVD (PECVD), or/and PVD processes. As a result of depositing the tunnel barrier material 528 as a liner within the opening 529, the volume of the opening 529 is reduced but there still remains a smaller opening, as indicated in FIG. 5D with the smaller opening 531.

[0085] In some embodiments, the inner surfaces of the opening 529 may be cleaned or treated prior to depositing the tunnel barrier material liner 528 to reduce surface contamination and minimize interface traps and/or promote adhesion, for example using chemical or plasma clean, or applying heat in a controlled environment. In some embodiments, an "interface layer" may be provided between a portions of the inner sidewalls of the opening 529 (e.g. the portion(s) where the first electrode material 524 is exposed) and the tunnel barrier material 528 deposited thereon to prevent, decrease, or minimize spontaneous and uncontrolled formation of other interfacial layers and thus improve performance of the final Josephson Junction. In some embodiments, an adhesion promoter or adhesion layer may be applied prior to deposition of the tunnel barrier material 528.

[0086] Although not specifically illustrated in FIG. 5D, in some implementations, as a result of performing the process 408, the tunnel barrier material 528 may be deposited not only within the opening 529, but also over the upper surfaces 535 of the support layer 526. Such a layer over the upper surfaces 535 may subsequently be removed, e.g. using a suitable planarization technique.

[0087] The method 400 may then proceed with filling at least a portion of the lined opening formed as a result of the process 408 with an electrically conductive, preferably superconductive, material to form a second electrode of the future Josephson Junction (process 410 shown in FIG. 4, a result of which is illustrated with an assembly 510 shown in FIG. 5E). The assembly 510 illustrates an electrically conductive material 530 filling up the opening 531. A portion of the conductive material 530 deposited over the tunnel barrier material 528 on the sidewall(s) opposite to the first electrode material 524 can form the top electrode 537, indicated in FIG. 5E, of the Josephson Junction.

[0088] Although not specifically illustrated in FIG. 5E, in some implementations, as a result of performing the process 410, the conductive material 530 may be deposited not only within the opening 531, but also over the upper surfaces 539. Such a layer over the upper surfaces 539 may subsequently be removed, e.g. using a suitable planarization technique.

[0089] In various embodiments, the electrically conductive material 530 forming the second electrode 537 provided in the process 410 may include any conducting or superconducting material suitable for providing electrical connectivity in a quantum circuit, such as e.g. any of such materials described above, and may be the same or different from the electrically conductive materials of the first electrode 524. Any suitable deposition techniques, possibly in combination with patterning, may be used for providing the electrically conductive material 530 forming the second electrode 537 in the process 410, such as e.g. those described above.

[0090] After the process 410, a Josephson Junction 541 is formed by the small region where the conductive material of the first electrode 524 is opposite the conductive material of the second electrode 530, with the two conductive materials separated by the portion 533 of the tunnel barrier material 528. As a result of the symmetric deposition within an opening, two such Josephson Junctions may be formed, as indicated in FIG. 5E with two Josephson Junctions 541 and two regions where the conductive material of the first electrode 524 is opposite the conductive material of the second electrode 530, with the two conductive materials separated by the portion 533 of the tunnel barrier material 528 (the regions outlined in FIG. 5E with dashed boxes shown in the bottom, i.e. the top down view, illustration of FIG. 5E). While FIG. 5E illustrates that the two Josephson Junctions 541 share their second electrode 537 (i.e. their second electrodes 537 are formed from a single continuous region of the conductive material 530), in other embodiments, the second electrodes of the two Josephson Junctions 541 may be electrically separated from one another, e.g. by providing an insulating structure 543 as shown with a dotted outline illustrated only (in order to not clutter the drawings) in the top down view shown in FIG. 5E. Whether or not their second electrodes are shared, in some embodiments, the two Josephson Junctions 541 as shown in FIG. 5E may advantageously be fabricated substantially at the same time.

[0091] Characteristic and indicative of the use of the trench method described above is the fact that the plane of the tunnel barrier layer 528 of the Josephson Junction 541 (said plane indicated in the cross-sectional side view of FIG. 5E as a plane 545) may be substantially perpendicular or at a small angle with respect to the plane perpendicular to the substrate (said plane indicated in the cross- sectional side view of FIG. 5E as a plane 547). For example, in various embodiments, the plane 545 of the tunnel barrier layer may be at an angle less than about 50 degrees, including all values and ranges therein, e.g. less than about 30 degrees, or less than about 20 degrees, from the plane 547 perpendicular to the substrate 522. While these planes are indicated in FIG. 5E only for the

Josephson Junction 541 on one side of the top illustration, this is applicable to the other Josephson Junction 541 shown in FIG. 5E. In fact, the planes of the tunnel barrier layer of the first and second Josephson Junctions 541 shown in FIG. 5E could be substantially symmetric with respect to a plane that is perpendicular to the substrate and is in the middle between the two Josephson Junctions 541.

[0092] In various embodiments, the method 400 may further include a number of other, optional, processes which are shown in FIG. 4 as processes 412, 414, and 416, in that sequence, but may be carried out in any suitable order with respect to one another and with respect to other processes shown in FIG. 4.

[0093] In the process 412, a result of which is illustrated with an assembly 512 shown in FIG. 5F, a contact 532 to the first electrode 524 may be provided. Such a contact may be provided by forming an opening in the support layer, the opening extending to the layer of the conductive material 524, and then filling the opening with a suitable electrically conductive material, e.g. using processes described above. In various embodiments, the conductive material 532 may be the same or different than other electrically conductive materials described herein.

[0094] In the process 414, a result of which is illustrated with an assembly 514 shown in FIG. 5G, some or all of the support layer 526 may be removed, and in the process 416, a result of which is illustrated with an assembly 516 shown in FIG. 5H, portions 549 of the upper layer of the substrate 522 in the vicinity (e.g. adjacent to) of the Josephson Junctions 541 may be removed. While FIG. 5H illustrates result of the process 416 in combination with the process 414, in other embodiments, the process 416 may be performed even though the process 414 is not. Such embodiments of removing portions of dielectric materials in the vicinity of the Josephson Junction(s) 541 have the potential of advantageously reducing the amount of spurious TLS's surrounding the Josephson Junction(s) 541, which improve coherence time of qubits with such Josephson Junction(s).

[0095] In various embodiments, removal of the support layer 526 may be carried out by e.g. etching the support layer 526 using an appropriate etchant, provided that the material of the support layer 526 has sufficient etch selectivity with respect to the materials of the surrounding elements shown in FIGS. 5G and 5H. As known in the art, two materials are said to have "sufficient etch selectivity" when etchants used to etch one material do not substantially etch the other, enabling selective etching of one material but not the other. Removal of the portions 549 of the upper layer of the substrate 522 may be carried out using sacrificial, etch-selective material there before the first electrode material 524 was deposited, and later on etching such a sacrificial material away.

[0096] In various embodiments, Josephson Junctions as described herein, e.g. one or more of the Josephson Junctions 541 as shown in the quantum circuit assemblies 510, 512, 514, or 516, could be included in a superconducting qubit, e.g. included in a charge qubit, in particular included in a transmon, or included in a flux qubit. In some embodiments, a pair of Josephson Junctions 541 could be a part of a SQUID.

[0097] Various embodiments of the proposed trench method can be efficiently used in large-scale manufacturing, providing a substantial improvement with respect to conventional approaches, such as e.g. the double-angle shadow evaporation method, which, as described above, includes fabrications steps that are not suitable for implementing with larger wafer sizes used by device manufacturers. In addition, the trench method described herein advantageously enables atomic control of the tunnel junction barrier (i.e. the layer 528) due to formation of such a layer using a conformal deposition process. Yet another advantage of the proposed method is the ability to define and carefully control the area of the Josephson Junction by the width of the strip of the first electrode 524. Still another advantage is the ability to use a larger selection of

conductive/superconductive materials to form the first and second electrodes of Josephson Junctions, which may reduce losses due to interfaces with materials used to form interconnects in quantum circuits, resulting in Josephson Junctions having improved performance compared to those fabricated using existing techniques. Exemplary qubit devices

[0098] Quantum circuit assemblies/structures with Josephson Junctions as described above may be included in any kind of qubit devices or quantum processing devices/structures. Some examples of such devices/structures are illustrated in FIGS. 6A-6B, 7, and 8.

[0099] FIGS. 6A-6B are top views of a wafer 1100 and dies 1102 that may be formed from the wafer 1100, according to some embodiments of the present disclosure. The dies 1102 may include any of the quantum circuits disclosed herein, e.g., the quantum circuit 100, may include any of the quantum circuit assemblies described herein, such as e.g. the quantum circuit assembly 510, 512, 514, or 516, or any further embodiments of such an assembly as described herein, and may include one or more Josephson Junctions fabricated using the trench method described herein. The wafer 1100 may include semiconductor material and may include one or more dies 1102 having conventional and quantum circuit device elements formed on a surface of the wafer 1100. Each of the dies 1102 may be a repeating unit of a semiconductor product that includes any suitable conventional and/or quantum circuit qubit device. After the fabrication of the semiconductor product is complete, the wafer 1100 may undergo a singulation process in which each of the dies 1102 is separated from one another to provide discrete "chips" of the semiconductor product. A die 1102 may include one or more quantum circuits 100, including any Josephson Junctions fabricated using the trench method described herein, as well as any other 1C components. In some

embodiments, the wafer 1100 or the die 1102 may include a memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 1102. For example, a memory array formed by multiple memory devices may be formed on a same die 1102 as a processing device (e.g., the processing device 2002 of FIG. 8) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

[0100] FIG. 7 is a cross-sectional side view of a device assembly 1200 that may include any of the embodiments of the quantum circuit assemblies disclosed herein. The device assembly 1200 includes a number of components disposed on a circuit board 1202. The device assembly 1200 may include components disposed on a first face 1240 of the circuit board 1202 and an opposing second face 1242 of the circuit board 1202; generally, components may be disposed on one or both faces 1240 and 1242.

[0101] In some embodiments, the circuit board 1202 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1202. Signal transfer between components or layer may happen with both low resistance DC connections or by either in-plane or out-of-plane capacitive connections. In other embodiments, the circuit board 1202 may be a package substrate or flexible board.

[0102] The 1C device assembly 1200 illustrated in FIG. 7 may include a package-on-interposer structure 1236 coupled to the first face 1240 of the circuit board 1202 by coupling components 1216. The coupling components 1216 may electrically and mechanically couple the package-on- interposer structure 1236 to the circuit board 1202, and may include solder balls (as shown in FIG.

7), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure. The coupling components 1216 may include other forms of electrical connections that may have no mechanical contact, such as parallel plate capacitors or inductors, which can allow high-frequency connection between components without mechanical or DC connections.

[0103] The package-on-interposer structure 1236 may include a package 1220 coupled to an interposer 1204 by coupling components 1218. The coupling components 1218 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 1216. Although a single package 1220 is shown in FIG. 7, multiple packages may be coupled to the interposer 1204; indeed, additional interposers may be coupled to the interposer 1204. The interposer 1204 may provide an intervening substrate used to bridge the circuit board 1202 and the package 1220. The package 1220 may be a quantum circuit device package as described herein, e.g. a package including any of the quantum circuits disclosed herein, e.g., the quantum circuit 100, may include any of the quantum circuit assemblies described herein, such as e.g. the quantum circuit assembly 510, 512, 514, or 516, or any further embodiments of such an assembly as described herein, and may include one or more Josephson Junctions fabricated using the trench method described herein, or may be a conventional 1C package, for example. Generally, the interposer 1204 may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer 1204 may couple the package 1220 (e.g., a die) to a ball grid array (BGA) of the coupling components 1216 for coupling to the circuit board 1202. In the embodiment illustrated in FIG. 7, the package 1220 and the circuit board 1202 are attached to opposing sides of the interposer 1204; in other embodiments, the package 1220 and the circuit board 1202 may be attached to a same side of the interposer 1204. In some embodiments, three or more components may be interconnected by way of the interposer 1204.

[0104] The interposer 1204 may be formed of a crystalline material, such as silicon, germanium, or other semiconductors, an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer 1204 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group lll-V and group IV materials. The interposer 1204 may include metal interconnects 1210 and vias 1208, including but not limited to through-silicon vias (TSVs) 1206. The interposer 1204 may further include embedded devices 1214, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as RF devices, power amplifiers, power management devices, antennas, arrays, sensors, and

microelectromechanical systems (M EMS) devices may also be formed on the interposer 1204. The package-on-interposer structure 1236 may take the form of any of the package-on-interposer structures known in the art.

[0105] The device assembly 1200 may include a package 1224 coupled to the first face 1240 of the circuit board 1202 by coupling components 1222. The coupling components 1222 may take the form of any of the embodiments discussed above with reference to the coupling components 1216, and the package 1224 may take the form of any of the embodiments discussed above with reference to the package 1220. The package 1224 may be a package including one or more quantum circuits with Josephson Junctions fabricated using the trench method as described herein, or may be a conventional 1C package, for example. In some embodiments, the package 1224 may take the form of any of the embodiments of the quantum circuit 100 with any of the quantum circuit assemblies described herein.

[0106] The device assembly 1200 illustrated in FIG. 7 includes a package-on-package structure 1234 coupled to the second face 1242 of the circuit board 1202 by coupling components 1228. The package-on-package structure 1234 may include a package 1226 and a package 1232 coupled together by coupling components 1230 such that the package 1226 is disposed between the circuit board 1202 and the package 1232. The coupling components 1228 and 1230 may take the form of any of the embodiments of the coupling components 1216 discussed above, and the packages 1226 and 1232 may take the form of any of the embodiments of the package 1220 discussed above. Each of the packages 1226 and 1232 may be a qubit device package as described herein or may be a conventional 1C package, for example. In some embodiments, one or both of the packages 1226 and 1232 may take the form of any of the embodiments of the quantum circuit 100 with any of the quantum circuit assemblies described herein, or a combination thereof.

[0107] FIG. 8 is a block diagram of an exemplary quantum computing device 2000 that may include any of the quantum circuits with any of the quantum circuit assemblies disclosed herein. A number of components are illustrated in FIG. 8 as included in the quantum computing device 2000, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the quantum computing device 2000 may be attached to one or more PCBs (e.g., a motherboard), and may be included in, or include, any of the quantum circuits with any of the quantum circuit assemblies described herein. In some embodiments, various ones of these components may be fabricated onto a single system-on-a-chip (SoC) die. Additionally, in various embodiments, the quantum computing device 2000 may not include one or more of the components illustrated in FIG. 8, but the quantum computing device 2000 may include interface circuitry for coupling to the one or more components. For example, the quantum computing device 2000 may not include a display device 2006, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 2006 may be coupled. In another set of examples, the quantum computing device 2000 may not include an audio input device 2018 or an audio output device 2008, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 2018 or audio output device 2008 may be coupled. In further examples, the quantum computing device 2000 may include a microwave input device or a microwave output device (not specifically shown in FIG. 7), or may include microwave input or output device interface circuitry (e.g., connectors and supporting circuitry) to which a microwave input device or microwave output device may be coupled.

[0108] The quantum computing device 2000 may include a processing device 2002 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 2002 may include a quantum processing device 2026 (e.g., one or more quantum processing devices), and a non-quantum processing device 2028 (e.g., one or more non-quantum processing devices). The quantum processing device 2026 may include any of the quantum circuits disclosed herein, e.g., the quantum circuit 100, may include any of the quantum circuit assemblies described herein, such as e.g. the quantum circuit assembly 510, 512, 514, or 516, or any further embodiments of such an assembly as described herein, and may include one or more Josephson Junctions fabricated using the trench method described herein, and may perform data processing by performing operations on the qubits that may be generated in the quantum circuits 100, and monitoring the result of those operations. For example, as discussed above, different qubits may be allowed to interact, the quantum states of different qubits may be set or transformed, and the quantum states of different qubits may be read. The quantum processing device 2026 may be a universal quantum processor, or specialized quantum processor configured to run one or more particular quantum algorithms. In some embodiments, the quantum processing device 2026 may execute algorithms that are particularly suitable for quantum computers, such as cryptographic algorithms that utilize prime factorization, encryption/decryption, algorithms to optimize chemical reactions, algorithms to model protein folding, etc. The quantum processing device 2026 may also include support circuitry to support the processing capability of the quantum processing device 2026, such as input/output channels, multiplexers, signal mixers, quantum amplifiers, and analog-to- digital converters.

[0109] As noted above, the processing device 2002 may include a non-quantum processing device 2028. In some embodiments, the non-quantum processing device 2028 may provide peripheral logic to support the operation of the quantum processing device 2026. For example, the non-quantum processing device 2028 may control the performance of a read operation, control the performance of a write operation, control the clearing of quantum bits, etc. The non-quantum processing device 2028 may also perform conventional computing functions to supplement the computing functions provided by the quantum processing device 2026. For example, the non-quantum processing device 2028 may interface with one or more of the other components of the quantum computing device 2000 (e.g., the communication chip 2012 discussed below, the display device 2006 discussed below, etc.) in a conventional manner, and may serve as an interface between the quantum processing device 2026 and conventional components. The non-quantum processing device 2028 may include one or more digital signal processors (DSPs), application-specific ICs (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices.

[0110] The quantum computing device 2000 may include a memory 2004, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and/or a hard drive. In some embodiments, the states of qubits in the quantum processing device 2026 may be read and stored in the memory 2004. In some embodiments, the memory 2004 may include memory that shares a die with the non-quantum processing device 2028. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0111] The quantum computing device 2000 may include a cooling apparatus 2024. The cooling apparatus 2024 may maintain the quantum processing device 2026, in particular the quantum circuits 100 as described herein, at a predetermined low temperature during operation to avoid qubit decoherence and to reduce the effects of scattering in the quantum processing device 2026. This predetermined low temperature may vary depending on the setting; in some embodiments, the temperature may be 5 degrees Kelvin or less. In some embodiments, the non-quantum processing device 2028 (and various other components of the quantum computing device 2000) may not be cooled by the cooling apparatus 2030, and may instead operate at room temperature. The cooling apparatus 2024 may be, for example, a dilution refrigerator, a helium-3 refrigerator, or a liquid helium refrigerator.

[0112] In some embodiments, the quantum computing device 2000 may include a communication chip 2012 (e.g., one or more communication chips). For example, the communication chip 2012 may be configured for managing wireless communications for the transfer of data to and from the quantum computing device 2000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.

[0113] The communication chip 2012 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UM B) project (also referred to as "3GPP2"), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for

Microwave Access, which is a certification mark for products that pass conformity and

interoperability tests for the IEEE 802.16 standards. The communication chip 2012 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2012 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2012 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 2012 may operate in accordance with other wireless protocols in other embodiments. The quantum computing device 2000 may include an antenna 2022 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).

[0114] In some embodiments, the communication chip 2012 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 2012 may include multiple communication chips. For instance, a first communication chip 2012 may be dedicated to shorter-range wireless

communications such as Wi-Fi or Bluetooth, and a second communication chip 2012 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 2012 may be dedicated to wireless communications, and a second communication chip 2012 may be dedicated to wired communications.

[0115] The quantum computing device 2000 may include battery/power circuitry 2014. The battery/power circuitry 2014 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the quantum computing device 2000 to an energy source separate from the quantum computing device 2000 (e.g., AC line power).

[0116] The quantum computing device 2000 may include a display device 2006 (or corresponding interface circuitry, as discussed above). The display device 2006 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.

[0117] The quantum computing device 2000 may include an audio output device 2008 (or corresponding interface circuitry, as discussed above). The audio output device 2008 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.

[0118] The quantum computing device 2000 may include an audio input device 2018 (or corresponding interface circuitry, as discussed above). The audio input device 2018 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).

[0119] The quantum computing device 2000 may include a GPS device 2016 (or corresponding interface circuitry, as discussed above). The GPS device 2016 may be in communication with a satellite-based system and may receive a location of the quantum computing device 2000, as known in the art.

[0120] The quantum computing device 2000 may include an other output device 2010 (or corresponding interface circuitry, as discussed above). Examples of the other output device 2010 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device. [0121] The quantum computing device 2000 may include an other input device 2020 (or corresponding interface circuitry, as discussed above). Examples of the other input device 2020 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0122] The quantum computing device 2000, or a subset of its components, may have any appropriate form factor, such as a hand-held or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device.

Select Examples

[0123] The following paragraphs provide examples of various ones of the embodiments disclosed herein.

[0124] Example 1 provides a quantum circuit assembly that includes a Josephson Junction over a substrate, the Josephson Junction including a first electrode, a second electrode, and a tunnel barrier layer between the first electrode and the second electrode, where the plane of the tunnel barrier layer is at an angle less than about 50 degrees, including all values and ranges therein, e.g. less than about 30 degrees, or less than about 20 degrees, from a plane perpendicular to the substrate.

[0125] Example 2 provides the quantum circuit assembly according to Example 1, where the Josephson Junction is a first Josephson Junction and the quantum circuit assembly further includes a second Josephson Junction including a first electrode, a second electrode, and a tunnel barrier layer between the first electrode and the second electrode. In some implementations, such a pair of Josephson Junctions could advantageously be fabricated at the same time.

[0126] Example 3 provides the quantum circuit assembly according to Example 2, where the plane of the tunnel barrier layer of the second Josephson Junction and the plane of the tunnel barrier layer of the first Josephson Junction are substantially symmetric with respect to a plane that is perpendicular to the substrate and is in the middle between the plane of the tunnel barrier layer of the second Josephson Junction and the plane of the tunnel barrier layer of the first Josephson Junction.

[0127] Example 4 provides the quantum circuit assembly according to Examples 2 or 3, where the plane of the tunnel barrier layer of the second Josephson Junction is at an angle less than about 50 degrees, including all values and ranges therein, e.g. less than about 30 degrees, or less than about 20 degrees, from the plane perpendicular to the substrate.

[0128] Example 5 provides the quantum circuit assembly according to any one of Examples 2-4, where the first Josephson Junction and the second Josephson Junction form a SQUID.

[0129] Example 6 provides the quantum circuit assembly according to any one of Examples 2-5, where the second electrode of the first Josephson Junction is electrically isolated from the second electrode of the second Josephson Junction.

[0130] Example 7 provides the quantum circuit assembly according to any one of Examples 2-5, where the second electrode of the first Josephson Junction and the second electrode of the second Josephson Junction is a single shared electrode.

[0131] Example 8 provides the quantum circuit assembly according to Example 7, where the tunnel barrier layer of the first Josephson Junction is adjacent to a first sidewall of the single shared electrode.

[0132] Example 9 provides the quantum circuit assembly according to Examples 7 or 8, where the tunnel barrier layer of the second Josephson Junction is adjacent to a second sidewall of the single shared electrode.

[0133] Example 10 provides the quantum circuit assembly according to any one of the preceding Examples, where the first electrode is a portion of a layer of an electrically conductive, preferably superconductive, material, the layer being substantially parallel to the plane of the substrate.

[0134] Example 11 provides the quantum circuit assembly according to any one of the preceding Examples, where a thickness of the tunnel barrier layer is between about 1 and 8 nm, including all values and ranges therein, e.g. between about 1 and 4 nm, or between about 1 and 2 nm.

[0135] Example 12 provides a method of fabricating a quantum circuit assembly including a Josephson Junction that includes a first electrode, a second electrode, and a tunnel barrier layer between the first electrode and the second electrode. The method includes providing a first layer over a substrate, the first layer including a first electrically conductive, preferably superconductive, material; providing a support layer over the first layer; forming an opening in the support layer, the opening extending through and past (i.e. extending further/deeper than) the first layer; depositing a liner of a tunnel barrier material within the opening; and providing a second electrically conductive, preferably superconductive, material within at least a portion of the opening having the liner, where the first electrically conductive material forms the first electrode, the second electrically conductive material forms the second electrode, and a portion of the liner forms the tunnel barrier layer of the Josephson Junction. [0136] Example 13 provides the method according to Example 12, where the opening extends past the first layer by a depth of at least about 10% of a thickness of the support layer, including all values and ranges therein, e.g. at least about 30%, or at least about 50%.

[0137] Example 14 provides the method according to Examples 12 or 13, where a depth of the opening (i.e. a dimension measured along the z-axis of the x-y-z coordinate system shown in FIGS. 5A-5H) is between about 40 and 400 nm, including all values and ranges therein, e.g. between about 60 and 200 nm, or between about 80 and 100 nm.

[0138] Example 15 provides the method according to any one of Examples 12-14, where a width of the opening (i.e. a dimension measured along the y-axis of the x-y-z coordinate system shown in FIGS. 5A-5FI) is between about 20 and 300 nm, including all values and ranges therein, e.g. between about 40 and 200 nm, or between about 50 and 150 nm.

[0139] Example 16 provides the method according to any one of Examples 12-15, where the opening is a trench, and a length of the trench (i.e. a dimension measured along the x-axis of the x-y- z coordinate system shown in FIGS. 5A-5FI) is between about 20 and 300 nm, including all values and ranges therein, e.g. between about 40 and 200 nm, or between about 50 and 100 nm.

[0140] Example 17 provides the method according to any one of Examples 12-16, where a thickness of the first layer is between about 2 and 40 nm, including all values and ranges therein, e.g. between about 4 and 30 nm, or between about 6 and 20 nm.

[0141] Example 18 provides the method according to any one of Examples 12-17, where the first layer is patterned into a strip, where a width of the strip of the first layer is between about 5 and 40 nm, including all values and ranges therein, e.g. between about 7 and 30 nm, or between about 10 and 20 nm.

[0142] Example 19 provides the method according to any one of Examples 12-18, where a thickness of the support layer (i.e. a dimension measured along the z-axis of the x-y-z coordinate system shown in FIGS. 5A-5FI) is between about 10 and 300 nm, including all values and ranges therein, e.g. between about 20 and 100 nm, or between about 40 and 80 nm.

[0143] Example 20 provides the method according to any one of Examples 12-19, where depositing the liner includes performing ALD to conformally deposit the tunnel barrier material within the opening.

[0144] Example 21 provides the method according to any one of Examples 12-20, where a thickness of the liner is between about 1 and 8 nm, including all values and ranges therein, e.g. between about 1 and 4 nm, or between about 1 and 2 nm.

[0145] Example 22 provides a quantum 1C package that includes a qubit die and a further 1C element, where the qubit die is coupled to the further 1C element by one or more first-level interconnects. The qubit die includes a substrate, and one or more qubits, where at least one qubit includes a Josephson Junction over the substrate, the Josephson Junction including a first electrode, a second electrode, and a tunnel barrier layer between the first electrode and the second electrode, and where the plane of the tunnel barrier layer is at an angle less than about 50 degrees, including all values and ranges therein, e.g. less than about 30 degrees, or less than about 20 degrees, from a plane perpendicular to the substrate.

[0146] Example 23 provides the quantum 1C package according to Example 22, where the further 1C element is one of an interposer, a circuit board, a flexible board, or a package substrate.

[0147] Example 24 provides the quantum 1C package according to Examples 22 or 23, where the one or more qubits include a plurality of superconducting qubits, and where at least of a first and a second of the plurality of superconducting qubits are coupled by a coupling resonator.

[0148] Example 25 provides the quantum 1C package according to any one of Examples 22-25, where the Josephson Junction is a first Josephson Junction and the quantum circuit assembly further includes a second Josephson Junction including a first electrode, a second electrode, and a tunnel barrier layer between the first electrode and the second electrode, and where the first Josephson Junction and the second Josephson Junction form a SQUID.

[0149] Example 26 provides a quantum computing device that includes a quantum processing device and a memory device. The quantum processing device includes a die comprising a substrate and a plurality of qubits over or in the substrate, where one or more of the plurality of qubits include one or more quantum circuit assemblies according to any one of claims 1-11 or/and one or more quantum 1C packages according to any one of claims 22-25. The memory device is configured to store data generated by the plurality of qubits during operation of the quantum processing device.

[0150] Example 27 provides the quantum computing device according to Example 26, further including a cooling apparatus configured to maintain a temperature of the quantum processing device below 5 degrees Kelvin.

[0151] Example 28 provides the quantum computing device according to Examples 26 or 27, where the memory device is configured to store instructions for a quantum computing algorithm to be executed by the quantum processing device.

[0152] Example 29 provides the quantum computing device according to any one of Examples 26- 28, further including a non-quantum processing device coupled to the quantum processing device.

[0153] In further Examples, at least portions of the quantum processing device of the quantum computing device according to any one of Examples 26-29 may be fabricated using the method according to any one of Examples 12-21. [0154] The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.

[0155] These modifications may be made to the disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit the disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope of the disclosure is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.