Title:
WAFER SCALE PACKAGING TECHNIQUE FOR SEALED OPTICAL ELEMENTS AND SEALED PACKAGES PRODUCED THEREBY
Document Type and Number:
WIPO Patent Application WO2004068665
Kind Code:
A3
Abstract:
A wafer scale method for packaging semiconductor die or other devices in a sealed environment uses a plurality of wafers that are aligned and attached to each other to form an assembly. A front surface of a first wafer (10) has via regions (14) and laterally-extending conductors (15) electrically connected to metal at the via regions. Semiconductor die (25) or other devices are attached to thr front surface and electrically connected (28) to the conductors. A second wafer (20) has holes (22) which form recesses in which the semiconductor die or other devices and the vias are located. A third wafer (30) forms a cap for the recesses to provide a sealed environment (35) therein.
Inventors:
FOSTER RONALD (US)
MALSHE AJAY P (US)
O'NEAL CHAD (US)
MALSHE AJAY P (US)
O'NEAL CHAD (US)
Application Number:
PCT/US2004/001790
Publication Date:
September 22, 2005
Filing Date:
January 23, 2004
Export Citation:
Assignee:
UNIV ARKANSAS (US)
FOSTER RONALD (US)
MALSHE AJAY P (US)
O'NEAL CHAD (US)
FOSTER RONALD (US)
MALSHE AJAY P (US)
O'NEAL CHAD (US)
International Classes:
H01L23/10; H01L31/0203; (IPC1-7): B23K31/00; B23K31/02; H01L21/30; H01L21/46; H01L31/0203
Foreign References:
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| US6620731B1 | 2003-09-16 | |||
| US6257491B1 | 2001-07-10 | |||
| US6059188A | 2000-05-09 | |||
| US6798931B2 | 2004-09-28 | |||
| US5668033A | 1997-09-16 | |||
| US6096155A | 2000-08-01 | |||
| US5100480A | 1992-03-31 | |||
| US20030010431A1 | 2003-01-16 | |||
| US4144516A | 1979-03-13 | |||
| US20020180016A1 | 2002-12-05 |
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