SHIM YONGHYUN (US)
KR20110066395A | 2011-06-17 | |||
KR20050071012A | 2005-07-07 | |||
JP2012142285A | 2012-07-26 | |||
US6593672B2 | 2003-07-15 | |||
US20050275474A1 | 2005-12-15 | |||
EP1383234A1 | 2004-01-21 | |||
US20040214543A1 | 2004-10-28 | |||
US20080278249A1 | 2008-11-13 |
CLAIMS 1. A wide range tunable capacitor bank, comprising: a variable capacitor, the capacitance value of which is adjustable within a predetermined capacitance range defined by a minimum capacitance value and a maximum capacitance value; and one or more switched capacitors electrically connected in circuit to the variable capacitor; wherein the variable capacitor is configured to allow the capacitance value thereof to be adjusted within the predetermined capacitance range and the one or more switched capacitors are configured to be selectively actuated to permit continuous tuning of the capacitor bank over a second capacitance range that is greater than the predetermined capacitance range. 2. The capacitor bank of claim 1, wherein the second capacitance range extends from one of the minimum and maximum values of the predetermined capacitance range to past the other of the minimum and maximum values of the predetermined capacitance range. 3. The capacitor bank of claim 1, wherein the one or more switched capacitors comprises a plurality of switched capacitors, and further wherein each of the plurality of switched capacitors is electrically connected in circuit to the variable capacitor and the other of the plurality of switched capacitors. 4. The capacitor bank of claim 1, wherein the variable capacitor is a micro-electromechanical system (MEMS) variable capacitor, and the one or more switched capacitors are MEMS switched capacitors. 5. The capacitor bank of claim 1, wherein each of the one or more switched capacitors comprises one of: a combination of an ohmic switch and a capacitor; a capacitive switch; and a combination of a phase change switch and a capacitor. 6. The capacitor bank of claim 5, wherein each of the one or more switched capacitors has a first capacitance value corresponding to an un-actuated state and a second capacitance value corresponding to an actuated state, and further wherein the second capacitance value is greater than the first capacitance value and less than or equal to the maximum value of the variable capacitor. 7. The capacitor bank of claim 1, wherein each of the one or more switched capacitors comprises a combination of a switch and a variable capacitor, the capacitance value of the variable capacitor of each of the one or more switched capacitors being adjustable within a predetermined capacitance range corresponding thereto; and further wherein each of the one or more switched capacitors is configured such that when the switch thereof is actuated, the corresponding variable capacitor is configured to allow the capacitance value thereof to be adjusted within the predetermined capacitance range corresponding thereto to permit the further wide range tuning of the capacitor bank. 8. An electrical circuit, comprising: one or more resonator circuits, wherein each of the one or more resonator circuits comprises: a continuously tunable capacitor bank, the capacitor bank comprising a variable capacitor, the capacitance value of which is adjustable within a predetermined capacitance range defined by a minimum capacitance value and a maximum capacitance value, and one or more switched capacitors electrically connected in circuit to the variable capacitor, wherein the variable capacitor is configured to allow the capacitance value thereof to be adjusted within the predetermined capacitance range and the one or more switched capacitors are configured to be selectively actuated to permit continuous tuning of the capacitor bank over a second capacitance range that is greater than the predetermined capacitance range; and at least one inductive element electrically connected in circuit to the continuously tunable capacitor bank. 9. The electrical circuit of claim 8, wherein the one or more resonator circuits comprises a plurality of resonator circuits, and each of the plurality of resonator circuits is capacitively or inductively coupled to at least one other of the plurality of resonator circuits. 10. The electrical circuit of claim 9, wherein the plurality of resonator circuits combine to form at least a portion of one of a RF filter, a tunable antenna, a phase shifter, a balun, and a matching network. 11. The electrical circuit of claim 9, further comprising: a first port and a second port; and a first matching inductive element and a second matching inductive element; wherein the plurality of resonator circuits are disposed between the first and second ports, and further wherein the first matching inductive element is electrically connected between the first port and a first of the plurality of resonator circuits, and the second inductive element electrically connected between a second of the plurality of resonator circuits and the second port. 12. The electrical circuit of claim 9, wherein the plurality of resonator circuits are integrated on a single substrate to form an integrated micro- electromechanical system (MEMS). 13. The electrical circuit of claim 9, further comprising a single bias voltage line electrically coupled to the variable capacitor of each of the plurality of capacitor banks to allow for the simultaneous adjustment of the capacitance values of the variable capacitors. 14. The electrical circuit of claim 9, wherein the plurality of resonator circuits comprises three (3) resonator circuits. 15. A method of fabricating a micro-electromechanical system (MEMS) comprising a plurality of passive electrical components, the method comprising the steps of: (a) depositing and patterning a first metal layer on a substrate; (b) depositing and patterning a dielectric layer on top of the first metal layer; (c) depositing and patterning a first sacrificial layer on top of at least one of the dielectric layer and the first metal layer; (d) electroplating a second metal layer on top of at least one of the first sacrificial layer and the substrate; (e) depositing and patterning a second sacrificial layer on top of at least one of the second metal layer and the first metal layer; (f) electroplating a third metal layer onto at least one of the second sacrificial layer and the substrate; (g) removing the first and second sacrificial layers to form one or more gaps between those layers having the first or second sacrificial layers disposed therebetween. 16. The method of claim 15, wherein the plurality of passive electrical components comprises at least one variable capacitor and at least one capacitive switch, and further wherein: step (a) comprises patterning the first metal layer to form a first bottom electrode corresponding to the variable capacitor and a second bottom electrode corresponding to the capacitive switch; step (b) comprises patterning the dielectric layer to encompass each of the first and second bottom electrodes, respectively; step (c) comprises patterning the first sacrificial layer to encompass the first bottom electrode and the dielectric layer disposed thereon, and the second bottom electrode and the dielectric layer disposed thereon, respectively; and step (d) comprises electroplating the second metal layer on top of the first sacrificial layer disposed on top of each of the first bottom electrode and dielectric layer disposed thereon, and the second bottom electrode and dielectric layer disposed thereon, to form flexible membranes of each of the variable capacitor and capacitive switch. 17. The method of claim 16, further comprising the step (h) of depositing and patterning a fourth metal layer on top of the dielectric layer disposed on the second bottom electrode corresponding to the capacitive switch, wherein step (h) is performed after step (b) and prior to step (c). 18. The method of claim 15, wherein the plurality of passive components comprises an inductor, and further wherein step (f) comprises patterning the third metal layer to form the inductor. 19. The method of claim 15, wherein: the first metal layer comprises gold, the dielectric layer comprises aluminum oxide, the first sacrificial layer comprises poly-methylmethacrylate (PMMA), the second metal layer comprises gold, the second sacrificial layer comprises a photoresist material, and the third metal layer comprises copper. 20. The method of claim 15, wherein the plurality of passive components comprises a switched capacitor having a switch and a fixed capacitor, and further wherein: step (a) comprises patterning the first metal layer to form a bottom electrode of the switch and a bottom electrode of the fixed capacitor; step (b) comprises patterning the first dielectric layer to encompass the bottom electrode of the fixed capacitor; step (c) comprises patterning the first sacrificial layer to encompass the bottom electrode of the switch; and step (d) comprises electroplating the second metal layer on top of the sacrificial layer disposed on the bottom electrode of the switch to form a flexible membrane of the switch, and on top of at least a portion of the dielectric layer to form a top electrode of the fixed capacitor. |
If the desired capacitance of the capacitor bank 10 is between 0.5 and 1.0 pF, the capacitance value of the variable capacitor 12 can be adjusted to achieve the desired value without actuating any of the switched capacitors 14. However, if the desired capacitance of the capacitor bank 10 is between 1.0 pF and 2.0 pF, a combination of the adjustment of the variable capacitor 12 and the actuation of a first switched capacitor 14 1 (and possibly the adjustment of the variable capacitor 42 thereof) may be used to achieve the desired value. More particularly, the variable capacitor 12 may adjusted to its maximum value (e.g., 1 pF) and then the first switched capacitor 14 1 may be actuated. For the same reasons described above, simultaneous with the actuation of the first switched capacitor 14 1 , the variable capacitor 12 is de-tuned to its initial value (0.5 pF). When the actuation of the first switched capacitor 14 1 and the de-tuning of the variable capacitor 12 are simultaneous, the capacitance of the capacitor bank 10 will remain at 1.0 pF (i.e., 0.5 pF from the variable capacitor 12 and 0.5 pF from the switched capacitor 14 1 ). The value of one or both of the variable capacitors 12, 42 may then be adjusted within their respective ranges to acquire a desired capacitance value within the range of 1.0- 2.0 pF. Similar to the above, if the desired capacitance of the capacitor bank 10 is between 2.0 pF and 4.0 pF, a combination of the adjustment of the variable capacitor 12 and the actuation of the first and second switched capacitors 14 1 and 14 2 (and possibly the adjustment of the variable capacitors 42 thereof) may be used to achieve the desired value. More particularly, once the first switch 14 1 is actuated as described above, the variable capacitors 12, 42 may be adjusted to their maximum values, thereby resulting in a total capacitance of 2.0 pF (i.e., 1.0 pF from each of the variable capacitors 12, 42). At that point, the second switched capacitor 14 2 may be actuated. Simultaneous with the actuation of the second switched capacitor 14 2 , and for the same reasons described elsewhere above, the variable capacitor 12 and the variable capacitor 42 of the first switched capacitor 14 1 are de-tuned to their initial values (0.5 pF). When the actuation of the second switched capacitor 14 2 and the de-tuning of both the variable capacitor 12 and variable capacitor 42 of the first switched capacitor 14 1 are simultaneous, the capacitance of the capacitor bank 10 will remain at 2.0 pF (i.e., 0.5 pF from each of the variable capacitor 12 and the first switched capacitor 14 1 , and 1.0 pF from the second switched capacitor 14 2 ). The values of one or all of the variable capacitors 12, 42 may then be adjusted within their respective ranges to acquire a desired capacitance value within the range of 2.0-4.0 pF. Accordingly, as illustrated above, by adjusting the capacitance value of the variable capacitor 12 and either selectively actuating (or de-actuating) one or more of the switched capacitors 14, or selectively actuating (or de-actuating) one or more of the switched capacitors 14 and then adjusting the capacitance value(s) of the variable capacitor(s) 42 thereof, the capacitor bank 10 may be continuously tuned over a wide range of capacitances that exceeds the range of the variable capacitor 12, while also meeting or satisfying high performance standards. It will be appreciated by those of ordinary skill in the art that while the description above is limited to the continuous tuning of the capacitor bank 10 upwards (i.e., to higher capacitance values within the tuning range of the capacitor bank 10), a similar process in which the capacitance value of the variable capacitor 12 is adjusted, the switched capacitors 14 are selectively actuated and de-actuated, and the capacitance values of the variable capacitors of the actuated switched capacitors 14 are adjusted, may be used to continuously tune the capacitor bank 10 downwards (i.e., to lower capacitance values within the tuning range of the capacitor bank 10). It will be further appreciated that while the examples and description above are directed to an embodiment wherein the tuning of the capacitor bank 10 is continuous and smooth, the capacitor bank 10 may also be tuned in a non-continuous manner. More particularly, by adjusting the value of the variable capacitor 12 and selectively actuating the switches 40 of the switched capacitors 14 and possibly adjusting the values of the variable capacitors 42 thereof, the capacitor bank 10 can be tuned to any capacitance within the wide tunable capacitance range of the capacitor bank 10 either continuously or by jumping or hopping from one capacitance value to another within the range. As briefly described above, the capacitor bank 10 may lend itself to implementation in a number of applications. One such application is a RF filter that is tunable over a wide range of frequencies (e.g., 600-1000 MHz, for example). More particularly, in such an application, one or more tunable capacitor banks 10 may be employed in combination with other elements (e.g., inductive elements such as, for example, one or more inductors) to form a continuously tunable resonator circuit. One or more of the resonator circuits may, in turn, be combined to form, at least in part, a lumped RF bandpass filter. For example, Fig. 5 illustrates a third-order continuously tunable Chebyshev RF filter 58 comprising three (3) continuously tunable resonator circuits 59 (i.e., resonator circuits 59 1 , 59 2 , 59 3 ), each of which comprises a respective capacitor bank 10 (i.e., capacitor banks 10 1 , 10 2 , 10 3 ). Each of the resonator circuits 59 may be inductively or capacitively coupled to at least one other resonator circuit 59. For instance, in the illustrated embodiment, the resonator circuit 59 1 is inductively coupled with the resonator circuit 59 2 by a pair of mutually coupled inductive elements (e.g., inductors 60 1 , 60 2 ). Similarly, the resonator circuit 59 2 is inductively coupled with the resonator circuit 10 3 by a second pair of mutually coupled inductive elements (e.g., inductors 62 1, 62 2 ). In operation, and as will be described below, by tuning the capacitor banks 10 of the resonator circuits 59, the filter 58 may be tuned to a particular frequency band or a specific frequency within a given wide frequency band. Because, as described above, the capacitor banks 10 have such wide tuning ranges, the filter 58 may also have a wide frequency range such that it may be tuned to a frequency or frequency band within a much wider frequency range than conventional filters. In addition to the components described above, in an exemplary embodiment, the filter 58 further comprises a first or input port 64, a second or output port 66, a first matching inductive element (e.g., inductor 68) electrically connected between the input port 64 and the resonator circuit 59 1 , and a second matching inductive element (e.g., inductor 70) electrically connected between the output port 66 and the resonator circuit 59 3 . Mutually coupled inductive elements and inductive matching are utilized to provide wider frequency band matching and to avoid complicated tuning control of the filter 58. As with the capacitor bank 10, the filter 58 and each of the resonator circuits 59 and other components thereof may be fabricated in a number of ways, including, for example, using a surface micro-fabrication technology such as MEMS technology. In such an embodiment, the filter 58, or least certain components thereof, may be constructed as an integrated system formed on a single substrate or wafer to form a system-on-a-chip. Fig. 6 is a top plan view of an exemplary embodiment of the filter 58 in the form of a fully-integrated RF MEMS tunable filter. As illustrated in Fig. 6, the filter 58 comprises three capacitor banks 10 (each corresponding to a respective resonator circuit), two pairs of inductors (i.e., inductors 60 1 , 60 2 and 62 1 , 62 2 ) that function to inductively couple respective resonator circuits together, and the matching inductors (i.e., inductors 68, 70). In such an embodiment, electrical interconnects on the substrate may serve to connect those components that are to be electrically connected to each other. Further, the actuation electrodes 20 of the variable capacitors 12 of the capacitor banks 10 are tied together to a single bias or actuation line (best shown in Fig. 7) to allow for the simultaneous tuning of the variable capacitors 12, while corresponding switched capacitors 14 of each capacitor bank 10 are also tied to respective bias or actuation lines (best shown in Fig. 7) to allow for the simultaneous actuation of corresponding switched capacitors. More particularly, the actuation electrodes 20 of the first switched capacitors 14 1 of the capacitor banks 10 are tied together, the actuation electrodes 20 of the second switched capacitors 14 2 of the capacitor banks 10 are tied together, and the actuation electrodes 20 of the third switched capacitors 14 3 of the capacitor banks 10 are tied together. As a result, in an exemplary embodiment, only one bias or actuation line is required for the variable capacitors 12, and a number of bias or actuation lines equal to the number of switched capacitors 14 in one capacitor bank 10 are required for the switched capacitors (e.g., three bias or actuation lines where the capacitor banks 10 each include three switched capacitors) to tune the filter 58. As was described above, it will be appreciated that specific values for the various components of the resonator circuits 59 and other various components (e.g., inductors) of the filter 58 will be dependent upon a number of factors, including, for example, desired performance characteristics and design parameters or specifications of the filter 58, such as, for example, those relating to tuning range, tuning speed, temperature stability, power consumption and handling, insertion loss, and shape factor, to name a few. Therefore, the present disclosure is not meant to be limited to any particular values or ranges. For purposes of illustration, Table III identifies a number of exemplary target specifications for a particular filter.
(Table III) Based on these criteria, Table IV sets forth the values and ranges of the various components of the filter 58 that serve to meet most, if not all, of the specifications and parameters identified in Table III. Using the component values set forth in Table IV above, the operation of the filter 58 will now be described. As briefly described above, the filter 58 may be tuned to a particular frequency or frequency band by tuning the capacitance of the capacitor banks 10 of the resonator circuits 59. How the capacitor banks 10 are tuned depends on the particular frequency that is desired. Accordingly, in an exemplary embodiment, an arrangement such as that illustrated in Fig. 7 may be utilized to control the tuning of the capacitor banks 10, and therefore, the filter 58. More particularly, in an exemplary embodiment, a control unit 72 comprising a controller 74 and a power supply 76 is configured and operable to receive an input representative of a desired frequency or frequency band from, for example, a control unit input 78. Responsive to the received input, the controller 74 is configured to determine the required capacitance of the capacitor banks 10 needed to achieve the desired frequency. This may be accomplished by, for example, looking up the desired frequency in a data structure (e.g., look-up table), such as, for example, that set forth in Table V below, that may be stored in or on a memory 80 or other storage device that is part of or accessible by the controller 74.
Once the required capacitance is determined, the controller 74 is operable to tune the filter 58 to the desired frequency by appropriately tuning the capacitor banks 10. As described above with respect to the capacitor bank 10, this may comprise adjusting the variable capacitors 12 of the capacitor banks 10 and controlling the state of the switched capacitors 14 thereof, as necessary. More particularly, in an exemplary embodiment, the controller 74 is configured to adjust the bias voltage applied by the power supply 76 to the variable capacitors 12 of each capacitor bank 10, which in an exemplary embodiment entails adjusting bias voltage between 0-40 VDC, and to apply either a digital high (e.g., 40 VDC) or a digital low (e.g., 0 VDC) to the switched capacitors 14 to selectively control which, if any, switched capacitors 14 are actuated. As illustrated in Fig. 7, a plurality of bias lines 82 (i.e., bias lines 82 VC , 82 SC1 , 82 SC2 , 82 SC3 , 82 SCN ) may electrically connect the control unit 72 and the capacitor banks 10 to facilitate this control. Accordingly, in exemplary embodiment, the controller 74 may include any type of suitable electronic processor (e.g., a microprocessor, a microcontroller, an application specific integrated circuit (ASIC), etc.) that executes instructions for software, firmware, programs, algorithms, scripts, etc., and is not limited to any one type of component or device. The control unit input 78 may comprise any number inputs, such as, for example, a RF power meters, feedback from a component of the control unit 72, or any number of user interfaces known in the art, such as, for example, push buttons, switches, knobs, touch screens, keypads, keyboards, graphical user interfaces, and any other device suitable configured to allow the input or selection representative of a desired frequency or frequency band. Further, the memory device 80 may include any type of suitable electronic memory means and may store a variety of data and information. This includes, for example: the data structures correlating frequency with capacitance; software, firmware, programs, algorithms, scripts, and other electronic instructions; etc. Once the requisite capacitor bank capacitance value has been determined, the capacitor banks 10 may tuned to that capacitance value in the manner described in detail above. For example, in an exemplary embodiment, and using the data structure of Table V, if the desired frequency is within the frequency band of 811-1000 MHz, the capacitance of the capacitor banks 10 is adjusted to be within the capacitance range of 2.3-3.5 pF. As described above, the capacitance value of the variable capacitors 12 can be adjusted to achieve this capacitance value without having to actuate any of the switched capacitors 14. Accordingly, the controller 74 can adjust the capacitance value of the variable capacitors 12, and transmit a digital low signal to all of the switched capacitors 14 to keep them in an un-actuated state. However, if the desired frequency is within the frequency band of 707-824 MHz, the capacitance value of each capacitor bank 10 must be within the capacitance range of 3.4-4.6 pF, and therefore, a combination of the adjustment of the variable capacitors 12 and the actuation of a first switched capacitor 14 1 of the capacitor banks 10 may be used to achieve the required capacitance. More particularly, and as described above, the variable capacitors 12 may be adjusted to the maximum value of the switched capacitors 14 and then the first switched capacitors 14 1 may be actuated. Simultaneous with the actuation of the first switched capacitors 14 1 , and for the reasons described above, each of the variable capacitors 12 is de-tuned to its initial value. The variable capacitors 12 may then be adjusted again to acquire the required capacitance value. Similar to the above, if the desired frequency is within the frequency band of 635-715 MHz, the capacitance value of each capacitor bank 10 must be within the capacitance range of 4.5-5.7 pF, and therefore, a combination of the adjustment of the variable capacitors 12 and the actuation of a pair of switched capacitors 14 of each capacitor bank 10 may be used to achieve the required capacitance. More particularly, once the first switched capacitors 14 1 are actuated as described above, the variable capacitors 12 may once again be adjusted to the maximum value of the switched capacitors 14 and then the second switched capacitors 14 2 may be actuated. Again, and for reasons described above, the variable capacitors 12 are simultaneously de-tuned to their initial values upon the actuation of the second switched capacitors 14 2 . The variable capacitors 12 may then be adjusted again to acquire the required capacitance value. Finally, if the desired frequency is within the frequency band of 582-640 MHz, the capacitance value of each capacitor bank 10 must be within the capacitance range of 5.6-6.8 pF, and therefore, a combination of the adjustment of the variable capacitors 12 and the actuation of all three switched capacitors 14 1- 14 3 of each capacitor bank 10 may be used to achieve the required capacitance in a similar manner to that described above. Accordingly, the description will not be repeated here. Accordingly, by incorporating wide range continuously tunable capacitor banks 10 in the filter 58, the filter 58 may be continuously tuned over a wide range of frequencies while also meeting or satisfying high performance standards. As described above, some or all of the components of the filter 58 may be fabricated using a surface micro-fabrication technology such as MEMS technology. For example, the variable capacitor 12, the switched capacitors 14, and/or the fixed capacitor 16 of the capacitor bank 10 may be MEMS components. When each of the aforementioned components are MEMS components, they may be combined to form a MEMS capacitor bank 10. Similarly, each pair of coupling inductors 60, 62 and/or matching inductors 68, 70 may also be fabricated using MEMS technology to form the resonator circuits 59 and the RF filter 58 as an integrated MEMS resonator circuit and filter, respectively, disposed on a single substrate or wafer (i.e., an integrated system on a chip). It will be appreciated that while the description above has primarily been directed to an embodiment wherein the aforementioned components are MEMS components, those of ordinary skill in the art will appreciated that some or all of those components may comprise components other than MEMS components, and may be fabricated using technologies other than MEMS technology. Accordingly, the present disclosure is not meant to be limited to any one particular type of component or fabrication technology. However, in an embodiment wherein components such as those described above are MEMS components, they may be fabricated using the methodology illustrated in Figs. 8-9h. Accordingly, another aspect of this disclosure relates to a method 100 of fabricating a MEMS comprising one or more passive electrical components, including but not limited to, those components described in detail above. In an exemplary embodiment wherein the MEMS includes multiple passive electrical components, the multiple components are fabricated simultaneously. In an exemplary embodiment, the method 100 comprises a step 102 of providing a substrate, such as, for example, the substrate 200 shown in Fig. 9a. As described elsewhere above, the substrate may comprise a single- or multi-layer substrate. In an exemplary embodiment, the substrate 200 comprises a glass substrate, such as, for example, a Borosilicate glass substrate. It will be appreciated by those of ordinary skill in the art, however, that other suitable substrates exist that may also be used, including, for example, those formed of CMOS-grade silicon. Therefore, the present disclosure is not meant to be limited to any one particular type of substrate. With respect to Figs. 8 and 9a, the method 100 further comprises a step 104 of depositing and patterning a first metal layer 202 on the substrate 200 to form, for example, a portion of one or more of the passive components (e.g., the bottom (i.e., sense and actuation) electrodes of the capacitors and/or switches described above, bottom electrodes of MIM capacitors, etc.), or one or more interconnects that may be used to connect various components of the system disposed on the substrate 200. In an exemplary embodiment, the metal layer 202 deposited and patterned in step 104 comprises gold. More particularly, in an exemplary embodiment, the metal layer 202 comprises a combination of 300 Aº thick chromium, 5000 Aº thick gold, and 300 Aº thick chromium, though the present disclosure is not meant to be so limited. The first metal layer 202 may be deposited and patterned in a number of ways known in the art. In one embodiment provided for exemplary purposes only, a lift-off process is employed, though the present disclosure is not meant to be limited to such a technique or process. In an embodiment wherein a lift-off process is used, the step 104 may comprise a number of substeps. For example, first a layer of photoresist material is applied to all or a portion of the substrate 200. Next, the photoresist material is removed from the areas of the substrate 200 where the metal is to be placed using techniques well known in the art. The first metal layer 202 is then deposited on all or a portion of the substrate 200. The photoresist material and the portion of the metal layer 202 deposited on the photoresist material are then removed from the substrate 200. Following the depositing and patterning of the first metal layer 202 in step 104, a step 106 comprises depositing and patterning a dielectric layer 204. As illustrated in Fig. 9b, in an exemplary embodiment, step 106 comprises depositing and patterning the dielectric layer over the first metal layer 202. More particularly, in an embodiment wherein a portion of the first metal layer 202 serves to form one or more bottom electrodes of one or more capacitors or capacitive switches, the dielectric layer 204 may be patterned to encompass one or more of those bottom electrodes. In an exemplary embodiment, the dielectric layer 204 deposited and patterned in step 106 comprises aluminum oxide (Al 2 O 3 ). More particularly, in an exemplary embodiment, the dielectric layer 204 comprises a 500-1000 Aº thick layer of Al 2 O 3 , though the present disclosure is not meant to be so limited. The dielectric layer 204 may be deposited and patterned in a number of ways known in the art. In one embodiment provided for exemplary purposes only, the dielectric layer 204 is deposited using an atomic layer deposition (ALD) tool, and patterned using a suitable aluminum etchant, though the present disclosure is not meant to be limited to such techniques or processes. Once the dielectric layer 204 is deposited and patterned in step 106, in an exemplary embodiment wherein the system includes one or more switched capacitors comprising a capacitive switch, the method 100 may further comprise a step 108 of depositing and patterning another metal layer (not shown). More particularly, step 108 may comprise patterning a metal layer onto the dielectric layer 204 of a capacitive switch. The purpose of adding this additional metal layer is that surface of the dielectric material may be rough and/or the top electrode of the capacitive switch may be warped and so the contact between the top electrode of the capacitive switch and the dielectric material may not be ideal or optimal. Therefore, at the pull-down state, the capacitance of the capacitive switch may be limited to the contact area. By adding the metal layer on top of the dielectric, the capacitance value of the capacitive switch becomes independent of the contact area, and this, can be improved. Step 108 may be performed in the same or similar manner as step 104 described above, and therefore, the description will not be repeated here. With reference to Figs. 8, 9c, and 9d, in an exemplary embodiment, the method 100 may further include a step 110 of depositing and patterning a first sacrificial layer 206. More particularly, step 110 may comprise patterning the first sacrificial layer on top of at least a portion of the dielectric layer 204 (as shown in Fig. 9c) and/or the first metal layer 202 (or the metal layer resulting from step 108 above). In an exemplary embodiment wherein a portion of the first metal layer 202 comprises one or more bottom electrodes of one or more capacitors, switches, or capacitive switches, for example, the step 110 comprises patterning the sacrificial layer 206 to encompass one or more of the bottom electrode(s), and, if present, both the bottom electrode and the dielectric layer 204 disposed thereon. The sacrificial layer 206 is applied and patterned to define at least a portion of one or more gaps of one or more components, such as, for example, the actuation and sense gaps of the capacitors and switches described above, and gaps between interconnects (e.g., underpass interconnects) formed by metal layer 202 and components disposed thereabove. The particular material used for the sacrificial layer 206 is at least in part dependent upon the particular techniques and materials used in the other steps of the method 100. The sacrificial layer 206 may comprise, for example and without limitation, materials such as polymers, metals, silicon dioxide, and amorphous silicon, to name a few. In an exemplary embodiment, the sacrificial layer 206 comprises poly- methylmethacrylate (PMMA). In such an embodiment, the depositing and patterning of the PMMA may be performed using any number of techniques known in the art. In an exemplary embodiment, the depositing and patterning may comprise a number of substeps. For example, in one embodiment a layer of PMMA is first applied to the entire substrate 200 and the aforementioned layers already disposed thereon, followed by a layer of titanium tungsten (TiW) (e.g., having a thickness of approximately 500 Aº) on top of the PMMA layer. A layer of photoresist is then applied on top of the TiW. Next, the photoresist is patterned to remove photoresist material from areas in which no PMMA is desired. In the areas where the photoresist is removed, the TiW will be exposed. The TiW is then etched and the photoresist material is removed. The PMMA in those areas where there is no TiW is removed using, for example O 2 plasma. The remaining TiW is removed using, for example, a hydrogen peroxide (H 2 O 2 ) solution. In an exemplary embodiment, and with reference to Figs. 8 and 9e, following the deposition and patterning of the first sacrificial layer 206, the method 100 further comprises the step 112 of electroplating a second metal layer 208. More particularly, step 112 may comprise electroplating the second metal layer 208 on top of a portion of the sacrificial layer 206 and/or the substrate 200 or the other layers disposed thereon. The second metal layer 208 serves to form, for example, a portion of one or more of the passive components (e.g., the top electrodes or membranes of the capacitors and/or switches described above, the top electrodes of MIM capacitors, etc. of the switched capacitors described above, etc.) or one or more interconnects that may be used to connect various components of the system. In an exemplary embodiment, the electroplated second metal layer 208 comprises gold. More particularly, in an exemplary embodiment, the second metal layer 208 comprises a 4 μm thick layer of gold, though the present disclosure is not meant to be so limited. As is known in the art, the electroplating step 112 may comprise a number of substeps. For example, first, a seed layer of metallic material is applied to the entire substrate 200 and the aforementioned layers already disposed thereon. Next, a photoresist mold is applied to the wafer and patterned to cover areas of the substrate where the second metal layer 208 is not to be applied (e.g., over portions of the first metal layer 202, for example). After the mold is applied, the substrate 200 is electroplated to form the second metal layer 208. The mold and seed layer are then removed. In one exemplary embodiment, the second metal layer 208 is electroplated using a BDT-20 solution at 50 ºC and with a current density of 2 mA/cm 2 , though the present disclosure is not meant to be so limited. As illustrated in Figs. 8 and 9f, the method 100 may further comprise a step 114 of depositing and patterning a second sacrificial layer 210. More particularly, step 114 may comprise patterning the second sacrificial layer 210 on top of at least a portion of, for example, the electroplated second metal layer 208, the first metal layer 202, or the substrate 200 with the aforementioned layers disposed thereon. The purpose of the second sacrificial layer 210 is to define a gap between the portions of the already existing layers (e.g., layers 202, 204, 206) and a third metal layer (e.g., metal layer 212) to be described in a subsequent step. In an exemplary embodiment, the second sacrificial layer 210 comprises a photoresist material, such as, for example, Shipley 1813 photoresist, and it may be deposited and patterned using techniques well known in the art. Following the deposition and patterning of the second sacrificial layer 210, and with reference to Figs. 8 and 9g, the method 100 may further comprise a step 116 of electroplating a third metal layer 212. More particularly, step 116 may comprise electroplating a third metal layer onto at least a portion of the second sacrificial layer 210, the substrate 200, and/or the aforementioned layers already disposed on the substrate 200. The third metal layer 212 may be provided to form routing layers or interconnects between different components of the system, and/or to form one or more electrical components or portions thereof, such as, for example, one or more high quality factor inductors (e.g., the inductors of the filter 58 described above). In an exemplary embodiment, the third metal layer 212 comprises copper. More particularly, in an exemplary embodiment, the third metal layer 212 comprises a 35 μm thick copper layer, though the present disclosure is not meant to be so limited. As is known in the art, and as was described with respect to the electroplating step 112 above, the electroplating step 116 may comprise a number of substeps. For example, first, a seed layer of metallic material may be applied to the entire substrate 200 and the aforementioned layer disposed thereon. Next, a photoresist mold is applied to the substrate 200 and patterned to cover areas of the substrate where the third metal layer 212 is not to be applied (e.g., over portions of the first and second metal layers, for example). After the mold is applied, the substrate is electroplated to form the third metal layer 212. The mold and seed layer are then removed. Following the electroplating step 116, or following the electroplating step 112 in an embodiment wherein the method 100 does not include either step 114 (i.e., applying the second sacrificial) or step 116, the method may further comprise a step 118 of removing the sacrificial layer(s). In an exemplary embodiment, the sacrificial layers 206, 210 may be removed using any number of techniques known in the art, such as, for example, using a suitable photoresist stripper followed by acetone. In another exemplary embodiment, and as is known in the art, the sacrificial layers 206, 210 may be removed using O 2 plasma. Following the removal of the sacrificial layer(s), a critical point dryer may be used to alleviate or avoid stiction between the released metal layers and the layers underneath the released metal layers. It is to be understood that the foregoing description is of one or more embodiments of the invention. The invention is not limited to the particular embodiment(s) disclosed herein, but rather is defined solely by the claims below. Furthermore, the statements contained in the foregoing description relate to the disclosed embodiment(s) and are not to be construed as limitations on the scope of the invention or on the definition of terms used in the claims, except where a term or phrase is expressly defined above. Various other embodiments and various changes and modifications to the disclosed embodiment(s) will become apparent to those skilled in the art. As used in this specification and claims, the terms "e.g.,"“for example,”“for instance,”“such as,” and“like,” and the verbs“comprising,”“having,”“including,” and their other verb forms, when used in conjunction with a listing of one or more components or other items, are each to be construed as open-ended, meaning that the listing is not to be considered as excluding other, additional components or items. Other terms are to be construed using their broadest reasonable meaning unless they are used in a context that requires a different interpretation.
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