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Title:
WIRING BOARD AND LAMINATED CHIP CAPACITOR
Document Type and Number:
WIPO Patent Application WO/2016/170894
Kind Code:
A1
Abstract:
Disclosed is a laminated chip capacitor wherein a main body includes a first electrode layer, a second electrode layer, and a dielectric layer that is disposed between the first electrode layer and the second electrode layer. In a region of an upper surface of the main body, and in a region of a lower surface of the main body, a first terminal electrically connected to the first electrode layer is provided. In a region of the upper surface of the main body, and in a region of the lower surface of the main body, a second terminal electrically connected to the second electrode layer is provided. A first terminal portion that is provided on the upper surface occupies a larger area than a first terminal portion that is provided on the lower surface, and a second terminal portion that is provided on the lower surface occupies a larger area than a second terminal portion that is provided on the upper surface.

Inventors:
TANAKA, Daisuke (10-1, Higashikotari 1-chome, Nagaokakyo-sh, Kyoto 55, 〒6178555, JP)
Application Number:
JP2016/059099
Publication Date:
October 27, 2016
Filing Date:
March 23, 2016
Export Citation:
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Assignee:
MURATA MANUFACTURING CO., LTD. (10-1, Higashikotari 1-chome Nagaokakyo-sh, Kyoto 55, 〒6178555, JP)
International Classes:
H05K3/46; H01G2/06; H01G4/232; H01G4/30
Domestic Patent References:
WO2012005236A12012-01-12
Foreign References:
JP2014179578A2014-09-25
JP2014187127A2014-10-02
JP2014192321A2014-10-06
JP2014131039A2014-07-10
Attorney, Agent or Firm:
KITAYAMA, Mikio et al. (OWA PATENT FIRM, Tokyo Office 3rd Floor, Sankyo Building, 2-1-2, Koishikawa, Bunkyo-k, Tokyo 02, 〒1120002, JP)
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