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Patent Searching and Data


Title:
WIRING BOARD AND METHOD FOR MANUFACTURING SAME
Document Type and Number:
WIPO Patent Application WO/2014/045491
Kind Code:
A1
Abstract:
Provided is a wiring board having excellent reliability in connection with a semiconductor chip. On the board main surface (11) side of an organic wiring board (10), a first build-up layer (31) is formed, said build-up layer having laminated therein resin insulating layers (21, 22) and conductor layers (24). A conductor layer (24), i.e., the topmost layer of the first build-up layer (31), includes a plurality of connecting terminal sections (41) for flip-chip mounting a semiconductor chip. Each of the connecting terminal sections (41) is exposed through an opening (43) in a solder resist layer (25). Each of the connecting terminal sections (41) has a semiconductor chip connecting region (51), and a wiring region (52) that extends in the planar direction from the connecting region (51). The solder resist layer (25) has, in the opening (43), a side-surface covering section (55) that covers the side surface of each of the connecting terminal sections (41), and a protruding wall section (56), which is integrally formed with the side-surface covering section (55), and which protrudes to intersect the connecting region (51).

Inventors:
HAYASHI TAKAHIRO (JP)
NAGAI MAKOTO (JP)
MORI SEIJI (JP)
NISHIDA TOMOHIRO (JP)
WAKAZONO MAKOTO (JP)
ITO TATSUYA (JP)
Application Number:
PCT/JP2013/003137
Publication Date:
March 27, 2014
Filing Date:
May 17, 2013
Export Citation:
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Assignee:
NGK SPARK PLUG CO (JP)
International Classes:
H01L21/60; H01L23/12; H05K3/34; H05K3/46
Foreign References:
JPS534468A1978-01-17
JPH07321151A1995-12-08
JP2001156203A2001-06-08
JPS48112955U1973-12-24
JPH11340277A1999-12-10
JPS5239373A1977-03-26
JP2001320168A2001-11-16
JP2008147458A2008-06-26
Other References:
See also references of EP 2899751A4
Attorney, Agent or Firm:
AOKI, Noboru et al. (JP)
Aoki 昇 (JP)
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