WIRING STRUCTURE FOR INTEGRATED CIRCUIT WITH REDUCED INTRALEVEL CAPACITANCE

Title:

WIRING STRUCTURE FOR INTEGRATED CIRCUIT WITH REDUCED INTRALEVEL CAPACITANCE

Document Type and Number:

WIPO Patent Application WO2005104212

Kind Code:

A3

Abstract:

A method of forming a wiring structure for an integrated circuit includes the steps of forming a plurality of features (16) in a layer of dielectric material (13), and forming spacers (20) on sidewalls (16s) of the features. Conductors (25) are then formed in the features, being separated from the sidewalls by the spacers. The spacers are then removed, forming air gaps (40) at the sidewalls so that the conductors are separated from the sidewalls by the air gaps. Dielectric layers (42, 12) above and below the conductors may be low-k dielectrics having a dielectric constant less than that of the dielectric between the conductors. A cross-section of each of the conductors (25) has a bottom in contact with a low-k dielectric layer (12), a top in contact with another low-k dielectric (42), and sides in contact only with the air gaps (40). The air gaps serve to reduce the intralevel capacitance.

Inventors:

WISE RICHARD S (US)
CHEN BOMY A (US)
HAKEY MARK C (US)
YAN HONGWEN (US)

Application Number:

PCT/US2005/013601

Publication Date:

July 20, 2006

Filing Date:

April 21, 2005

Export Citation:

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Assignee:

IBM (US)
WISE RICHARD S (US)
CHEN BOMY A (US)
HAKEY MARK C (US)
YAN HONGWEN (US)

International Classes:

H01L21/4763; H01L21/44; H01L21/768; H01L23/522; H01L23/532

Foreign References:

US6228763B1	2001-05-08
US6661094B2	2003-12-09

Other References: