DESCRIPTION

Title of Invention

XNOR GATE AND BINARY CONVOLUTION CIRCUIT

Technical Field

This invention relates to an XNOR gate and a binary convolution circuit.

Background Art

Convolutional Neural Networks (CNN) have been introduced to perform object recognition [see NPL 1] and detection [see NPL 2] in real world applications. However, CNN-based recognition systems need a large amount of memory and computational power (such as ResNet-50 shown in NPL 2 in which 25.5M memory storage and 3.9G high precision Multiply-Accumulate (MAC) operations are needed) which limits their applications into Internet of Things (IoT) edge devices. To overcome these issues, a binary CNN [see NPL 3] has been proposed to binarize floating-/fixed-point inputs and weights to -1 and 1 to reduce memory storage significantly. Furthermore, the MAC operations are replaced by bit-wise XNOR (exclusive NOR) and bit-counting operations to reduce the computational resources (for example, memories).

In CNN hardware accelerators, SRAMs (Static Random Access Memories) are commonly utilized to store weight [see NPL 4]. Each weight coefficient is stored in one SRAM cell.

Citation List

Non Patent Literature

NPL 1 : S. Ren, K. He, R. Girshich et al.,“Faster r-cnn: towards real-time object detection with 2

region proposal networks”, IEEE Trans. Pattern Anal. Mach. IntelL, vol. 39, no. 6, pp. 1137-1149, 2017.

NPL 2: K. He, X. Zhang, S. Ren, J. Sun,“Deep residual learning for image recognition”, Computer Vision and Pattern Recognition (CVPR), 2016.

NPL 3: M. Rastegari, V. Ordonez, J. Redmon, A. Farhadi, “XNOR-Net: ImageNet classification using binary convolutional neural networks”. European Conference on Computer Vision (ECCV), 2016.

NPL 4: Y.-H. Chen, et al.,“Eyeriss: an energy-efficient reconfigurable accelerator for deep convolutional neural networks,” IEEE ISSCC, 2016.

Summary of Invention

Technical Problem

In CNN hardware accelerators, a binary convolution circuit 200 using SRAM cells is constructed as shown in Fig. 10. The binary convolution circuit 200 includes SRAM cells 210, 211, ..., 21(n-l), XNORs 220, 221, ..., 22(n-l) and a bit counter 230. Each of the typical SRAM cells 210, 211, ..., 21(n-l) includes six transistors. Each of the typical XNORs 220, 221, ..., 22(n-l) includes fourteen transistors. Each of the SRAM 210 and the XNOR 220, the SRAM 211 and the XNOR 221, and the SRAM 21(n-l) and the XNOR 22(n-l) implements an XNOR operation. Thus, twenty transistors are necessary for implementing the XNOR operation inputting one datum and one weight coefficient in the CNN hardware accelerators. As a result, in general, area of logic circuits in the CNN hardware accelerators becomes large.

Therefore, a technique for realizing logic circuits with small area is desired.

Solution to Problem 3

According to a first aspect of the present invention, an exclusive NOR (XNOR) gate includes an inverter, a first resistive switch whose first terminal is connected to an input terminal of the inverter, and a second resistive switch whose first terminal is connected to an output terminal of the inverter and whose second terminal is connected to a second terminal of the first resistive switch.

According to a second aspect of the present invention, in the XNOR gate of the first aspect, the first resistive switch and the second resistive may be a solid electrolyte switch including a film sandwiched between two metals.

According to a third aspect of the present invention, in the XNOR gate of the first aspect, the first resistive switch and the second resistive may be a resistance random access memory.

According to a fourth aspect of the present invention, in the XNOR gate of any one of the first to third aspects, each of the first and second resistive switches has an OFF/ON resistance ratio of larger than 10 ⁴ , the ratio being an OFF resistance with respect to an ON resistance.

According to a fifth aspect of the present invention, in the XNOR gate of any one of the first to fourth aspects, the first resistive switch or the second resistive switch may be at an ON state.

According to a sixth aspect of the present invention, a binary convolution circuit may include

a bit counter, and a plurality of the XNOR gates of any one of the first to fifth aspects which are connected to the bit counter.

According to a seventh aspect of the present invention, the binary convolution circuit of the sixth aspect may include the write circuit including column write transistors and row write transistors. According to an eighth aspect of the present invention, in the binary convolution circuit of the sixth or the seventh aspect, each of the XNOR gates may include a structure including one transistor and one nonvolatile resistive switch.

According to a ninth aspect of the present invention, in the binary convolution circuit of the sixth or the seventh aspect, each of the XNOR gates may include a structure including one transistor and two nonvolatile resistive switches.

Advantageous Effects of Invention

According to the Resistive-Switch-Logic (RSL) XNOR gate described above, the small XNOR gate can be provided.

Brief Description of Drawings

[Fig. 1] Figure 1 is a diagram which shows a configuration of a Resistive- Switch-Logic (RSL) XNOR gate according to a first exemplary embodiment of the present invention.

[Fig. 2] Figure 2 is a diagram which shows an operation principle of the RSL XNOR gate according to the first exemplary embodiment of the present invention.

[Fig. 3] Figure 3 is a diagram which shows a truth table of the RSL XNOR gate according to the first exemplary embodiment of the present invention.

[Fig. 4] Figure 4 is a diagram which shows a RSL binary convolution circuit according to a second exemplary embodiment of the present invention.

[Fig. 5] Figure 5 is a diagram which shows a RSL XNOR gate system with a write circuit according to a third exemplary embodiment of the present invention.

[Fig. 6] Figure 6 is a diagram which shows a RSL binary convolution circuit with a write circuit according to a fourth exemplary embodiment of the present invention.

[Fig. 7] Figure 7 is a diagram which shows a RSL binary convolution circuit with a write circuit according to a fifth exemplary embodiment of the present invention.

[Fig. 8] Figure 8 is a diagram which shows a RSL binary convolution circuit with a write circuit according to a sixth exemplary embodiment of the present invention

[Fig. 9] Figure 9 is a schematic block diagram which shows a configuration of a computer according to at least one embodiment.

[Fig. 10] Figure 10 is a diagram which shows an example of a binary convolution circuit to be compared.

Description of Embodiments

Exemplary embodiments of the present invention will be next described with reference to the accompanying drawings.

<First exemplary embodiment

Figure 1 illustrates a structure of a Resistive-Switch-Logic (RSL) XNOR (exclusive NOR) gate 10 according to a first exemplary embodiment of the present invention. The RSL XNOR gate 10 includes an inverter 10a and two Nonvolatile Resistive Switches (NRSs) SO and SI. The inverter 10a includes two transistors. Each of the NRSs SO and SI has OFF/ON resistance ratio larger than 10 ⁴ . The NRSs SO and SI construct a nonvolatile memory 10b. The nonvolatile memory 10b is used to store a weight coefficient of a CNN hardware accelerator. The nonvolatile memory 10b has a value“0” when the NRS SO is an OFF state and the NRS SI is an ON state. The nonvolatile memory 10b has a value“1” when the NRS SO is an ON state and the NRS SI is an OFF state. There are mainly two kinds of NRSs as examples of the NRSs SO and SI. One is a ReRAM (Resistance Random Access Memory). The ReRAM includes a transition metal oxide. The other is Nano Bridge (registered trademark of NEC Corporation). The Nano Bridge is a solid electrolyte switch including a film sandwiched between two metals. The Nano Bridge includes an ion 6

conductor. Each of the NRSs SO and S 1 is stacked on a CMOS (Complementary Metal Oxide Semiconductor) logic circuit. As a result, the area of the RSL XNOR gate 10 can be small. In addition, non- volatility of the nonvolatile memory 10b reduces the stand-by power of the RSL XNOR gate 10. Furthermore, a small resistance and a capacitance of the NRSs SO and SI contribute to high speed operation of the RSL XNOR gate 10.

Figure 2 illustrates the operation principle of the RSL XNOR gate 10. When the nonvolatile memory 10b has the value“0” and the input signal A is“0”, the output signal OUT is“1”. When the nonvolatile memory 10b has the value“0” and the input signal A is“1”, the output signal OUT is“0”. When the nonvolatile memory 10b has the value“1” and the input signal A is“0”, the output signal OUT is“0”. When the nonvolatile memory 10b has the value“1” and the input signal A is“1”, the output signal OUT is“1”. That is, when the logic value of the input signal A is different from the value that the nonvolatile memory 10b has, the output signal OUT becomes“0”. When the logic value of the input signal A is the same as the value that the nonvolatile memory 10b has, the output signal OUT becomes“1”. The truth table of the RSL XNOR gate 10 is shown in Fig. 3.

As described above, the RSL XNOR gate 10 according to the first embodiment includes an inverter 10a and two NRSs SO and SI. In this manner, the RSL XNOR gate 10 can be smaller than the XNOR shown in Fig. 10, for example.

<Second exemplary embodiment

Next, a second exemplary embodiment will be described.

Figure 4 illustrates a RSL binary convolution circuit 2 according to a second exemplary embodiment of the present invention. The RSL binary convolution circuit 2 includes the RSL XNOR gate 10 and the bit counter 230.

As described in the first exemplary embodiment, devices of the RSL XNOR gate 10 are less than devices of the binary convolution circuit 200. Therefore, the RSL binary convolution circuit 2 can be smaller than the binary convolution circuit 200 shown in Fig. 10.

As described above, the RSL binary convolution circuit 2 according to the second embodiment includes the RSL XNOR gate 10 and the bit counter 230. The RSL XNOR gate 10 is smaller than the SRAM cell and the XNOR of the binary convolution circuit 200. Thus, the RSL binary convolution circuit 2 is smaller than the binary convolution circuit 200.

<Third exemplary embodiment

Next, a third exemplary embodiment will be described.

Figure 5 illustrates a RSL XNOR gate system 20 with a write circuit according to a third exemplary embodiment of the present invention. The RSL XNOR gate system 20 includes the RSL XNOR gate 10, two write drivers X and Y, two column write transistors Mgo and MYI, a row write transistor Mxo, and two transistors Miso and Misi. The transistors MYO and MYI are used to select column in order to implement write operations. The transistor Mgo is controlled by a signal Y0. The transistor MYI is controlled by signal Yl. The transistor Mxo is used to select row in order to implement write operations. The transistor Mxo is controlled by signal X0. The transistors Miso is used to isolate an input signal A from the NRS SO. The transistor Misi is used to isolate an inverse signal Abar of the input signal A from NRS SI. In a write operation mode, a signal APON is set as“0” to turn off the transistors Miso and Misi and to isolate the NRSs SO and SI from the signal A and its inverse signal Abar. In addition, in the write operation mode, the signals X0, Y0 and Yl are set to select one of NRSs SO and SI. In an application mode, the signal X0, Y0, and Yl are set as “0” to isolate NRSs SO and SI from the write drivers X and Y. In addition, in the application mode, the signal APON is set as“1” to turn on the transistors Miso and Misi to apply the signal A to NRS SO and to apply its inverse signal Abar to NRS S 1.

As described above, the RSL XNOR gate system 20 with the write circuit according to the third exemplary embodiment of the present invention includes the RSL XNOR gate 10, the 8

two write drivers X and Y, the two column write transistors MYO and Mgi, the row write transistor Mxo, and the two transistors Miso and Misi. In this manner, the RSL XNOR gate system 20 can be smaller than the typical SRAM cell and the XNOR shown in Fig. 10, for example.

<Fourth exemplary embodiment

Next, a fourth exemplary embodiment will be described.

Figure 6 illustrates a RSL binary convolution circuit 30 with a write circuit according to a fourth exemplary embodiment of the present invention. For example, the RSL binary convolution circuit 30 is a 4-bit RSL binary convolution circuit. The RSL binary convolution circuit 30 includes an 8x4 crossbar, a write circuit and a bit counter 230. The 8x4 crossbar includes eight input terminals IN0 to IN7 and four output terminals OUTO to OUT3. The NRSs S00, SOI, S10, SI 1, S20, S21, S30 and S31 are located at the cross points of (IN0, OUTO), (INI, OUTO), (IN2, OUT1), (IN3, OUT1), (IN4, OUT2), (IN5, OUT2), (IN6, OUT3) and (IN7, OUT3), respectively. An input signal A0 is applied to the input terminal IN0. An input inverse signal AObar of the input signal A0 is applied to the input terminal INI. An input signal A1 is applied to the input terminal IN2. An input inverse signal Albar of the input signal A1 is applied to the input terminal IN3. An input signal A2 is applied to the input terminal IN4. An input inverse signal A2bar of the input signal A2 is applied to the input terminal IN5. An input signal A3 is applied to the input terminal IN6. An input inverse signal A3bar of the input signal A3 is applied to the input terminal IN7. The output terminals OUTO to OUT3 are connected to the bit counter 230. The write circuit includes two write drivers X and Y, eight column write transistors MYO to MY7, four row write transistor Mxo to MX3. The transistors MYO to Mgg are used to select column in order to implement write operations. The transistors Mgo, Mgi, Mg2, Mg3, MU4, MYS, Mgb, and Mgg are controlled by signals YO, Yl, Y2, Y3, U4, U5, U6, and U7, respectively. The transistors Mco to Mc3 are used to select row in order to implement write operations. The transistors Mxo to Mx ₃ are controlled by signals X0, XI, X2, and X3, respectively. The transistor Miso is used to isolate the input signal AO from the NRS S00. The transistor Misi is used to isolate the input inverse signal AObar from NRS SOI. The transistor M _IS 2 is used to isolate the input signal A1 from the NRS S10. The transistor MI _S 3 is used to isolate the input inverse signal Albar from NRS SI 1. The transistor M _IS 4 is used to isolate the input signal A2 from the NRS S20. The transistor Miss is used to isolate the input inverse signal A2bar from NRS S21. The transistor MIS6 is used to isolate the input signal A3 from the NRS S30. The transistor MIS7 is used to isolate the input inverse signal A3bar from NRS S31.

As described above, the RSL binary convolution circuit 30 with the write circuit according to the fourth exemplary embodiment of the present invention includes the 8x4 crossbar, the write circuit and the bit counter 230. In this manner, the RSL binary convolution circuit 30 can be smaller than the binary convolution circuit 200 with a write circuit, for example.

<Fifth exemplary embodiment

Next, a fifth exemplary embodiment will be described.

Figure 7 illustrates a RSL binary convolution circuit 30 with a write circuit according to a fifth exemplary embodiment of the present invention. For example, the RSL binary convolution circuit 30 is a 4-bit RSL binary convolution circuit. The RSL binary convolution circuit 30 has eight 1-transistor 1-NRS (1T1R) structures as shown in Fig. 7. The RSL binary convolution circuit 30 shown in Fig. 7 is different from the RSL binary convolution circuit 30 shown in Fig. 6 in that the selection transistor is added at each cross point of (IN0, OUTO), (INI, OUTO), (IN2, OUT1), (IN3, OUT1), (IN4, OUT2), (IN5, OUT2), (IN6, OUT3) and (IN7, OUT3). The selection transistors M00, M01, M10, Mi l, M20, M21, M30, and M31 are serially connected to NVRs S00, SOI, S10, SI 1, S20, S21, S30, and S31, respectively. The 10

selection transistors MOO, M01, M10, Mi l, M20, M21, M30, and M31 are used to access the selected NRS and isolate unselected NRSs for high write reliability. Also, a write enable transistor is added between the driver X and the row write transistor at each row. The write enable transistor MEO is serially connected to the transistor Mxo. The write enable transistor MEI is serially connected to the transistor Mci. The write enable transistor ME2 is serially connected to the transistor Mx2. The write enable transistor M _E 3 is serially connected to the transistor Mc3. A write enable signal WE is applied to all the gate terminals of the transistors MEO, MEI, M _E 2 and ME3 to isolate the driver X from the transistors Mco, Mci, Mx2 and Mx3 in the application mode. A row write control signal X0 is applied to the gate terminals of the transistors Mxo, MOO, and M01. A row write control signal XI is applied to the gate terminals of the transistors Mci, M10, and Ml 1. A row write control signal X2 is applied to the gate terminals of the transistors Mc2, M20, and M21. A row write control signal X3 is applied to the gate terminals of the transistors Mc3, M30, and M31.

As described above, the RSL binary convolution circuit 30 with the write circuit according to the fifth exemplary embodiment of the present invention includes the selection transistors MOO, M01, M10, Mi l, M20, M21, M30, and M31 serially connected to the NVRs S00, SOI, S10, SI 1, S20, S21, S30, and S31, respectively. In this manner, write reliability of the RSL binary convolution circuit 30 can be higher than that of the binary convolution circuit 200 with a write circuit, for example.

<Sixth exemplary embodiment

Next, a sixth exemplary embodiment will be described.

Figure 8 illustrates a RSL binary convolution circuit 30 with a write circuit according to a sixth exemplary embodiment of the present invention. For example, the RSL binary convolution circuit 30 is a 4-bit RSL binary convolution circuit. The RSL binary convolution circuit 30 includes eight 1-transistor 2-NRSs (1T2R) structures as shown in Fig. 8. The 1T2R 11

structure has been introduced in U.S. Patent No. 8,816,312 to improve OFF-state reliability. In the RSL binary convolution circuit 30, two NRSs (SOOa and SOOb, SOla and SOlb, SlOa and SlOb, SI la and SI lb, S20a and S20b, S21a and S21b, S30a and S30b, and S31a and S31b) are connected in series, in which two OFF-state NRSs complementarily divide the voltage stress, greatly enlarging the OFF-state lifetime of using only one NRS. The common terminal of the two serially-connected NRSs is connected to the source of a selection transistor whose gate is connected to one of the row write control signals X0 to X3. The drain of the selection transistor (each of transistors MOO, M01, M10, Mi l, M20, M21, M30, and M31) is connected to another write driver Z via one of write transistors Mzo to Mz7-

As described above, the RSL binary convolution circuit 30 with the write circuit according to the sixth exemplary embodiment of the present invention includes the eight 1-transistor 2-NRSs (1T2R) structures. In this manner, the OFF-state lifetime of the RSL binary convolution circuit 30 can be longer than that of the binary convolution circuit 200 with a write circuit, for example.

In the above-mentioned embodiments, the signals used to switch transistors between an ON state and an OFF state may be generated by controller.

It is apparent that the present invention is not limited to the above exemplary embodiments and examples, but may be modified and changed without departing from the scope and sprit of the invention.

In the processing in the embodiment of the present invention, the order of processing may be switched within a range in which appropriate processing is performed.

Each of the storage units may be provided in any place within a range in which transmission and reception of appropriate information are performed. In addition, a plurality of each of the storage units may be present within the range in which transmission and reception of appropriate information are performed, and may store data in a dispersed manner. 12

In the embodiments of the present invention, the controllers and other control devices described above may have a computer system therein. Then, processes of the processing described above are stored in a computer-readable recording medium in a form of program, and the processing is performed by a computer reading and executing this program. A specific example of the computer will be shown below.

FIG. 9 is a schematic block diagram which shows a configuration of a computer according to at least one embodiment.

A computer 5 includes, as shown in FIG. 9, a Central Processing Unit (CPU) 6, a main storage device 7, an auxiliary storage device 8, and an interface 9.

For example, each of the controllers and other control devices described above is mounted on the computer 5. Then, an operation of each processing unit described above is stored in the auxiliary storage device 8 in the form of program. The CPU 6 reads the program from the auxiliary storage device 8 to develop it in the main storage device 7 and executes the processing described above according to the program. In addition, the CPU 6 secures a storage area corresponding to each storage unit described above in the main storage device 7 according to the program.

Examples of the auxiliary storage device 8 include a hard disk drive (HDD), a solid state drive (SSD), a magnetic disk, a magneto-optical disc, a compact disc read only memory (CD-ROM), a digital versatile disc read only memory (DVD-ROM), a semiconductor memory, and the like. The auxiliary storage device 8 may be an internal media directly connected to a bus of the computer 5, and may also be an external media connected to the computer 5 via the interface 9 or a communication line. In addition, when this program is distributed to the computer 5 through a communication line, the computer 5 which receives this distributed program may develop the program in the main storage device 7, and execute the processing described above. In at least one embodiment, the auxiliary storage device 8 is a non-transitory tangible storage medium.

In addition, the program described above may realize some of the functions described above. Furthermore, the program may be a file, a so-called difference file (a difference program), which can realize the functions described above in combination with a program that is already recorded in a computer system.

Several embodiments of the present invention have been described, but these embodiments are examples, and do not limit the scope of the invention. Various additions, omissions, substitutions, and changes may be made in these embodiments within a range not departing from the gist of the invention.

While preferred embodiments of the invention have been described and illustrated above, it should be understood that these are exemplary examples of the invention and are not to be considered as limiting. Additions, omissions, substitutions, and other modifications can be made without departing from the spirit or scope of the present invention. Accordingly, the invention is not to be considered as being limited by the foregoing description and is only limited by the scope of the appended claims.

Industrial Applicability

The present invention relates to an XNOR gate and a binary convolution circuit.

Reference Signs List

2, 30 RSL binary convolution circuit

5 Computer

6 CPU

7 Main storage device

8 Auxiliary storage device 14

9 Interface

10 Resistive-Switch-Logic (RSL) XNOR (exclusive NOR) gate

10a Inverter

10b Nonvolatile memory

20 RSL XNOR gate system

200 Binary convolution circuit

210, 211, ..., 21(n-l) SRAM cell

220, 221, ..., 22(n-l) XNOR

230 Bit counter

MYO, MYI, MY2, MY3, MY4, MY5, MY6, MY7 Column write transistor

Mxo, Mxi, MX2, M 3 ROW write transistor

Miso, Misi, MIS2, MIS3, MIS4, MISS, MIS6, MIS7, MOO, MOl, M10, Ml 1, M20, M21, M30, M31, Mzo, Mzi, MZ2, MZ3, MZ4, MZS, MZ6, MZ7 Transistor

SO, SI, S00, SOI, S10, SI 1, S20, S21, S30, S31, SOOa, SOOb, SOla, SOlb, SlOa, SlOb, SI la, SI lb, S20a, S20b, S21a, S21b, S30a, S30b, S31a, S3 lb Nonvolatile Resistive Switch (NRS)

X, Y, Z Write driver