Title:
YIELD AND SPEED ENHANCEMENT OF SEMICONDUCTOR INTEGRATED CIRCUITS USING POST-FABRICATION TRANSISTOR MISMATCH COMPENSATION CIRCUITRY
Document Type and Number:
WIPO Patent Application WO2002073658
Kind Code:
A3
Abstract:
A novel technique for the enhancement of yield and speed of semiconductor integrated circuits using post fabrication transistor mismatch compensation circuitry is proposed. The system comprises of sense amplifier SA, multiplexer MUX, delay elements Delay-1, Delay-2, and provision for hardwiring fast and slow circuits during packaging. The sense amplifier firing path is split into slow and fast path and the multiplexer can select one of these paths. The memory circuits are tested after fabrication to assess whether they could be partitioned as slow or fast circuits and accordingly an appropriate path is selected by the multiplexer.
Inventors:
BHAT NAVAKANTA (IN)
MUKHERJEE SUGATO (IN)
MUKHERJEE SUGATO (IN)
Application Number:
PCT/IN2002/000039
Publication Date:
April 03, 2003
Filing Date:
March 11, 2002
Export Citation:
Assignee:
INDIAN INST SCIENT (IN)
BHAT NAVAKANTA (IN)
MUKHERJEE SUGATO (IN)
BHAT NAVAKANTA (IN)
MUKHERJEE SUGATO (IN)
International Classes:
G11C7/00; G11C7/06; G11C11/4091; G11C11/413; G11C29/50; H01L; (IPC1-7): G11C7/00
Foreign References:
| US4604534A | 1986-08-05 | |||
| US6181621B1 | 2001-01-30 |
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