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Title:
ZERO CROSS DETECTION CIRCUIT TO MINIMIZE RELAY-SWITCHING CURRENT
Document Type and Number:
WIPO Patent Application WO/2018/194538
Kind Code:
A1
Abstract:
A zero cross detection circuit is included in a system circuit for accurately detecting a zero cross event from an alternating current power source in the system circuit. The detecting zero cross event is monitored to accurately time a closing of a relay circuit component to control power to a load connected to the system circuit.

Inventors:
KOPCZYNSKI, Steven (9419 66th Street, Kenosha, WI, 53142, US)
Application Number:
US2017/027864
Publication Date:
October 25, 2018
Filing Date:
April 17, 2017
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
INTERMATIC INCORPORATED (7777 Winn Road, Spring Grove, IL, 60081, US)
International Classes:
H01H47/18; H03K5/1536
Foreign References:
US20150098164A12015-04-09
US20090027824A12009-01-29
US5804991A1998-09-08
Other References:
None
Attorney, Agent or Firm:
LEE, Peter (Brinks Gilson & Lione, P.O. Box 10087Chicago, IL, 60610, US)
Download PDF:
Claims:
CLAIMS

What is claimed is:

1 . A relay monitoring circuit comprising:

an alternating current power source;

a load electrically connected to the alternating current power source; a relay electrically connected to the load; and

a zero cross detection circuit comprising:

a resister;

an optocoupler including a light source and a phototransistor; and a switch electrically connecting the resister to the optocoupler.

2. The relay monitoring circuit of claim 1 , wherein the zero cross detection circuit is electrically connected in series with the alternating current power source and electrically connected in series with the load.

3. The relay monitoring circuit of claim 1 , wherein the zero cross detection circuit is electrically connected in parallel with the relay.

4. The relay monitoring circuit of claim 1 , wherein the optocoupler is configured to receive a power signal from the alternating current power source when the switch is closed and the relay is open.

5. The relay monitoring circuit of claim 4, wherein the optocoupler is configured to:

receive the power signal;

activate the light source from the power signal;

receive, by the phototransistor, a light emitted from the light source; and transmit, by the phototransistor, a zero cross detection signal in response to each zero cross event detected from the power signal.

6. The relay monitoring circuit of claim 1 , further comprising a system logic controller configured to:

receive a zero cross detection signal from the optocoupler;

control the relay to close based on the zero cross detection signal; and control the switch to open and to close based on the zero cross detection signal.

7. The relay monitoring circuit of claim 1 , further comprising a system logic controller configured to:

receive a zero cross detection signal from the optocoupler;

detect a falling edge of the zero cross detection signal;

initiate a relay close sequence based on the detection of the falling edge; start a timer starting from the detection of the falling edge;

determine whether a predetermined amount of time has elapsed in reference to the timer; when the predetermined amount of time has elapsed, transmit a relay close signal to the relay;

confirm the relay has closed based on a voltage measured across the relay measuring zero;

record, in reference to the timer, a first time measured from the detection of the falling edge to the confirmation the relay has closed; and

record, in reference to the timer, a second time measured from the transmission of the relay close signal to the confirmation the relay has closed.

8. The relay monitoring circuit of claim 7, wherein the system logic controller is further configured to:

calculate a subsequent predetermined amount of time as a difference between the first time and the second time.

9. The relay monitoring circuit of claim 1 , wherein the switch is a TRIAC output optocoupler.

10. The relay monitoring circuit of claim 1 , further comprising:

a diode electrically connected in parallel to the optocoupler to restrict reverse voltage across the optocoupler.

1 1 . A method for monitoring a relay circuit, the method comprising:

receiving a zero cross detection signal from the optocoupler; detecting a falling edge of the zero cross detection signal;

initiating a relay close sequence based on the detection of the falling edge; starting a timer starting from the detection of the falling edge;

determining whether a predetermined amount of time has elapsed in reference to the timer;

when the predetermined amount of time has elapsed, transmitting a relay close signal to a relay included in the relay circuit;

receiving a voltage measurement across the relay; and

confirming the relay has closed based on the voltage measured across the relay measuring zero.

12. The method of claim 1 1 , further comprising:

recording, in reference to the timer, a first time measured from the detection of the falling edge to the confirmation the relay has closed; and

recording, in reference to the timer, a second time measured from the transmission of the relay close signal to the confirmation the relay has closed.

13. The method of claim 12, further comprising:

calculating a subsequent predetermined amount of time as a difference between the first time and the second time.

14. A system logic controller comprising: an interface configured to receive a zero cross detection signal from an optocoupler; and

a controller configured to:

detect a falling edge of the zero cross detection signal; initiate a relay close sequence based on the detection of the falling edge;

start a timer starting from the detection of the falling edge;

determine whether a predetermined amount of time has elapsed in reference to the timer;

when the predetermined amount of time has elapsed, transmit a relay close signal to a relay;

receive a voltage measurement across the relay; and confirm the relay has closed based on the voltage measured across the relay measuring zero.

15. The system logic controller of claim 14, wherein the controller is further configured to:

record, in reference to the timer, a first time measured from the detection of the falling edge to the confirmation the relay has closed; and

record, in reference to the timer, a second time measured from the transmission of the relay close signal to the confirmation the relay has closed.

16. The system logic controller of claim 14, wherein the controller is further configured to:

calculate a subsequent predetermined amount of time as a difference between the first time and the second time.

Description:
ZERO CROSS DETECTION CIRCUIT TO MINIMIZE RELAY-SWITCHING

CURRENT

TECHNICAL FIELD

[0001] This application relates generally to a dynamic zero cross detection circuit for minimizing a current through a relay during a switching operation, as well as for detecting a status of the relay contact closure.

BACKGROUND

[0002] A zero cross detection circuit is included to detect when an AC voltage source crosses 0 V as the voltage oscillates between positive to negative, or negative to positive. The zero cross detection may be used as an input to a system logic controller to control the operation of circuit components within a circuit system. For example, the system logic controller may try to control the closing of relays included in the circuit systems to coincide with the zero cross occurrences.

SUMMARY

Technical Problem

[0003] The introduction of recent high efficiency loads (e.g., light emitting diode (LED) light fixtures), as well as the promotion of energy conservation, find many existing zero cross detection circuits unable to perform effectively or efficiently. Solution to Problem

[0004] A zero cross detection circuit is disclosed including a switch for controlling current being supplied to the zero cross detection circuit. By including the switch, a system circuit is able to control when to allow the current to flow through the zero cross detection circuit before initiating a relay closing sequence.

Advantageous Effects

[0005] Controlling the current through the zero detection circuit provides the benefit of promoting energy conservation by reducing excess power dissipation within the system circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a circuit diagram of an exemplary zero cross detection circuit.

[0007] Figure 2 is a circuit diagram of an exemplary system circuit including a zero cross detection circuit utilizing a dedicated switch.

[0008] Figure 3 is a circuit diagram of an exemplary system circuit including a zero cross detection circuit utilizing a TRIAC switch.

[0009] Figure 4 is a graph depicting an exemplary zero cross detection output.

[0010] Figure 5 is a flow diagram of an exemplary process for controlling a relay.

[0011] Figure 6 is a graph depicting the exemplary process for controlling a relay described in the flow diagram of Figure 5.

[0012] Figure 7 is a block diagram of exemplary computer architecture.

DETAILED DESCRIPTION

[0013] In circuits where the opening and closing of relays is used to control power supplied to a load, zero cross detection may be used to time the closing of the relays. The zero cross detection looks to detect the timing moment when an AC voltage supplied from a voltage source to the circuit experiences a zero cross event, which is when the AC voltage crosses from negative to positive, or positive to negative. The optimal time to close the relay is right at this zero cross event to avoid large current spikes that can deteriorate the circuitry hardware. To do this, an accurate prediction for when the zero cross events will occur is relied upon by system logic controllers.

[0014] An exemplary zero cross detection circuit 100 is shown in Figure 1. In the zero cross detection circuit 100, an AC power source 101 produces an AC voltage that passes through a current limiting resistor 102 and a rectifier 103 before the AC voltage reaches an optocoupler 1 10. The optocoupler 1 10 includes a light emitting source such as the light emitting diode (LED) 1 1 1 shown in Figure 1 , as well as a phototransistor 1 12. When the AC voltage provided by the AC power source 101 is positive, and the magnitude is high enough to trigger the light emitting diode 1 1 1 to emit light, the LED 1 1 1 beings emitting light. The light emitted by the LED 1 1 1 is received by the base of the phototransistor 1 12, which in turn biases the

phototransistor 1 12 to turn ON. When the phototransistor 1 12 is in the ON state, the collector of the phototransistor 1 12 is pulled to ground, which provides a zero cross detection signal to the system that the AC voltage is in the positive half of its cycle. The system may connect to a system logic controller 120 configured to receive the zero cross detection signal and control other components in a circuitry system. The system logic controller 120 may include hardware, software, and circuitry for implementing the control processes described herein.

[0015] When the AC voltage provided by the AC power source 101 goes negative, the LED 1 1 1 ceases emitting light, the base of the phototransistor 1 12 ceases receiving light, and the optocoupler 1 10 turns to an OFF state. This causes the collector in the phototransistor 1 12 to output another zero cross detection signal to the system that the AC voltage is in the negative half of its cycle. The diode 104 is positioned in the zero cross detection circuit 100 to protect the LED 1 1 1 from experiencing a high reverse voltage when the AC voltage goes negative. Through this process of changing the state of the optocoupler 1 10 from ON to OFF, and OFF to ON, each transition is detected by the system and recognized as a zero cross event.

[0016] While the zero cross detection circuit 100 shown in Figure 1 is simple and has been known to provide adequate results in many past applications, the zero cross detection circuit 100 has not been able to perform effectively and efficiently under new, more higher efficiency, standards. For example, to achieve a sharp transition output at the collector of the phototransistor 1 12 when the AC voltage passes through the zero cross point, the current through the LED 1 1 1 was previously a high current. As the AC power source 101 could range between, for example, 120- 277 VAC, selecting an effective and efficient resistance value for the current limiting resistor 102 was a difficult task. When the resistance value (low resistance) for the current limiting resistor 102 is chosen to provide good results for a voltage source of 120 VAC, the same resistance value when the voltage source is 277 VAC results in high power dissipation. Conversely, when the resistance value (high resistance) for the current limiting resistor 102 is chosen to provide good results for a voltage source of 277 VAC, the same resistance value when the voltage source is 120 VAC results in an output signal that is rounded and lacks the sharp transition to accurately detect the moment when the zero cross event occurs.

[0017] Therefore, many times the chosen resistance value for the current limiting resistor 102 is a compromise resistance value to account for the range in voltage sources (120-277 VAC) the zero cross detection circuit 100 may be used in. In most cases, this results in less than ideal outputs that are rounded and do not provide sharp transitions. The consequence of the rounded output signals is a greater error in accurately identifying the zero cross event timing.

[0018] Figure 4 shows a graph 400 illustrating an AC voltage from an AC power source (e.g., AC power source 101 ), and an ideal resulting zero cross detection signal output from an optocoupler (e.g., optocoupler 1 10). The zero cross detection signal output may be received by, for example, the system logic controller 120 described with reference to the zero cross detection circuit 100 in Figure 1. As shown by the graph 400 in Figure 4, the zero cross detection signal has edges that coincide with zero cross events by the AC power source 101 at times t-i , t 2 , t 3 , and - Now, when the resistance value for the current limiting resistor 102 is non-ideal and compromised, the zero cross detection signal will be rounded instead of the sharp edges shown by graph 400. When the edges of the zero cross detection signal are rounded, this makes it difficult for the system logic controller 120 to recognize the timing of the zero cross event. So instead, the system logic controller 120 resorts to a prediction calculation for the timing of the zero cross event, thus lowering the accuracy of the zero cross event detection.

[0019] Figure 2 shows a circuit diagram of an exemplary system circuit 200 including an AC power source 201 producing an AC voltage, load 220, relay 230, and a zero cross detection circuit 240. The load 220 may be a high efficiency light fixture such as an LED light fixture where even a low level of power may result in the light fixture turning on. The relay 230 is controlled by a system logic controller 250 to control power being supplied to the load 220. By closing the relay 230, current is allowed to flow through the load 220 to turn on the load. The zero cross detection circuit 240 is included to provide detection of zero cross events of the AC voltage supplied by the AC power source 201 . The zero cross detection signal output by the zero cross detection circuit 240 is received by the system logic controller prior 250 to the system logic controller 250 closing the relay 230 to supply current to the load 220. By detecting the zero cross events from the zero cross detection signal output by the zero cross detection circuit 240, the system logic controller 250 may time closure of the relay 230 accordingly to avoid a large current spike through the relay 230.

[0020] The zero cross detection circuit 240 is similar to the zero cross detection circuit 100 from Figure 1 . The zero cross detection circuit 240 includes a current limiting resistor 202, a diode 204, and an optocoupler 210 that includes an LED 21 1 and a phototransistor 212. However, the zero cross detection circuit 240 shown in Figure 2 replaces the rectifier 103 from the zero cross detection circuit 100 shown in Figure 1 , with a switch 203.

[0021] In the system circuit 200, the zero cross detection circuit 240 is in a series electrical connection with both the AC power source 201 and load 220. The zero cross detection circuit 240 is in a parallel electrical connection with the relay 230. As before, the system shown in the system circuit 200 may connect to a system logic controller 250 for controlling operation of one or more components included in the system circuit 200. For example, the system logic controller 250 may control the switch 203 and/or relay 230. The system logic controller 250 may include hardware, software, and circuitry for implementing the control processes described herein. [0022] Under this configuration, when the switch 203 is closed and the relay 230 is left open, the zero cross detection signal output from the collector of the phototransistor 212 will flow through the load 220. When the switch 203 is opened (or when the relay 230 is closed), this prevents the zero cross detection signal output from the collector of the phototransistor 212 from flowing through the zero cross detection circuit 240, which also results in no current through the load 220. By including the switch 203, the system circuit 200 has the option of preventing current from flowing through the load 220 when the zero cross detection circuit 240 is not being used. Without this option of opening and closing the system circuit 200 provided by the switch 203, a current through the zero cross detection circuit 240 would flow through to the load 220 based on the otherwise series connection between the zero cross detection circuit 240 and the load 220. This results in unnecessary power dissipation, as well as the unwanted occurrence of the load activating (e.g., high efficiency LED light fixture emitting light even from low current levels) from the current.

[0023] By switching out the diode 103 with the switch 203, the system circuit 200 achieves the benefit of power conservation as the switch 203 will remain open until a zero cross detection for closing the relay 230 (to turn on the load) is needed. Even when the switch 203 is closed to implement the zero cross detection by the zero cross detection circuit 240 to initiate a closing of the relay 230, because the current from the zero cross detection circuit 240 will only flow through the load 220 for a short amount of time (e.g., few hundred milliseconds) prior to the relay closing to close the system circuit 200 and turn on the load 220 (e.g., LED light fixture), whatever activation of the load 220 that results will only be for the short amount of time before the load 220 is activated by the closure of the relay 230, and may not be noticeable.

[0024] Also, the short duration during which the load 220 experiences the current from the zero cross detection circuit 240 due to the switch 203 being closed, also allows for a high current (by selecting a low resistance value for the current limiting resistor 102) through the zero cross detection circuit 240. The high current results in a good zero cross signal output from the zero cross detection circuit 240, which allows the system logic controller 250 to more accurately recognize the timing of the zero cross event. The high current is tolerable by the circuitry for the short amount of time.

[0025] Also, due to the improvement in conserving power by the system circuit 200, the system circuit 200 may utilize shunt rectification with diode 204 and the LED 21 1. This greatly improves the integrity of the zero cross detection signal output.

[0026] With the switch 203, the system logic controller 250 can confirm closure of the relay 230 because closure of the relay 230 will also cut off current through the zero cross detection circuit 240. So when the system logic controller 250 no longer detects a zero cross detection signal output, the system logic controller 250 confirms the relay 230 has closed and current is being provided to the load 220.

[0027] Figure 3 shows a circuit diagram of an exemplary system circuit 300 where a TRIAC output optocoupler is used as a switch 303. The system circuit 300 includes an AC power source 301 producing an AC voltage, load 320, relay 330, and a zero cross detection circuit 340. The load 320 may be a high efficiency light fixture such as an LED light fixture where even a low level of power may result in the light fixture turning on. The relay 330 is controlled by a system logic controller 350 to control power being supplied to the load 320. By closing the relay 330, current is allowed to flow through the load 320 to turn on the load. The zero cross detection circuit 340 is included to provide detection of zero cross events of the AC voltage supplied by the AC power source 301 . The zero cross detection signal output by the zero cross detection circuit 340 is received by the system logic controller 350 prior to the system logic controller 350 closing the relay 330 to supply current to the load 320. By detecting the zero cross events from the zero cross detection signal output by the zero cross detection circuit 340, the system logic controller 350 may time closure of the relay 330 accordingly to avoid a large current spike through the relay 330.

[0028] The zero cross detection circuit 340 is similar to the zero cross detection circuit 240 from Figure 2. The zero cross detection circuit 340 includes a current limiting resistor 302, a diode 304, and an optocoupler 310 that includes an LED 31 1 and a phototransistor 312. The zero cross detection circuit 340 shown in Figure 3 also specifically includes a TRIAC output optocoupler as the switch 303. The TRIAC output optocoupler is controlled to open, and close, to allow for, and prevent, current from flowing through the zero cross detection circuit 340 by a control side LED 305. The TRIAC output optocoupler may have a voltage rating of 600-800V and a current rating of more than 1.OA continuous.

[0029] In the system circuit 300, the zero cross detection circuit 340 is in a series electrical connection with both the AC power source 301 and load 320. The zero cross detection circuit 340 is in a parallel electrical connection with the relay 330. As before, the system shown in the system circuit 300 may connect to a system logic controller 350 for controlling operation of one or more components included in the system circuit 300. For example, the system logic controller 350 may control the switch 303, the relay 330, and/or the control side LED 305. The system logic controller 350 may include hardware, software, and circuitry for implementing the control processes described herein.

[0030] Under this configuration, when the switch 303 is closed and the relay 330 is left open, the zero cross detection signal output from the collector of the phototransistor 312 will flow through the load 320. When the switch 303 is opened (or when the relay 330 is closed), this prevents the zero cross detection signal output from the collector of the phototransistor 312 from flowing through the zero cross detection circuit 340, which also results in no current through the load 320. By including the switch 303, the system circuit 300 has the option of preventing current from flowing through the load 320 when the zero cross detection circuit 340 is not being used. Without this option of opening and closing the system circuit 300 provided by the switch 303, a current through the zero cross detection circuit 340 would flow through to the load 320 based on the otherwise series connection between the zero cross detection circuit 340 and the load 320. This results in unnecessary power dissipation, as well as the unwanted occurrence of the load activating (e.g., high efficiency LED light fixture emitting light even from low current levels) from the current. The system circuit 300 achieves the same benefits as system circuit 200.

[0031] Figure 5 shows a flow diagram 500 of a process implemented by a system logic controller to implement and monitor a relay closure process. The system logic controller may be, for example, the system logic controller 350 described as controlling components included in the system circuit 300. Reference will be made to the graph 600 shown in Figure 6. The graph 600 includes an AC power source graph 610 mapping a sinusoidal plot of an AC voltage supplied by, for example, the AC power source 301 and measured across the relay 330. The graph 600 also includes a zero cross detection signal graph 620 mapping a zero cross detection signal output by, for example, the zero cross detection circuit 340, as described herein. The graph 600 also includes a relay close signal graph 630 that maps a relay closing control signal output by, for example, the system logic controller 350 for closing the relay 330.

[0032] The system logic controller 350 initiates a relay close sequence for closing the relay 330 based on the detection of a falling edge of the zero cross detection signal (501 ). This way, the system logic controller holds the initiation of the relay close sequence until the falling edge of the zero cross detection signal is detected. In the zero cross detection signal graph 620, the falling edge of the zero cross detection signal occurs at time t 2 . At time t 2 , the AC power source graph 610 shows the AC voltage having a zero cross event as the AC voltage goes from negative to positive.

[0033] Also at time t 2 , the system logic controller 350 starts two timers (502). A first timer starts measuring an amount of time from the detection of the falling edge of the zero cross detection signal when the relay close signal is initiated, to when the relay 330 is detected to close (time T 2 - 4 ). A second timer starts measuring from the detection of the falling edge of the zero cross detection signal when the relay close signal is initiated, to when a predetermined amount of time has elapsed (time T 2 - a ). The predetermined amount of time is when the system logic controller 350 will transmit a relay close signal to the relay 330. [0034] The system logic controller 350 references the second timer to determine whether the predetermined amount of time described by the second timer has elapsed (503). When the predetermined amount of time has not elapsed, the second timer continues to measure an elapsed time (502).

[0035] When the system logic controller 350 determines the predetermined amount of time has elapsed, the relay close signal is transmitted to the relay 330 (504). In the relay close signal graph 630, the relay close signal is shown to go high at time t a , which is slightly before the next zero cross event at time t 3 . Although the relay close signal is transmitted to the relay 330 at time t a , the relay 330 will not close instantaneously.

[0036] So the system logic controller 350 continues to monitor the system circuit 300 to confirm the relay has closed (505). The system logic controller 350 does this by monitoring the voltage across the relay 330. When the voltage across the relay 330 goes to zero, this confirms the relay has closed. In the AC power source graph 610, the voltage is seen to return to zero at time , which is recognized by the system logic controller 350 as confirmation that the relay 330 has closed. Time t is also shown in the zero cross detection signal graph 620 as another falling edge in the zero cross detection signal, which is another indicator the relay 330 has closed.

[0037] After confirming the relay 330 has closed, the system logic controller 350 references the first timer to record an amount of time from the detection of the falling edge of the zero cross detection signal when the relay close signal is initiated, to when the relay 330 is detected to close (time T 2 - 4 ). The system logic controller 350 also references the first timer to record an amount of time from the relay close signal was transmitted at time t a , to when the relay 330 was confirmed as being closed at time t (time T a ^). Knowing time T 2 - 4 and T a - 4 allows the system logic controller 350 to then calculate a revised predetermined amount of time (T 2 - a ) which is used to determine an appropriate time to initiate the relay close signal at time t a to achieve actual relay close at a desired time in subsequent relay close sequences. By running the first timer to measure an elapsed time from the first falling edge of the zero cross detection signal at time t 2 to the confirmation of the relay close at time t , the system logic controller 350 achieves a more accurate calculation of the actual time from when the relay close signal is transmitted to when the relay closes. This takes into account real-time variances, and is more accurate than relying simply on a fixed value for the time between the relay close signal is transmitted to when the relay closes.

[0038] Figure 7 illustrates exemplary computer architecture for computer 700. Embodiments of computer 700, including embodiments that include additional components and embodiments including fewer components than described, may be representative of the system logic controller, or a larger computing system that includes the system logic controller, described herein.

[0039] Computer 700 includes a network interface device 720 that enables communication with other computers via a network 726. The computer 700 may include a processor 702, a main memory 704, a static memory 706, the network interface device 720, an output device 710 (e.g., a display or speaker), an input device 712, and a storage device 716, all connected via a bus 708.

[0040] The processor 702 represents a central processing unit of any type of architecture, such as a CISC (Complex Instruction Set Computing), RISC (Reduced Instruction Set Computing), VLIW (Very Long Instruction Word), or a hybrid architecture, although any appropriate processor may be used. The processor 702 executes instructions and includes portions of the computer 700 that control the operation of the entire computer 700. The processor 702 may also represent a controller that organizes data and program storage in memory and transfers data and other information between the various parts of the computer 700.

[0041] The processor 702 is configured to receive input data and/or user commands from the input device 712. The input device 712 may be a keyboard, mouse or other pointing device, trackball, scroll, button, touchpad, touch screen, keypad, microphone, speech recognition device, video recognition device, or any other appropriate mechanism for the user to input data to the computer 700 and control operation of the computer 700 to implement the features described herein. Although only one input device 712 is shown, in another embodiment any number and type of input devices may be included. For example, input device 712 may include an accelerometer, a gyroscope, and a global positioning system (GPS) transceiver.

[0042] The processor 702 may also communicate with other computers via the network 726 to receive instructions 724, where the processor may control the storage of such instructions 724 into any one or more of the main memory 704, such as random access memory (RAM), static memory 706, such as read only memory (ROM), and the storage device 716. The processor 702 may then read and execute the instructions 724 from any one or more of the main memory 704, static memory 706, or storage device 716. The instructions 724 may also be stored onto any one or more of the main memory 704, static memory 706, or storage device 716 through other sources. The instructions 724 may correspond to, for example, instructions that may be executed by the processor 702 to implement the selection tool described herein.

[0043] Although computer 700 is shown to contain only a single processor 702 and a single bus 708, the disclosed embodiment applies equally to computers that may have multiple processors and to computers that may have multiple busses with some or all performing different functions in different ways.

[0044] The storage device 716 represents one or more mechanisms for storing data. For example, the storage device 716 may include a computer readable medium 722 such as read-only memory (ROM), RAM, non-volatile storage media, optical storage media, flash memory devices, and/or other machine-readable media. In other embodiments, any appropriate type of storage device may be used.

Although only one storage device 716 is shown, multiple storage devices and multiple types of storage devices may be present. Further, although the computer 700 is drawn to contain the storage device 716, it may be distributed across other computers, for example on a server.

[0045] The storage device 716 may include a controller (not shown) and a computer readable medium 722 having instructions 724 capable of being executed by the processor 702 to carry out processes described herein. In another embodiment, some or all of the functions are carried out via hardware in lieu of a processor-based system. The storage device 716 may also contain additional software and data (not shown), which is not necessary to understand the features described herein.

[0046] Output device 710 is configured to present information to the user. For example, the output device 710 may be a display such as a liquid crystal display (LCD), a gas or plasma-based flat-panel display, or a traditional cathode-ray tube (CRT) display or other well-known type of display in the art of computer hardware. Accordingly, in some embodiments the output device 710 displays a user interface. In other embodiments, the output device 710 may be a speaker configured to output audible information to the user. In still other embodiments, any combination of output devices may be represented by the output device 710.

[0047] Network interface device 720 provides the computer 700 with connectivity to the network 726 through any suitable communications protocol. The network interface device 720 sends and/or receives data from the network 726 via a wireless or wired transceiver 714. The transceiver 714 may be a cellular frequency, radio frequency (RF), infrared (IR) or any of a number of known wireless or wired transmission systems capable of communicating with a network 726 or other computer device having some or all of the features of computer 700. Bus 708 may represent one or more busses, e.g., USB, PCI, ISA (Industry Standard Architecture), X-Bus, EISA (Extended Industry Standard Architecture), or any other appropriate bus and/or bridge (also called a bus controller). The network interface device 720 may also include a connection for receiving a signal through a connected circuit.

[0048] Computer 700 may be implemented using any suitable hardware and/or software, such as a personal computer or other electronic computing device. In addition to the various types of wearable devices described herein, computer 700 may also be a portable computer, laptop, tablet or notebook computer, PDA, pocket computer, appliance, telephone, or mainframe computer.

[0049] The present disclosure describes a relay monitoring circuit comprising an alternating current power source, a load electrically connected to the alternating current power source, a relay electrically connected to the load, and a zero cross detection circuit. The zero cross detection circuit may include a resister, an optocoupler including a light source and a phototransistor, and a switch electrically connecting the resister to the optocoupler.

[0050] The switch included in the zero cross detection circuit may be a TRIAC output optocoupler. The zero cross detection circuit may be electrically connected in series with the alternating current power source and electrically connected in series with the load. The zero cross detection circuit may be electrically connected in parallel with the relay. The optocoupler may be configured to receive a power signal from the alternating current power source when the switch is closed and the relay is open. The optocoupler may be configured to receive the power signal, activate the light source from the power signal, receive, by the phototransistor, a light emitted from the light source, and transmit, by the phototransistor, a zero cross detection signal in response to each zero cross event detected from the power signal. The relay monitoring circuit may further include a diode electrically connected in parallel to the optocoupler to restrict reverse voltage across the optocoupler.

[0051] The relay monitoring circuit may further include a system logic controller configured to receive a zero cross detection signal from the optocoupler, control the relay to close based on the zero cross detection signal, and control the switch to open and to close based on the zero cross detection signal.

[0052] The relay monitoring circuit may further include a system logic controller configured to receive a zero cross detection signal from the optocoupler, detect a falling edge of the zero cross detection signal, initiate a relay close sequence based on the detection of the falling edge, start a timer starting from the detection of the falling edge, determine whether a predetermined amount of time has elapsed in reference to the timer, when the predetermined amount of time has elapsed, transmit a relay close signal to the relay, confirm the relay has closed based on a voltage measured across the relay measuring zero, record, in reference to the timer, a first time measured from the detection of the falling edge to the confirmation the relay has closed, and record, in reference to the timer, a second time measured from the transmission of the relay close signal to the confirmation the relay has closed. The system logic controller may be further configured to calculate a subsequent predetermined amount of time as a difference between the first time and the second time.

[0053] The present disclosure also describes a method for monitoring a relay circuit, the method including receiving a zero cross detection signal from the optocoupler, detecting a falling edge of the zero cross detection signal, initiating a relay close sequence based on the detection of the falling edge, starting a timer starting from the detection of the falling edge, determining whether a predetermined amount of time has elapsed in reference to the timer, when the predetermined amount of time has elapsed, transmitting a relay close signal to a relay included in the relay circuit, receiving a voltage measurement across the relay, and confirming the relay has closed based on the voltage measured across the relay measuring zero.

[0054] The method may further include recording, in reference to the timer, a first time measured from the detection of the falling edge to the confirmation the relay has closed, and recording, in reference to the timer, a second time measured from the transmission of the relay close signal to the confirmation the relay has closed. The method may further include calculating a subsequent predetermined amount of time as a difference between the first time and the second time.

[0055] The present disclosure also describes a system logic controller comprising an interface configured to receive a zero cross detection signal from an optocoupler, and a controller configured to detect a falling edge of the zero cross detection signal, initiate a relay close sequence based on the detection of the falling edge, start a timer starting from the detection of the falling edge, determine whether a

predetermined amount of time has elapsed in reference to the timer, when the predetermined amount of time has elapsed, transmit a relay close signal to a relay, receive a voltage measurement across the relay, and confirm the relay has closed based on the voltage measured across the relay measuring zero.

[0056] The controller may further be configured to record, in reference to the timer, a first time measured from the detection of the falling edge to the confirmation the relay has closed, and record, in reference to the timer, a second time measured from the transmission of the relay close signal to the confirmation the relay has closed. The controller may further be configured to calculate a subsequent predetermined amount of time as a difference between the first time and the second time.

[0057] Each of the methods described herein may be encoded in a computer- readable storage medium (e.g., a computer memory), programmed within a device (e.g., one or more circuits or processors), or may be processed by a controller or a computer. If the processes are performed by software, the software may reside in a local or distributed memory resident to or interfaced to a storage device, a communication interface, or non-volatile or volatile memory in communication with a transmitter. The memory may include an ordered listing of executable instructions for implementing logic. Logic or any system element described may be implemented through optic circuitry, digital circuitry, through source code, through analog circuitry, or through an analog source, such as through an electrical, audio, or video signal. The software may be embodied in any computer-readable or signal-bearing medium, for use by, or in connection with an instruction executable system, apparatus, or device. Such a system may include a computer-based system, a processor- containing system, or another system that may selectively fetch instructions from an instruction executable system, apparatus, or device that may also execute instructions.

[0058] A "computer-readable storage medium," "machine-readable medium," "propagated-signal" medium, and/or "signal-bearing medium" may comprise a medium (e.g., a non-transitory medium) that stores, communicates, propagates, or transports software or data for use by or in connection with an instruction executable system, apparatus, or device. The machine-readable medium may selectively be, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, device, or propagation medium. A non- exhaustive list of examples of a machine-readable medium would include: an electrical connection having one or more wires, a portable magnetic or optical disk, a volatile memory, such as a Random Access Memory (RAM), a Read-Only Memory (ROM), an Erasable Programmable Read-Only Memory (EPROM or Flash memory), or an optical fiber. A machine-readable medium may also include a tangible medium, as the software may be electronically stored as an image or in another format (e.g., through an optical scan), then compiled, and/or interpreted or otherwise processed. The processed medium may then be stored in a computer and/or machine memory.

[0059] While various embodiments, features, and benefits of the present system have been described, it will be apparent to those of ordinary skill in the art that many more embodiments, features, and benefits are possible within the scope of the disclosure. For example, other alternate systems may include any combinations of structure and functions described above or shown in the figures.

INDUSTRIAL APPLICABILITY

[0060] The zero cross detection circuit may be used to more accurately and efficiently detect a zero cross event. The zero cross event may be referenced by a system logic controller to better time a relay closing sequence, resulting in minimized current spikes through the relay. Other circuit components may also benefit from the more accurate and efficient zero cross detection circuit.