Document |
Document Title |
WO/2019/212664A1 |
A cascaded clock ring network includes a clock path that transmits a source clock through series-connected processing nodes, from a first processing node to a last processing node. A data path transmits data through the processing nodes ...
|
WO/2019/208566A1 |
In a processor device according to the present invention a memory access device reads processing subject data from an external memory, and writes the data to a first register group which, among a plurality of register groups, is not bein...
|
WO/2019/199490A1 |
A plurality of synchronization FIFOs receive input data streams from corresponding transmitting agents. Data is written to the synchronization FIFOs based on write clock signals provided by the corresponding transmitting agents. An arbit...
|
WO/2019/183849A1 |
A data processing method and device. The method comprises: writing data in a first matrix into a register; carrying out a reading operation on the data of the first matrix in the register multiple times, wherein at least one piece of dat...
|
WO/2019/166771A1 |
Control apparatus to control operation of a data buffer to which data items are written according to a write pointer which advances in position in response to an input data item rate and from which data items are read according to a read...
|
WO/2019/144112A1 |
Methods for harmonization of test results from a biological sample in a multiplexed biochemical assay, wherein presence and/or concentration of multiple biomarkers are determined at the same time in the same sample, making test results o...
|
WO/2019/136094A1 |
A system and method for adapting an audios stream for reducing latency. The method may include the steps of, and the system may function to, receive an audio stream having a packet buffer and an audio buffer, measure the audio buffer dep...
|
WO/2019/126869A1 |
A system for operating a configuration platform. The system comprising a conversion pipeline, the conversion pipeline allowing converting a first set of data associated with a computer-aided design (CAD) system into polygon meshes suitab...
|
WO/2019/125265A1 |
The invention solves the problems of delay between signals intended for parallel / simultaneous reproduction, between a certain point until the signals have been sampled and have got a common clock domain. The delays are caused, for exam...
|
WO/2019/117854A1 |
The examples include methods and apparatuses to store events in a queue for an EC, Storing events in a queue for an EC can include receiving a message from a core FW of an EC and identifying an event corresponding to the message. Storing...
|
WO/2019/113628A1 |
Embodiments of the invention relate to methods and systems for processing a network data block. One or more embodiments of the invention include receiving network data at a receiver/transmitter comprising a serializer/deserializer (SERDE...
|
WO/2019/101350A1 |
A data bus comprises process elements and a linear main pipeline. Each process element is coupled to a linear pipeline having M stages arranged in series, each of the M stages comprising a buffer element configured to buffer a data bit s...
|
WO/2019/075504A1 |
Methods and systems for performing clock domain crossing. The method may include receiving a start signal from an ingress domain delay device at a first egress domain delay device. The start signal may be received at a first rising edge ...
|
WO/2019/054495A1 |
The purpose of the present invention is to provide a memory circuit device that enables the circuit to be downscaled. The memory circuit device is provided with: multiple memory cells 11, each comprising a variable resistance memory comp...
|
WO/2019/009993A1 |
Methods, systems, and apparatus, including an apparatus for transferring data using multiple buffers, including multiple memories and one or more processing units configured to determine buffer memory addresses for a sequence of data ele...
|
WO/2019/005424A1 |
Methods and systems for dynamically controlling buffer size in a computing device in a computing device ("PCD") are disclosed. A monitor module determines a first use case for defining a first activity level for a plurality of components...
|
WO/2018/232490A1 |
A multilevel queue based blockchain transaction traffic shaping method is disclosed. The method includes receiving a transaction request at the blockchain from a client; inserting the transaction into the first-level queue, and using the...
|
WO/2018/200274A1 |
At least some aspects of the present disclosure direct to systems and methods of extracting medical entry information from medical documentation. A method comprises the steps of: identifying patient information needed for a predefined me...
|
WO/2018/193707A1 |
[Problem] The purpose of the present invention is to provide an information processing device and the like with which it is possible to prevent an increase in circuit size. [Solution] This information processing device 1 is provided with...
|
WO/2018/144413A1 |
Superconducting devices with enforced directionality and related methods are provided. In one example, a device including a first Josephson junction transmission line (JTL) for propagating a first set of quantum signals in a first direct...
|
WO/2018/144347A1 |
An integrated circuit may have configurable storage blocks. A configurable storage block may include a memory array, and arithmetic and control circuitry. The arithmetic and control circuitry may be used to determine whether to operate t...
|
WO/2018/129930A1 |
A fast Fourier transform (FFT) processing method and device, and a computer storage medium. The method comprises: writing discrete digital signals in a discrete digital signal sequence into an upper memory and a lower memory according to...
|
WO/2018/057349A1 |
A control system controls First-In First-Out (FIFO) settings (30) of a receiving system (14) (14). The control system includes a FIFO settings controller (28) that receives a first signal indicative of a first frequency of data (16) rece...
|
WO/2018/042402A1 |
The invention relates to a software defined device interface system 10, a software defined device interface, gateway and a method of defining an interface for a device which uses a specific communication protocol for communication purpos...
|
WO/2018/031468A1 |
Some disclosed embodiments include a platform for secure data management and, in particular, for secure data management of smart city data. A method includes converting at least a portion of a first plurality of data streams from a plura...
|
WO/2018/027133A1 |
A system and method for obtaining a reissue of an electronic document lacking required data. The method includes creating a template for the electronic document, wherein the template is a structured dataset including at least one transac...
|
WO/2017/222576A1 |
Systems, apparatuses, and methods for implementing asynchronous feedback training sequences are described. A transmitter transmits a training sequence indication to a receiver via a communication channel including a plurality of data lin...
|
WO/2017/210798A1 |
A computer-implemented method for performing data storage. The method comprises the steps of: receiving data to be stored from a data source; segmenting the data into immutable core objects each being written into a collection and being ...
|
WO/2017/208182A1 |
A first memory device stores (i) a head part of a FIFO queue structured as a linked list (LL) of LL elements arranged in an order in which the LL elements were added to the FIFO queue and (ii) a tail part of the FIFO queue. A second memo...
|
WO/2017/207889A1 |
The invention relates to a method for processing data by means of a device (DV2) for parallel data processing comprising a unit (U1) configured to receive, on parallel inputs, a set (W) of binary words (wi). The method comprises a step c...
|
WO/2017/196693A1 |
An architecture and associated techniques of an apparatus for hardware accelerated machine learning are disclosed. The architecture features multiple memory banks storing tensor data. The tensor data may be concurrently fetched by a numb...
|
WO/2017/171983A1 |
Techniques described herein perform high fidelity combination of data, for example combining time series data in response to a query. In an embodiment, a first input data stream of a first type (e.g., continuous), a second input data str...
|
WO/2017/172050A1 |
A system with improved power performance for task executed in parallel. A plurality of processing cores each to execute tasks. An inter-core messaging unit to conveys messages between the cores. A power management agent transitions a fir...
|
WO/2017/151012A1 |
The invention relates to the field of processing machine readable information and can be used in the exercise of commercial operations and electronic and online commerce, and also in the creation of targeted and contextual audio advertis...
|
WO/2017/124186A1 |
A system for interactive virtual lighting of a virtual sample representative of a real-life manufactured object, based on data relative to the real-life manufactured object. A lighting calibration module generates user lighting condition...
|
WO/2017/101759A1 |
Methods and apparatus for managing data content among in-network caches of a communication network are provided. In some embodiments, multiple registers are maintained for indexing cached data content. Different data content is indexed i...
|
WO/2017/091254A1 |
Techniques for enabling a rapid clock frequency transition are described. An example of a computing device includes a Central Processing Unit (CPU) that includes a core and noncore components. The computing device also includes a dual mo...
|
WO/2017/068405A1 |
Systems and methods for detecting data in a received multiple-input-multiple-output signal are provided. N signals are received from N antennas, with M being greater than or equal to three. The N signals form a vector y and are associate...
|
WO/2017/039393A1 |
An apparatus and a method for processing data are provided. The method for processing data by a terminal, the method comprises: identifying a plurality of inspection types for a packet; determining at least one inspection type from the p...
|
WO/2017/040586A1 |
Methods and systems of controlling frequency regulation system controllers in a utility grid frequency regulation program are shown and described. One method includes providing historical frequency regulation data and energy storage devi...
|
WO/2017/027169A1 |
Apparatus and methods are disclosed for reordering data received in a non-contiguous order into a contiguous order. In one example of the disclosed technology, an apparatus includes a number of input buffers comprising at least a first, ...
|
WO/2017/009599A1 |
An integrated circuit includes multiple blocks of circuitry (4, 6, 8) communicating signals via an interface 10 controlled by a clock signal. A clock mesh (20, 22) is used on at least one side of the interface driven by one or more clock...
|
WO/2016/162872A1 |
A method of transforming data including receiving data in a first language specific form, converting the data in the first language specific form to a language agnostic form, storing the data in the language agnostic form, converting the...
|
WO/2016/145508A1 |
Systems and methods for the generation of timelines for emails found on a computer. The files relating to emails on a computer are first located on the machine. These files are then analyzed and each email is extracted into a separate fi...
|
WO/2016/071667A1 |
A processing apparatus (200) includes floating point arithmetic circuitry (214, 216) coupled to monitoring circuitry (226). The monitoring circuitry stores exponent limit data indicating at least one of a maximum exponent value and a min...
|
WO/2016/058355A1 |
Disclosed is a data caching method, comprising: according to an input port number of a cell, storing the cell in a corresponding first-in first-out queue; determining that a cell to be dequeued can be dequeued in the current Kth cycle, s...
|
WO/2016/045288A1 |
Disclosed are an asynchronous FIFO controller and a method for preventing data overflow of an asynchronous FIFO buffer. The method may comprise: an asynchronous FIFO controller acquires the data volume to be acquired by a second FIFO buf...
|
WO/2016/049350A1 |
Systems and methods are provided for determining identifier information associated with media content stored in a storage device; wherein the storage device comprises a plurality of clusters and stores a media file including media conten...
|
WO/2016/025487A1 |
Methods for monitoring subject compliance with a prescribed treatment regimen are disclosed. In an embodiment, the method comprises measuring a drug and a metabolite level in fluid of a subject and transforming the ratio of the measured ...
|
WO/2016/004629A1 |
The present invention relates to the technical field of data processing. Provided are an expected data compressibility calculation method and device. In the solution, the expected compressibility is calculated using related indicators ch...
|