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WO/2004/034401A2 |
Described are dynamic memory systems that perform overlapping refresh and data-access (read or write) transactions that minimize the impact of the refresh transaction on memory performance. The memory systems support independent and simu...
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WO/2004/029793A1 |
A method and system for performing many different types if algorithms utilizes a single mathematical engine (30) such that the mathematical engine is capable of utilizing the same multipliers for all of the algorithms. The mathematical e...
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WO/2004/027596A1 |
System for decompressing a program word that is subsequently delivered to a processor for execution. Program word fields are compressed based on regularities between operations and operands. The resulting microcode, is stored in program ...
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WO/2004/021113A2 |
A method and apparatus for achieving a non-disruptive code load that includes staging the new version of executable code, stacking the hardware events during code copy and code switch over, copying the code into the runtime area, restart...
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WO/2004/019202A2 |
A data retiming arrangement applies data to be retimed to a delay line. The data is applied concurrently with a data clock applied to a clock multiplexer and to a data counter, and a second clock applied to the clock multiplexer. The cou...
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WO/2004/001574A1 |
Methods and apparatuses for scheduling commands are described. According to various embodiments of the invention ,delay information (108, 112), is issued with an associated command (101, 103). The delay information (201, 206) directs the...
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WO/2003/107172A2 |
A FIFO-register (10) according to the invention comprises a sequence of register cells (10.1,...,10.m), which register cells have a data section (40) and a status section (30). Data (Din) provided at an input (20) is shifted via the data...
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WO/2003/104968A2 |
The invention is based on the idea to maintain two counters for an input or output port of a FIFO. A device for writing data elements from a coprocessor into a FIFO memory is provided. Said device is embedded in a multiprocessing environ...
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WO/2003/103766A2 |
A system for writing data efficiently between a fast clock domain and a slow clock domain. In one embodiment, a processor that performs firmware routines is clocked by a fast clock that is turned on when a prescribed event occurs to oper...
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WO/2003/100985A1 |
A method of packing a variable number of bits from an input bit stream into an output bit stream, comprising the steps of: defining a maximum number n of bits which are to be packed into the output bit stream within a clock cycle, provid...
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WO/2003/101024A2 |
A method and apparatus for generating and using symbol messages, which may include trademarks, registered trademarks, service marks, and other well-known symbols. Additionally, a method is provided for generating a symbol or logo alphabe...
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WO/2003/098446A1 |
Appropriate contents are distributed in accordance with the performance specification of a client device without preparing contents in a plurality of formats. When receiving a request for data list from a client, a server establishes, as...
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WO/2003/090063A2 |
This invention relates to a method and system for changing an output rate of information for a buffer (3) with a constant first output rate (R1) which receives output data from a data source (2a), where the method step comprises; halting...
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WO/2003/090064A1 |
Bit-rate scalable compression for storing A/V information in a pause buffer of a digital video recorder, providing a viewer of a live program to take a delayed decision about whether or not to record the program while still viewing the '...
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WO/2003/083642A2 |
The data processing system and method performs a mathematical operation on multi bit binary integer numbers using floating point arithmetic. The binary integer numbers are divided into corresponding segments and processed to determine at...
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WO/2003/077504A2 |
Disclosed is an interface (10, 40) between a master device (30) and a slave device (20). The interface includes a bit serial bidirectional signal line (10A) for conveying commands and associated data from the master device to the slave d...
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WO/2003/073296A2 |
A queuing system uses a common buffer for receiving input data from multiple-inputs, by allocating memory-elements in the common buffer to each input-stream, as the streams provide their input data. To allow for an independently controll...
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WO/2003/073290A1 |
The present invention allows for an increase in programming parallelism in a non-volatile memory system without incurring additional data transfer latency. Data is transferred from a controller(101) to a first memory chip (131-0) and a p...
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WO/2003/067469A2 |
A document transformation system (1) comprises a layout server (2) which dynamically generates output documents for delivery to a user device. The layout server (2) selects a layout template (5) according to user device and delivery chan...
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WO/2003/060692A2 |
Disclosed is a shifting device for shifting the first place of a data word consisting of a plurality of places to a second place so as to obtain a shifted data word. The first place is coded by means of a first coding parameter while the...
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WO/2003/058425A1 |
A system and method for determining the resources available or used in a remote device is disclosed. The system can be used to determine whether the remote device (106) is using expected resources as originally configured or to determine...
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WO/2003/048924A1 |
A Galois field linear transformer (28) includes a matrix responsive to a number of input bits in one or more bit streams and having a plurality of outputs providing the Galois field linear transformation of those bits; the matrix includi...
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WO/2003/046757A2 |
Systems and methods for processing documents are disclosed. Documents received at a data server are transcoded using locally stored or generated code books. Code books for transcoded documents received at a wireless mobile communication ...
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WO/2003/047113A1 |
A hybrid serial&sol parallel bus interface method for a user equipment (UE) has a data block demultiplexing device (40). The data block demultiplexing device (40) has an input configured to receive a data block and demultiplexes the data...
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WO/2003/044652A2 |
A buffer, having a first buffer input, a second buffer input, and a buffer output. The buffer is configured to store a plurality of data entries. The buffer includes: a first memory, the first memory having an input and an output. The in...
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WO/2003/042811A1 |
The invention relates to a method and a device for reading/writing data elements from/into a shared FIFO buffer, wherein the signalling that a data element or a storage space for a data element is available in a FIFO buffer, i.e. perform...
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WO/2003/042810A1 |
A V-operation not performed atomically for each data element or storage space that becomes available in a FIFO or a P-operation is not performed atomically for each request for a data element or a storage space in the FIFO but rather one...
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WO/2003/039061A2 |
A method and arrangement of passing data from a source clock domain to a non-synchronous receive clock domain are provided. A first processing circuit, located in the source clock domain, links write-address information with the data, an...
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WO/2003/036475A1 |
Described herein is a technology facilitating the operation of non-native program modules within a native computing platform. This technology provides a mechanism for aligning-as necessary-parameters of data structures so that program mo...
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WO/2003/032147A2 |
So-called LCH packets are defined in the Hiperlan Type 2 System for wire-free transmission of video and audio data streams. These LCH packets have a length of 54 data bytes. Furthermore, the Hiperlan/2 Standard provides for so-called ARQ...
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WO/2003/032157A1 |
A compiler capable of facilitating calculation description in a source program and simplifying the source program description so as to reduce generation of bugs in calculation according to the block floating method by software. When a so...
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WO2002071249A9 |
The invention relates to procedures and methods for administering and transferring data within multi-dimensional systems consisting of transmitters and receivers. The division of a data stream into several independent branches and the su...
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WO/2003/029953A2 |
The invention relates to a method which is characterised in that the data is stored or transferred together with an information message on the basis of which it can be determined in which order, at which time, and/or during which time sp...
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WO/2003/023600A2 |
An apparatus and method for extracting and loading data to/from a buffer are described. The method includes the selection of data from a data buffer in response to execution of a data access instruction. The data buffer includes a plural...
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WO/2003/019350A1 |
A hierarchical memory access control distinguishes between blocks of data that are known to be sequentially accessed, and the contents of each block, which may or may not be sequentially accessed. If the contents of a block are provided ...
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WO/2003/019351A2 |
First-in first-out (FIFO) memory devices include a plurality of memory devices that are configured to support any combination of dual data rate (DDR) or single data rate (SDR) write modes that operate in-sync with a write clock signal (W...
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WO/2003/017541A1 |
A variable size FIFO memory (13) is provided by the use of head (17) and tail (16) FIFO memories operating at a very high data rate and then an off chip buffer memory (18), for example, of a dynamic RAM type, which temporarily stores dat...
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WO/2003/012648A1 |
A data formatter (100) includes a shift register (112) and a pointer manager (120). The shift register (112) receives data from a providing RAM (108) and shifts that data in response to reading data from the providing RAM (108) and writi...
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WO/2003/007517A1 |
This invention relates to the field of packet communications. More particularly, this invention is a method and system for using a jitter absorption buffer to absorb propagation delay variation in packet arrival time. The invention uses ...
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WO/2003/007614A2 |
The invention regards a method for compressing a hierarchical tree describing a multimedia signal, said tree comprising nodes and leaves, which can be associated to contents of at least two distinct types.According to the invention, said...
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WO/2003/001360A2 |
A first-in, first-out (FIFO) memory system (10) includes first and second FIFOs (A and B). First and second multiplexers (12, 14) each have two input terminals for receiving data. An output terminal of the first multiplexer (12) is coupl...
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WO/2002/101938A2 |
According to the invention, in order to carry out an equidistant data transfer between clock pulse domains having different clock pulse rates, a combination of a counter (1) and a finite state machine (2) is used. Said counter (1) contin...
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WO/2002/099554A2 |
The invention relates to a power controlled electronic circuit comprising a controller which is used to process a processor task and a power determination device which determines the power available for the controller. A control device o...
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WO/2002/099621A1 |
A first in, first out (FIFO) circular buffer enables high speed streaming data transfer between integrated circuit devices by performing more than one data element transfer unidirectionally by having a plurality of ports to address a mem...
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WO/2002/097606A1 |
A system for providing a floating point product comprises an analyzer circuit configured to determine a first status of a first floating point operand and a second status of a second floating point operand based upon data within the firs...
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WO/2002/097607A1 |
A floating point unit generates results in which status information generated for an operation is encoded within the resulting operand, instead of requiring a separate floating point status register for the status information. In one emb...
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WO/2002/097620A2 |
The present invention provides safe and secure application distribution and execution by providing systems and methods that test an application to ensure that it satisfies predetermined criteria associated with the environment in which i...
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WO/2002/097604A2 |
A system for providing a floating point sum comprises an analyzer circuit configured to determine a first status of a first floating point operand and a second status of a second floating point operand based upon data within the first fl...
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WO/2002/093392A1 |
A data processor (1) comprises a central processing unit (2), a memory (5) accessible by the central processing unit, input/output circuits (12, 13), and a FIFO control circuit (6) for operating the memory as a FIFO buffer for the input/...
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WO/2002/093358A1 |
Distributed compression of a data file can comprise a master server module for breaking the data file into data blocks and transmitting the data blocks to worker server modules. A first worker server module can compress a first data bloc...
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