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Patent Searching and Data


Matches 1 - 50 out of 26,982

Document Document Title
WO/2022/165473A1
Systems and methods for generating custom applications for querying a multidimensional database of a target platform include, responsive to receiving a custom application request, an application definition is discovered based on data rec...  
WO/2022/162225A1
A random number generator (100) comprising a vertical cavity surface emitting laser, VCSEL (101), a mode separator (102) and a photodetector (103), the random number generator further comprising a power source (105) to drive the VCSEL in...  
WO/2022/164743A1
One or more types of laser scanner apparatuses (100) perform object detection by emitting laser pulses (114) and detecting corresponding reflected pulses by correlating a digitized detection signal against a correlation template represen...  
WO/2022/164678A1
The present disclosure includes digital circuits that generate values of a power of two (2) raised to an input value. For example, a digital circuit may include combinational logic that receives first digital bits representing an input m...  
WO/2022/158104A1
The present invention provides a random number generator, random number generation method, and program capable of high-quality random number generation following a desired distribution. A random number generator (1) according to the pres...  
WO/2022/159031A1
Embedded memory structures and methods of fabricating an embedded memory structure. In one embodiment, the method comprises providing an array of bitcells interconnected by a plurality of bitlines and a plurality of wordlines, each bitce...  
WO/2022/159154A1
A system includes an interface configured to receive a user input string for a data cell and a processor configured to: determine a lexicon from data related to the data cell; determine an efficient formula from the lexicon; and provide ...  
WO/2022/159072A1
A security device includes a covering device that, in response to an input signal, consistently provides a same random output signal that varies according to the microstructure of the covering device, where altering the microstructure of...  
WO/2022/157621A1
The present disclosure relates to collaborative engagement between a user, the user itself and its contacts of data stored in heterogeneous sources. The interface (100) includes a first repository (102) for storing machine defined rules,...  
WO/2022/152397A1
The present invention relates to a controller (1) for a cache (2). The cache (2) is configured to store one or more outputs of a computation unit (3). The controller (1) is configured to map input queries to one or more approximate input...  
WO/2022/155207A1
A request is received to perform a management action for a domain of a name service, wherein the name service is implemented using at least both a first blockchain network and a second blockchain network different from the first blockcha...  
WO/2022/155648A1
Various embodiments described herein relate to efficient and accurate context discovery of an asset system. In this regard, telemetry data comprising a plurality of data points associated with an asset system is received. The telemetry d...  
WO/2022/154965A1
Embodiments relate to a neural engine circuit of a neural network processor circuit that performs a convolution operation on input data in a first mode and a parallel sorting operation on input data in a second mode. The neural engine ci...  
WO/2022/154777A1
In some examples, a computing device stores root metadata data structures (DSs) together in a group root metadata filesystem block, and stores, in a data filesystem block, at least first file data referenced by the first root metadata DS...  
WO/2022/155120A1
A finite impulse response (FIR) filter including a delay line and a plurality of arithmetic units. Each arithmetic unit is coupled to a different one of a plurality of tap points of the delay line, is configured to receive a respective s...  
WO/2022/154881A1
A computing device, including a hardware accelerator configured to train a machine learning model by computing a first product matrix including a plurality of first dot products. Computing the first product matrix may include receiving a...  
WO/2022/150058A1
In one embodiment, multiplier circuitry multiplies operands of a first format. One or more storage register circuits store digital bits corresponding to an operand and another operand of the first format. A decomposing circuit decomposes...  
WO/2022/147889A1
The present application relates to the field of connecting members, and specifically relates to a quick-mounting structure. The quick-mounting structure comprises a first connecting member, a second connecting member, and a self-locking ...  
WO/2022/148181A1
The present application discloses a sparse matrix accelerated computing method and apparatus, a device, and a medium. The method comprises: reading a first sparse matrix to be multiplied, performing non-zero detection on the first sparse...  
WO/2022/142111A1
The present application relates to the technical field of artificial intelligence, and provides a random number generation method and apparatus, an electronic device, and a storage medium. The method comprises: parsing a random number ge...  
WO/2022/140976A1
An ADC conversion unit, and a true random number generating method and device. The ADC conversion unit (100) comprises: a first switched capacitor circuit (110), a second switched capacitor circuit (120), a sub-ADC circuit (130), a multi...  
WO/2022/147350A1
A method of preparing personalized supplement packages for a subject involves identifying one or a plurality of suboptimal wellness categories in the subject, rank ordering ingredients in terms of their utility score to the suboptimal co...  
WO/2022/146436A1
A computer processing hardware architecture system for the Kyber lattice-based cryptosystem which is created with high resource reuse in the compression and decompression module, the operation unit, the binomial samplers, and the operati...  
WO/2022/137863A1
The present invention is a random number tester that carries out random number testing for a random number generator. The random number tester is provided with: a register unit for storing a pseudorandom number string generated by a rand...  
WO/2022/140156A1
These teachings include accessing (201, 202) energy dosing information along with at least one quality-of-care model that correlates at least one categorical energy-based treatment patient quality-of-care outcome with at least one result...  
WO/2022/140796A1
Systems and methods for generating jewelry designs and models using machine learning are disclosed. In one embodiment, generating a custom jewelry design based on user preferences using machine learning includes displaying a graphical us...  
WO/2022/133774A1
A method and device for dynamically switching between Native and JavaCard, the method comprising: writing a compiled firmware version into a security chip, the firmware version comprising a Native COS and a JavaCard COS on the basis of c...  
WO/2022/140510A1
A processing unit [100] includes a first memory device [106] and a second memory device [108]. The first memory device includes a first plurality of general purpose registers (GPRs) [112] and the second memory device includes a second pl...  
WO/2022/136971A1
Multi-cache-based digital output generation is provided. A system receives data objects that include fields from a remote data source. The system sorts the data objects based on a field to generate a sorted data set. The system cleans th...  
WO/2022/133686A1
A device and method for multiplication-and-addition operation with/without symbols, which are suitable for a coarse-grained reconstructable processor architecture. The device comprises a splitting module, an operation module, a processin...  
WO/2022/128293A1
The present invention relates to an Entropy measurement method comprising the steps of a start-up phase comprising powering on the entropy source unity, a signal emitting step comprising emitting a quantum signal characterized by an over...  
WO/2022/131389A1
A field programmable gate array (FPGA) design method for a deep learning algorithm comprises: a module architecture design step of configuring a module architecture including at least one operation among a convolution operation, an add o...  
WO/2022/132614A1
A software-based instruction scoreboard (126) indicates dependencies between closely-issued instructions (302, 304, 306) issued to an arithmetic logic unit (ALU) pipeline (218). The software-based instruction scoreboard inserts one or mo...  
WO/2022/132186A1
A computer processing system having an isogeny-based cryptosystem for randomizing computational hierarchy to protect against side-channel analysis in isogeny-based cryptosystems.  
WO/2022/128292A1
The present invention relates to a RNG Chip testing method comprising a test start-up phase starting a Final Test phase, a data collection step wherein frames of bit sequences having a length of 1024 KB, preferably 512 KB generated by th...  
WO/2022/132654A1
A processing system (100) executes wavefronts (302, 304) at multiple arithmetic logic unit (ALU) pipelines (232, 234) of a single instruction multiple data (SIMD) unit (230) in a single execution cycle. The ALU pipelines each include a n...  
WO/2022/133267A1
Techniques for data lifecycle discovery and management are presented. Data lifecycle discovery platform (DLDP) can identify data of users, data type, and language of data stored in data stores (DSs) of entities based on scanning of data ...  
WO/2022/133178A1
An artificial intelligence (AI)-based knowledge distillation and paper production computing system processes instructions to use machine learning models to automatically review papers from a large corpus of papers and distill knowledge u...  
WO/2022/124010A1
The objective of the present invention is to shorten the processing time for calculating a specific number sequence by means of parallel arithmetic processing. A preparatory processing unit (11) uses a recurrence formula to determine ari...  
WO/2022/121149A1
A parallel finite field multiplication device, comprising M cascaded logic processing modules; a first input end of a first logic processing module receives a first operand; a second input end of the first logic processing module receive...  
WO/2022/121569A1
Techniques for noise and bound management for DNN training on RPU crossbar arrays using a scaling factor based on a worst-case scenario are provided. A method for noise and bound management includes: obtaining input vector values x for a...  
WO/2022/121090A1
The present invention provides a RISC-V general-purpose processor supporting high-throughput multi-precision multiplication. The processor comprises an independent multiplier data path. The multiplier data path enables a data path of a m...  
WO/2022/122947A1
The invention relates to a system for creating and managing draft patent applications, wherein the system (1) has a database (2) and a user interface (3), the draft patent applications have an architecture (5) which comprises at least cl...  
WO/2022/126116A1
To reduce power consumption, data bits or a portion of a data register that is not expected to toggle frequently can be grouped together, and be clock-gated independently from the rest of the data register. The grouping of the data bits ...  
WO/2022/121619A1
A computer system includes a memory having computer readable instructions and a processor for executing the computer readable instructions. The computer readable instructions control the processor to determine an active workflow initiate...  
WO/2022/119718A1
An integrated circuit comprising a MAC pipeline including a plurality of MACs connected in series to perform concatenated multiply and accumulate operations, wherein each MAC includes a multiplier circuit array, including a plurality of ...  
WO/2022/115913A1
This disclosure relates to generating and sharing random data. A data port receives intensity data indicative of a measured intensity of electromagnetic radiation radiated from a rotating star over an observation time period. A processor...  
WO/2022/120325A1
Methods, systems, and devices for queue configuration for host interface are described. An apparatus may include a host system including a first circular queue having a first entry that indicates a first command for a memory system and a...  
WO/2022/109917A1
A floating point computation device, a floating point computation method, a mobile platform, and a storage medium. The device comprises a pre-processor (10), a near-path arithmetic unit (20), and a far-path arithmetic unit (30). The pre-...  
WO/2022/115108A1
A computer processing system having at least one accelerator operably configured to compute modular multiplication with a modulus of special form and having a systolic carry-save architecture configured to implement Montgomery multiplica...  

Matches 1 - 50 out of 26,982