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WO/2023/176573A1 |
The present invention reduces the size of a division circuit. A coefficient holding unit (101) holds coefficients of a filter to be used for a convolutional operation. A multiplier data holding unit (102) holds multiplier data that is th...
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WO/2023/173821A1 |
Provided in the embodiments of the present application are a method for searching data in an integrated development environment, and a related device. The method comprises: determining M search entries according to a data source and N ke...
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WO/2023/177269A1 |
A neural network method and device are included. A neural network circuit includes a synaptic memory cell including a resistive memory element, which is disposed along an output line and which can have a first resistance value and a seco...
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WO/2023/174833A1 |
A method, computer program, and computer system are provided for floating-point conversion with denormalization in a single clock cycle. An input floating-point number corresponding to an input data type is received. An exponent value an...
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WO/2023/174898A1 |
The invention relates to Device for quantum generation of random numbers comprising a light source (100) with fixed polarization and a polarization splitting element (110) optically connected thereto, having a first output (111) correspo...
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WO/2023/177494A1 |
Embodiments herein relate to a neural network processor in a control loop, where the control loop sets an optimum supply voltage for the processor based on a measured error count or rate of the neural network. For example, if the measure...
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WO/2023/177318A1 |
The present disclosure relates to a neural network comprising at least one neural network layer and a particular kind of activation function connected to an output of the at least one neural network layer. The activation function is impl...
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WO/2023/177319A1 |
The present disclosure relates to a method of operating a neural network based on conditioned weights. The method comprises defining integer lower and upper threshold values for values of integer numbers comprised in data entities of inp...
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WO/2023/177317A1 |
The present disclosure relates to a method of operating a neural network with clipped input data. The method comprises operating a neural network comprising defining an integer lower and upper threshold values for values of integer numbe...
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WO/2023/170405A1 |
An electronic to optical encoder including: a first modulator; a second modulator; a first controller configured to receive a first digital electronic signal, and a second controller configured to receive a second digital electronic sign...
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WO/2023/147435A3 |
A mass indoor production of vegetation system maintains a train in a stationary position on a rail system inside an indoor enclosure during a growing period of vegetation. The train has a plurality of plant-pots interconnected by a plura...
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WO/2023/170406A1 |
There is provided a controller of an optical encoder, the controller configured to: receive an electronic signal, wherein a value of the electronic signal is based on a complex element; receive a feedback signal based on a phase drift as...
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WO/2023/170675A1 |
A method for implementing a logic circuit employing a combination of binary adders of different lengths having summation and carry outputs and AND gates, comprising the steps of replacing at least one known CMOS implemented binary adder ...
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WO/2023/170407A1 |
An optical apparatus includes a plurality of encoders, each encoder arranged to encode a first complex element onto an input stream of light; and a plurality of input ports arranged in a first array. Each input port is arranged to be sup...
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WO/2023/172998A1 |
An apparatus is provided for generating certified random numbers usable as data keys, for example postquantum cryptographic keys, wherein the apparatus is a self-contained hardware unit configured to operate at room temperature. The appa...
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WO/2023/165771A1 |
A processing device comprising a plurality of operand registers, wherein a first subset of the operand registers are configured to store state information for a plurality of bins, comprising a range of values and a bin count associated w...
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WO/2023/167981A1 |
Systems and methods for enhanced multiply-accumulate units for convolutional neural network processing. An example multiply-accumulate unit includes a multiplier, with the multiplier being configured to receive (1) an input value of a wi...
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WO/2023/165935A1 |
A random number generator comprising resistive random-access memory (RRAM) devices including: a first electrode; a second electrode; a third electrode located between the first and second electrode; at least one electrically insulating l...
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WO/2023/159925A1 |
Disclosed in the present invention are a frequency hopping communication apparatus and method, and a chip, a transmitter and a storage medium. The apparatus comprises: a pseudo-random sequence generation module, which is used for generat...
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WO/2023/160399A1 |
Provided are an accelerator, an acceleration method, and an electronic device. The accelerator comprises a computing unit, the computing unit comprising general arithmetic logic composed of basic arithmetic logic, and the general arithme...
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WO/2023/160868A1 |
The present invention relates to a method for computing a linear algebra operation of two operands or arrays comprising one or more narrow bit width elements with a digital circuit. The method uses the principle of binary segmentation to...
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WO/2023/162642A1 |
The present disclosure relates to a computer implemented method for converting an input computer program into an output computer program having a target global accuracy, comprising: - receiving a target internal accuracy for each mathema...
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WO/2023/161484A1 |
A device for hyperdimensional computing comprising: an array of m x n 1-bit processing units; each processing unit comprising a 1-bit logic unit and a memory unit; at least one input terminal for receiving an input hypervector; n 1-bit m...
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WO/2023/158858A1 |
An integrated circuit device includes broadcast data paths, a weighting-value memory, and multiply-accumulate (MAC) units. The MAC units are coupled in common to each of the broadcast data paths and coupled to receive respective weightin...
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WO/2023/158330A1 |
A computer-implemented method for recording, comprising: transcribing a content of a conference session using a conferencing system, determining a topic from the content of the conference session, determining a timestamp for the topic fr...
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WO/2023/155240A1 |
A random number generator, an electronic device, and an operating method. The random number generator (100) comprises an entropy source circuit (110), an entropy extraction circuit (120), and an output circuit (130). The entropy source c...
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WO/2023/158500A1 |
This document discloses techniques, apparatuses, and systems for secure pseudo-random number generator (PRNG) reseeding. Integrated circuits (ICs) may use PRNGs to enable cryptographic processes that can protect an IC or electronic devic...
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WO/2023/158426A1 |
The method includes obtaining, by at least one processor of at least one first network node within a communication network, at least one first key performance metrics (KPM) data type, from a plurality of KPM data types, the plurality of ...
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WO/2023/158193A1 |
The present disclosure suggests an electronic device for generating a homomorphic encrypted text and a method thereof, the electronic device including at least one processor, wherein the at least one processor may: identify n messages; e...
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WO/2023/150231A1 |
A system and method of quickly and efficiently generating a series of random numbers from a source of random numbers in a computing system. Steps includes: loading a data loop (a looped array of stored values with an index) with random d...
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WO/2023/147785A1 |
The present invention belongs to the technical field of Internet-of-Vehicles security. Disclosed are an Internet-of-Vehicles communication security authentication method, system and device based on a national cryptographic algorithm. The...
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WO/2023/149935A1 |
Embodiments of the present disclosure include a multiply-accumulator (MAC) array circuit comprising an activation cache and a plurality of multiply-accumulator (MA) groups. The activation cache comprises cache lines configured to store s...
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WO/2023/150014A1 |
Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU or CPU. The apparatus may configure a BVH structure including a plurality of nodes, the BVH structure being associated wit...
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WO/2023/147718A1 |
The present disclosure relates to the technical field of computers, and particularly to the field of deep learning and the field of distributed computing. Provided in the present disclosure are a content initialization method and apparat...
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WO/2023/149662A1 |
Disclosed in one embodiment is a data processing method comprising the steps of: acquiring at least one weight, corresponding to at least one input value with respect to at least one from among a plurality of output channels correspondin...
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WO/2023/150027A1 |
Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may configure a BVH structure including a plurality of nodes each including one or more primitives, and eac...
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WO/2023/147770A1 |
A floating point number operation method, applied to multiplication operation of a first floating point number and a second floating point number. The first floating point number comprises a first symbol, a first exponent, and a first ma...
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WO/2023/148411A1 |
Disclosed is a method for calibrating graphs, by means of artificial intelligence, which coordinates the abscissas and ordinates of two or more graphs to compare them. The method comprises: recognising the units of the abscissa and ordin...
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WO/2023/148580A1 |
Provided is a method for operating a semiconductor device that performs data writing and correction processing. The present invention is a method for operating a semiconductor device that includes a control circuit, a first circuit, a se...
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WO/2023/141936A1 |
Disclosed are apparatuses, systems, and techniques to perform and facilitate fast and efficient modular computational operations, such as Montgomery multiplication with reduced interdependencies, using optimized processing resources.
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WO/2023/144039A1 |
A computer-implemented method for enabling elliptic curve arithmetic to be performed using blockchain transactions. A first script of a first blockchain transaction is generated, comprising a modular inversion script configured to obtain...
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WO/2023/146563A1 |
A method includes causing an evaluation profile user interface to be output by a display. The evaluation profile user interface includes a key performance indicator (KPI) input field to receive a user input identifying one or more select...
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WO/2023/147025A1 |
Methods, systems, and computer program products are provided for energy efficient generation of artificial noise to prevent side-channel attacks. An example method includes storing at least one secret value including secret value bits. A...
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WO/2023/144577A1 |
A hybrid time-shared iterative multiply-accumulate circuit comprises a product storage circuit, a multiply circuit operable to receive a first input value, receive a second input value, produce a product of the first input value and the ...
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WO/2023/141933A1 |
Disclosed are apparatuses, systems, and techniques to perform and facilitate fast and efficient modular computational operations, such as modular division and modular inversion, using shared platforms, including hardware accelerator engi...
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WO/2023/137696A1 |
Disclosed in the present application are a logical operation storage unit, a storage array and a logical operation memory. The logical operation storage unit comprises a logical operation control circuit, a result storage circuit, a WBL ...
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WO/2023/134130A1 |
Disclosed in the present application are a Galois field multiplier and an erasure coding and decoding system. The Galois field multiplier comprises a plurality of basic operation units connected in series and a plurality of cyclic proces...
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WO/2023/134507A1 |
A stochastic calculation method, a circuit, a chip and a device, belonging to the technical field of circuits. A stochastic calculation circuit comprises: a control circuit, which is used to input a control parameter into a pulse input c...
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WO/2023/134905A1 |
Techniques for determining an inner product between a non-binarized first array and a second array using a binary logic unit (201) are provided. The first array is decomposed into a plurality of binarized arrays by determining a respecti...
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WO/2023/131432A1 |
The invention relates to a device for identifying at least one synchronicity range (SB) of two time series of random numbers, a first time series ((Ak)) and a second time series ((Bk)). The device comprises - a first non-deterministic ra...
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