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Matches 1 - 50 out of 661,674

Document Document Title
WO/2022/127361A1
The present disclosure relates to the technical field of memories. Provided is a reading circuit for a differential OTP memory. The differential OTP memory comprises a first storage unit and a second storage unit, which are in a differen...  
WO/2022/133166A1
One example includes an integrated circuit (IC) (100). The IC (100) includes non-volatile memory (106) and logic (108). The logic (108) is configured to receive repair code associated with a memory instance and assign a compression param...  
WO/2022/127426A1
A magnetic memory and a performance adjustment method therefor. The method comprises: receiving a performance adjustment instruction (S101); acquiring a parallel-state reversal voltage and an anti-parallel-state reversal voltage of a mag...  
WO/2022/131632A1
A content reproduction device according to an embodiment of the present invention comprises: a mounting unit to which a content storage medium is detachably attached; and a control unit for performing authentication by recognizing identi...  
WO/2022/126835A1
A display panel and a display device. The display panel comprises a gate drive circuit (10), multiple impedance adjustment circuits (20), and a control module (30); the gate drive circuit (10) comprises multiple cascaded first shift regi...  
WO/2022/132538A1
Technologies for signal skew correction in integrated circuit memory devices are described. An integrated circuit memory device includes a first interface to receive command/address (CA) signals and a clock signal, a data interface, and ...  
WO/2022/126418A1
A memory device (900) includes a memory array, a bitline and a buffer (910_0-910_M). The memory array can include a plurality of memory strings. The memory strings can be divided into a first memory string group (950_0-950_M) and a secon...  
WO/2022/132539A1
Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, an integrated circuit (IC) device includes a first stack of IC dies connected to a plurality of second stacks of IC dies. The fir...  
WO/2022/131089A1
A memory cell array unit according to one embodiment of the present disclosure comprises an internal power supply unit, a memory cell array, and a microcontroller. The memory cell array includes a plurality of writable non-volatile memor...  
WO/2022/126595A1
Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, identifying a block family comprising a plurality of blocks of the memory devic...  
WO/2022/131633A1
A content playback method of a content playback system according to an embodiment of the present invention comprises the steps, carried out by a content playback apparatus, of: recognizing identification information of content storage me...  
WO/2022/128646A1
A memory device, and a method of forming the same, includes a bottom electrode above an electrically conductive structure, the electrically conductive structure is embedded in an interconnect dielectric material. A magnetic tunnel juncti...  
WO/2022/132993A1
In a described example, an integrated circuit (IC) (100) includes a repairable memory system (104, 106). A repair controller (102) is coupled to the repairable memory system (104, 106). The repair controller (102) includes compression lo...  
WO/2022/127930A1
The present application provides a storage unit and a storage array. The storage unit comprises a first storage subunit formed of a volatile storage medium and a first word line and a second storage subunit formed of a persistent storage...  
WO/2022/132475A1
Systems, apparatuses, and methods related to memory activation timing management are described herein. In an examples, memory activation timing management can include receiving a first command associated with a set of memory cells, activ...  
WO/2022/127086A1
A data processing method, system, and device for a magnetic storage medium, relating to the technical field of chips. The method comprises: obtaining the magnetic induction intensity of a magnetic storage medium at a set position; keepin...  
WO/2022/129028A1
The invention relates to an electric circuit assembly comprising a ferroelectric field effect transistor, an electric energy source (2), and a resistive element (3) having a minimum electric resistance of 100 kOhm, the resistive element ...  
WO/2022/127428A1
A magnetic random access memory and a read circuit thereof. The read circuit comprises a sense amplifier, a reference array, and a read array. The reference array comprises a first reference resistor, a second reference resistor, a first...  
WO/2022/127381A1
A device which comprises an array of resistive processing unit (RPU) cells, first control lines extending in a first direction across the array of RPU cells, and second control lines extending in a second direction across the array of RP...  
WO/2022/127446A1
An analog memory structure, and methods of writing to such a structure are provided. The analog memory structure includes a volatile memory element in series with a non-volatile memory element. The analog memory structure may change resi...  
WO/2022/127027A1
Provided by the present application are a semiconductor structure, memory cell, and memory array; an nT magnetoresistive random-access memory (nT-MRAM) can be implemented by means of a relatively simple structure; the transistors to whic...  
WO/2022/130554A1
A semiconductor memory device of an embodiment includes a substrate, a plurality of first conductor layers, a pillar, and a second conductor layer. The plurality of first conductor layers are provided above the substrate, and are separat...  
WO/2022/129306A1
The present invention relates to a device (12) for modifying at least the direction of magnetisation of a magnetic layer (10), the modifying device (12) comprising: - a ferroelectric layer (14) having a ferroelectric polarisation, placed...  
WO/2022/133479A1
A request for an audio arrangement having one or more target audio arrangement characteristics is received. One or more target audio attributes are identified based on the one or more target audio arrangement characteristics. First audio...  
WO/2022/131202A1
A fluorine-containing ether compound represented by the following formula. R1-[B]-[A]-CH2-R2-CH2-[C]-[D]-R3 (R2 is a perfluorinated polyether chain; [A] is formula (2-1); [B] is formula (2-2); [C] is formula (3-1); [D] is formula (3-2); ...  
WO/2022/131211A1
An aluminum alloy substrate for a magnetic disk according to the present invention comprises an aluminum alloy containing 1.80 mass% or less of Fe, 0.70 mass% or less of Mn, 2.50 mass% or less of Ni, 2.50 mass% or less of Si, 1.00 mass% ...  
WO/2022/126635A1
A read/write controller, a memory and an electronic device, which are used for improving the write flexibility of the memory. The read/write controller comprises a clock generation circuit, a multi-state write circuit, a row decoding cir...  
WO/2022/132265A1
An integrated circuit (IC) package, comprising a substrate that comprises a bridge die embedded within a dielectric. A first die comprising a first input/output (I/O) transmitter and a second die comprising a second I/O receiver and elec...  
WO/2022/132476A1
Systems, apparatuses, and methods related to memory activation timing management are described herein. In an examples, memory activation timing management can include receiving a first command associated with a set of memory cells, activ...  
WO/2022/127029A1
The present application provides a semiconductor structure and a storage circuit. A storage structure of an MRAM is implemented on the basis of a DRAM manufacturing platform, such that it is simpler and more convenient to manufacture a D...  
WO/2022/127161A1
A comparison circuit and a memory chip. The comparison circuit comprises: a comparison module, wherein a first input end thereof is connected to a voltage to be measured, and a second input end thereof is connected to a reference voltage...  
WO/2022/131210A1
This aluminum alloy disc blank for a magnetic disc is characterized by being formed from an aluminum alloy containing 3.40-3.90 mass% of Mg, the remainder being Al and unavoidable impurities, and by having a conductivity of at least 36.0...  
WO/2022/123366A1
A semiconductor structure (100) includes a heater (116) surrounded by a dielectric layer (114), a projection liner (124) on top of the heater (116); a phase change material layer (126) above the projection liner (124), and a top electrod...  
WO/2022/123107A1
A method for producing binaural immersive audio for audio-visual content. The method includes: receiving audio-visual content including video and audio; identifying audio-producing object(s) represented in given frame of video; analysing...  
WO/2022/122391A1
An apparatus according to one approach includes an array of skew detection transducers. An array of write transducers is spaced from the array of skew detection transducers along an intended direction of tape travel thereacross. An array...  
WO/2022/124632A1
The present invention relates to a semiconductor memory device comprising a semiconductor memory module and a semiconductor memory control unit, wherein the semiconductor memory module includes a power management unit. The power manageme...  
WO/2022/121603A1
A device includes a non-volatile analog resistive memory cell. The non-volatile analog resistive memory device includes a resistive memory device and a select transistor. The resistive memory device includes a first terminal and a second...  
WO/2022/122283A1
The disclosed spin-orbit torque (SOT)-MRAM (100) comprises a first magnetic tunneling junction (125A, 130A, 135A) having a first diameter and a first critical voltage, a second MT] (125B, 130B, 135B) having a second diameter and a second...  
WO/2022/125309A1
The present disclosure includes storage circuits, such latches. In one embodiment, a circuit includes a plurality of latches, each latch including a first N-type transistor formed in a first P-type material, a first P-type transistor for...  
WO/2022/123283A1
The present disclosure describes a memory device comprising memory cells at cross points of access lines of a memory array, and a two-transistor driver comprising a P-type transistor and a N-type transistor connected to the P-type transi...  
WO/2022/126065A1
Methods, systems, and devices for voltage equalization for pillars of a memory array are described. In some examples, a memory array may be configured with conductive pillars that are each coupled with a respective set of memory cells, a...  
WO/2022/126072A1
Methods, systems, and devices for decoding for a memory device are described. A decoder may include a first vertical n-type transistor and a second vertical n-type transistor that extends in a third direction relative to a die of a memor...  
WO/2022/125830A1
A memory device includes a memory array of memory cells and control logic, operatively coupled with the memory array. The control logic is to perform operations, which include causing the memory cells to be programmed with an initial vol...  
WO/2022/124976A1
This document describes a spatial light modulator that comprises a pixel array having a plurality of pixels whereby each pixel in this array is communicatively coupled to a digital pixel circuit which are in turn all coupled to a bit-pla...  
WO/2022/126073A1
Methods, systems, and devices for decoding for a memory device are described. A decoder of a memory device may include transistors in a first layer between a memory array and a second layer that includes one or more components associated...  
WO/2022/123284A1
The present disclosure provides a memory apparatus and a method for accessing a 3D vertical memory array. The 3D vertical memory array comprises word lines organized in planes separated from each other by insulating material, bit lines p...  
WO/2022/122469A1
An apparatus comprising a magnetic tunnel junction (MTJ), a diffusion barrier, wherein the MTJ is located on the diffusion barrier and a bottom contact that includes a magnetic field generating component, wherein the diffusion barrier is...  
WO/2022/121467A1
A non-volatile memory and an operating method for the non-volatile memory. The non-volatile memory comprises a plurality of memory units and unselected word lines connected to the plurality of memory units. The method comprises: applying...  
WO/2022/125172A1
An exemplary memory bit cell circuit, including a bit line coupled to an SRAM bit cell circuit and an NVM bit cell circuit, with reduced area and reduced power consumption, included in a memory bit cell array circuit, is disclosed. The S...  
WO/2022/120910A1
A ferroelectric memory and a storage data reading method thereof. The ferroelectric memory comprises a plurality of word lines and a plurality of plate lines extending in a first direction, a plurality of bit lines extending in a second ...  

Matches 1 - 50 out of 661,674