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Patent Searching and Data


Matches 451 - 500 out of 661,464

Document Document Title
WO/2022/010895A1
Computer game sound effects (SFX) (e.g., 700) are provided (304) to customer computers (204) in a container (202) that includes not only the audio file (such as a.wav file) of the SFX but also the information underlying the SFX (e.g., 40...  
WO/2022/010561A1
A video indexing system identifies groups of frames within a video frame sequence captured by a static camera during a same scene. Context metadata is generated for each frame in each group based on an analysis of fewer than all frames i...  
WO/2022/010577A1
The present disclosure generally relates to spin-orbital torque (SOT) differential reader designs. The SOT differential reader is a multi-terminal device that comprises a first shield, a first spin hall layer, a first free layer, a gap l...  
WO/2022/010584A1
The present disclosure generally relates to spin-orbital torque (SOT) differential reader designs. The SOT differential reader is a multi-terminal device comprising a first seed layer, a first spin hall effect (SHE) layer, a first interl...  
WO/2022/010691A1
Methods, systems, and devices for accessing a multi-level memory cell are described. The memory device may perform a read operation that includes pre-read portion and a read portion to access the multi-level memory cell. During the pre-r...  
WO/2022/010016A1
The present invention proposes a processing-in-memory (PIM) internal device and a method for including a read-write-operation instruction corresponding to a new instruction in an instruction set and processing the read-write-operation in...  
WO/2022/006733A1
Embodiments of apparatus and method for matrix multiplication using processing-in-memory (PIM) are disclosed. In an example, an apparatus for matrix multiplication includes an array of PIM blocks in rows and columns, a controller, and an...  
WO/2022/010754A1
A system and method for protecting against a voltage glitch are provided. Generally, the system includes a reset-detector coupled to a supply voltage (VCC) and to a power-on-reset (POR) block, and a glitch-detector coupled to VCC and the...  
WO/2022/007156A1
Provided are a voltage control method and circuit for an anti-fuse memory array. The method comprises: acquiring a storage data address, dividing the storage data address into a plurality of bit segments, decoding each bit segment, and t...  
WO/2022/009711A1
[Problem] To provide a method for manufacturing: a tape cartridge provided with a reel hub; a tape reel; and a reel hub. The method can ensure desired molding quality in single molding. [Solution] This tape cartridge according to one emb...  
WO/2022/009618A1
This variable-resistance-type non-volatile storage device comprises a variable resistance element (RSE) capable of reversibly changing the state of resistance between a high resistance state and a low resistance state, and a current supp...  
WO/2022/010692A1
Methods, systems, and devices for reading a multi-level memory cell are described. The memory cell may be configured to store three or more logic states. The memory device may apply a first read voltage to a memory cell to determine a lo...  
WO/2022/010533A1
Numerous embodiments of analog neural memory arrays are disclosed. Certain embodiments comprise an adaptive bias decoder for providing additional bias to array input lines to compensate for instances where ground floats above 0V. This is...  
WO/2022/010194A1
Disclosed is a three-dimensional flash memory having an improved memory operation. The three-dimensional flash memory comprises: at least one channel layer extending in the vertical direction on a substrate; multiple word lines extending...  
WO/2022/010909A1
An electronic device may include one or more output buffers each including a pair of final p-channel metal oxide semiconductor (PMOS) and n-channel metal oxide semiconductor (NMOS) transistors, a first pre-buffer to drive the PMOS transi...  
WO/2022/006709A1
The present invention provides a method and system for improving the performance of a gate tube device, a device, and a medium. The method comprises: determining an operating voltage and a limiting current of a gate tube device during a ...  
WO/2022/010672A1
Methods, systems, and devices for monitoring and reporting a status of a memory device are described. A memory device may include monitoring circuitry that may be configured to monitor health and wear information for the memory device. A...  
WO/2022/011309A1
A memory device includes a memory array comprising a plurality of planes and a plurality of independent plane driver circuits. The memory device further includes control logic to track a status of the plurality of independent plane drive...  
WO/2022/005655A1
Aspects of the subject disclosure may include, for example, a method that includes obtaining, by a processing system including a processor, video frames over a network; the processing system uses a machine learning algorithm to identify ...  
WO/2022/005944A1
Systems, apparatuses, and methods related to a neuron using posits are described. An example apparatus may include a memory array including a plurality of memory cells configured to store data. The data can include a plurality of bit str...  
WO/2022/001163A1
A sense amplifier, a storage device, and a reading and writing method. The sense amplifier comprises: a first switch unit, a second switch unit, and an amplifying latch module, wherein a first port of the amplifying latch module is elect...  
WO/2022/000927A1
A semiconductor apparatus. The semiconductor apparatus comprises a storage chip (100) and a temperature measurement module (110). The temperature measurement module (110) is used for measuring the temperature of the storage chip (100). W...  
WO/2022/005535A1
A data storage system includes a chassis housing multiple data storage devices, such as hard disk drives, a compartment housing cooling fans, and an air plenum positioned between the fans and the storage devices. A multibody chambered ac...  
WO/2022/003957A1
An accumulation apparatus (200) according to an embodiment of the present invention comprises a substrate (Sb) and a laminate structure (LS) that is laminated on the substrate. The laminate structure is provided with a first element grou...  
WO/2022/004826A1
Provided are: a magnetic disk substrate characterized by comprising an aluminum alloy containing one or more of 8.5 mass% or less of Fe, 2.5 mass% or less of Mn, 6.5 mass% or less of Ni, and 4.5 mass% or less of Mg, the remainder being A...  
WO/2022/000150A1
The present application relates to the field of memories. Disclosed are a stacked memory and a storage system, used for preventing power integrity and signal integrity degradation of the stacked memory while not increasing the number of ...  
WO/2022/000937A1
A double-pulse excitation method for ultrafast and super-resolution all-optical magnetic recording, comprising: a first excitation pulse and a second regulation pulse sequentially enter an optical magnetic recording medium, so that an al...  
WO/2022/005537A1
A storage device may detect errors during data transfer. Upon detection of one or more data transfer errors, for example, the storage device can begin to scan pages within a plurality of memory devices for uncorrectable error correction ...  
WO/2022/005517A1
Dual sense bin balancing (DSBB) to adjust a read level between memory states of an array of NAND flash memory cells implemented in a logic circuit of a NAND flash die or in a storage device controller. Reading a randomized data pattern s...  
WO/2022/001579A1
Disclosed in the present application are an audio processing method and apparatus, a device, and a storage medium. The method comprises: presenting a target audio and target text information corresponding to the target audio; using a pos...  
WO/2022/000926A1
The present invention provides a semiconductor device, comprising a memory chip and a temperature measurement unit. The temperature measurement unit is used for measuring the temperature of the memory chip; and the temperature measuremen...  
WO/2022/005639A1
The present disclosure generally relates to spin-orbital torque (SOT) differential reader designs. The SOT differential reader is a multi-terminal device that comprises a first shield, a first spin hall effect layer, a first free layer, ...  
WO/2022/000928A1
A semiconductor device, comprising a memory chip (100) and a temperature measurement module (110). The temperature measurement module (110) is used for measuring the temperature of the memory chip (100). The temperature measurement modul...  
WO/2022/005820A1
Methods, systems, and devices for system and method for reading and writing memory management data through a non-volatile cell based register are described. A memory device may include a set of latch units addressable via a set of row li...  
WO/2022/005534A1
A method and device for programming a non-volatile memory cell, where the non-volatile memory cell includes a first gate. The non-volatile memory cell is programmed to an initial program state that corresponds to meeting or exceeding a t...  
WO/2022/000486A1
A programming method for a three-dimensional ferroelectric memory device is disclosed. The programming method includes applying a first voltage on a selected word line of a target memory cell. The target memory cell has a first logic sta...  
WO/2022/000929A1
A method for improving a data retention capability of a nor flash memory, a system, a storage medium, and a terminal. A Vt value of data 0 is regularly detected and recovered, when it is detected that the Vt value of the data 0 is less t...  
WO/2022/000930A1
Disclosed in the present invention is a withstand voltage limited switching circuit from a negative high voltage to a power supply. The drain of a first PMOS transistor is connected to a power supply voltage, the gate of the first PMOS t...  
WO/2021/262137A1
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for generating videos. In one aspect, a method comprises: receiving: (i) an input video comprising a sequence of video frames, and (ii) da...  
WO/2021/261157A1
[Problem] To provide a semiconductor storage device with which error bits that occur because of line failures can be masked when writing and corrected when reading out. [Solution] A semiconductor storage device according to the present d...  
WO/2021/262241A1
A refractory metal-containing etch stop layer, a ruthenium etch stop layer, and a conductive material layer can be sequentially formed over an electrode layer and a selector material layer. A sequence of anisotropic etch processes can be...  
WO/2021/258305A1
A ferroelectric memory. The ferroelectric memory comprises at least one storage unit, and each storage unit comprises a first electrode (1), a second electrode (2), a third electrode (3), a ferroelectric layer (4), and a first semiconduc...  
WO/2021/262737A1
The disclosed computer-implemented method includes analyzing, by a speech detection system, a media file to detect lip movement of a speaker who is visually rendered in media content of the media file. The method additionally includes id...  
WO/2021/259194A1
The present application provides a storage device, comprising a hard disk backplane, a first cascade board and a hard disk array, the hard disk array comprising a plurality of hard disks; the hard disk array is located at a first side of...  
WO/2021/258814A1
Embodiments of the present invention provide a video synthesis method and apparatus, an electronic device, and a storage medium. The video synthesis method comprises: obtaining user-given materials, video synthesis strategy selection inf...  
WO/2021/262257A1
Disclosed herein are embodiments of sliders in which the length of the slider is less than or equal to its width. Also disclosed are data storage devices (e.g., hard disk drives) comprising such sliders. The sliders may include one or mo...  
WO/2021/262240A1
A cross-point memory device includes first conductive line structures laterally extending along a first horizontal direction, an array of memory pillar structures overlying top surfaces of the first conductive line structures, such that ...  
WO/2020/226740A9
A circuit for multiplying a number N of first operands each by a corresponding second operand, and for adding the products of the multiplications, with N ≥ 2; the circuit comprising: N input conductors; N programmable conductance circu...  
WO/2021/259611A1
The present invention concerns a method of generating a media file, the method comprising: generating a first track of media data samples; generating at least one annotated region, the annotated region being associated with a geometry of...  
WO/2021/258888A1
A shift register, a gate driving circuit, and a display panel. In the shift register, a forward input module (1) is used for providing a signal of a forward power supply voltage end (VNN) to a first node (PU) by means of a first transist...  

Matches 451 - 500 out of 661,464