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Patent Searching and Data


Matches 451 - 500 out of 863,225

Document Document Title
WO/2020/240857A1
An operating device 3 is provided with: a rotary body (51) that is mounted on a turntable (RP1) and that is rotated together with the turntable; virtual operation areas (VA), which are virtual areas that are set on the rotary body and th...  
WO/2020/240225A1
The present disclosure relates to a memory architecture comprising a plurality of subarrays of memory cells, a plurality of sense amplifiers connected to the subarrays; a plurality of original pads; at least one redundant pad; multiple d...  
WO/2020/242746A1
Techniques for performing in-memory matrix multiplication, taking into account temperature variations in the memory, are disclosed. In one example, the matrix multiplication memory uses ohmic multiplication and current summing to perform...  
WO/2020/243102A1
In described examples, a processor system includes a processor core that generates memory write requests, a cache memory (304), and a memory pipeline of the cache memory (304). The memory pipeline has a holding buffer (306), an anchor st...  
WO/2020/240612A1
A jog dial unit (1), which is a rotary operation device, comprises: a jog dial (2) that is a rotary operation unit; a base unit (3) that rotatably supports a rotary shaft unit (21) of the rotary operation unit; a load application unit (4...  
WO/2020/237637A1
Disclosed in the present application is a solid state drive data reading method, comprising: a controller receives a read request sent by a host and comprising location indication information of requested data; determine, according to a ...  
WO/2020/240529A2
The present disclosure relates to data storage device, more particularly to different types of devices which facilitates in capturing, storing, listing, editing, deleting & displaying and/or playing different types of user data, viz. tex...  
WO/2020/240236A1
The present disclosure relates to apparatuses and methods for memory management and more particularly to a memory device structured with internal analogic measurement mode features. The memory is provided with means for detecting a corre...  
WO/2020/240230A1
The present disclosure relates to an apparatuses and methods for memory management and more particularly to voltage or current detector for a non- volatile memory component that is coupled to a host device or to a System- on-Chip. The me...  
WO/2020/243075A1
A system writes input data to a storage device as machine-written polynucleotides; and reads machine written polynucleotides from the storage device as output data. The storage device includes a flow cell including a plurality of storage...  
WO/2020/242693A1
Methods, systems, and devices for reconfigurable channel interfaces for memory devices are described. A memory device may be split into multiple logical channels, where each logical channel is associated with a memory array and a command...  
WO/2020/243417A1
A method of controlling the forming voltage of a dielectric film in a resistive random access memory (ReRAM) device. The method includes depositing a dielectric film contains intrinsic defects on a substrate, forming a plasma-excited tre...  
WO/2020/240223A1
The present disclosure relates to an apparatus comprising: - a host device or a System-on-Chip: - a memory component having an independent structure and including at least an array of memory cells organized in sub-arrays with associated ...  
WO/2020/240234A1
The present disclosure relates to a non-volatile memory device including at least an array of memory cells and with associated decoding and sensing circuitry and a memory controller, and a method for checking the erasing phase of the non...  
WO/2020/240242A1
The present disclosure relates to a non-volatile memory device and to a method for generating overvoltage values in such a memory device structured in a plurality of sub-arrays and including: - at least a decoding and sensing circuitry a...  
WO/2020/239454A1
The invention relates to an analogue circuit arrangement (1) for variably setting a voltage Uout within defined voltage limits, comprising a non-inverting adder (10) having a positive input (11), wherein a voltage divider (20) comprising...  
WO/2020/243076A1
Devices, systems, and methods for non-volatile storage include a well activation device operable to modify one or more wells from a plurality of wells of a flow cell to provide a set of readable wells. Readable wells are configured to al...  
WO/2020/240231A1
The present disclosure relates to a method for improving the safety of the reading phase of a non-volatile memory device including at least an array of memory cells and with associated decoding and sensing circuitry and a memory controll...  
WO/2020/237456A1
A sample and hold scheme for temperature measurements for non-volatile memory can enable significant reduction in temperature readout latency. In one example thermometer circuits are enabled at a refresh rate to cause the temperature to ...  
WO/2020/240224A1
The present disclosure relates to integrated memory device including: - an array of memory cells with decoding and sensing circuitry; - a memory controller; - read and write circuitry associated to the sensing circuitry; - logic circuit ...  
WO/2020/240856A1
A detection device (2) is provided with: a rotator (41) that is placed on a turntable (RP1) of a record player (RP) and that is rotated together with the turntable; a rotation detection unit (RD) that detects the rotation of the rotator;...  
WO/2020/237682A1
Disclosed in embodiments of the present application are a content-addressable storage apparatus and method, and a related device, wherein the content-addressable storage apparatus may comprise: a memory used for storing data to be matche...  
WO/2020/240228A1
The present disclosure relates to a Flash memory component (1) having a structurally independent structure and coupled to a System- on-Chip through a plurality of interconnection pads, comprising: • - a memory array including a plurali...  
WO/2020/242793A1
Multilevel command and address (CA) signals are used to provide commands and memory addresses from a controller to a memory system. Using multilevel signals CA signals may allow for using fewer signals compared to binary signals to repre...  
WO/2020/243179A1
Systems, apparatuses, and methods for dynamically generating a memory bitcell supply voltage rail from a logic supply voltage rail are disclosed. A circuit includes at least one or more comparators, control logic, and power stage circuit...  
WO/2020/240239A1
The present disclosure relates to a memory component for a System-on-Chip (SoC) structure including at least a memory array and at least a logic portion for interacting with the memory array and with the SoC structure wherein the memory ...  
WO/2020/240232A1
The present disclosure relates to a memory device with an improved sensing structure and including: - a memory array comprising a plurality of sub-arrays of memory cells and structured in memory blocks; - sense amplifiers coupled to the ...  
WO/2020/242213A1
The present invention provides a magnetic memory device and an operation method therefor, the present invention comprising: a magnetic layer comprising Fe3GeTe2; end electrodes spaced apart in a first direction on the magnetic layer; a v...  
WO/2020/236223A1
A data storage system may include multiple data storage devices, such as solid-state drives, an enclosure housing the devices, and a thermal bridge positioned in a gap between and in contact with each of the enclosure and a device, where...  
WO/2020/233666A1
Provided by the present invention are a window, a medium, and an optical storage method; the window comprises a polymer solid film layer; light absorption controllable interchanging molecules are comprised in the material of the window, ...  
WO/2020/236222A1
A data storage device is disclosed comprising a first disk comprising a first disk surface, a second disk comprising a second disk surface, an elevator actuator configured to actuate a head along an axial dimension relative to the first ...  
WO/2020/236171A1
Methods, systems, and media for object grouping and manipulation in immersive environments are provided. The method comprises: displaying a plurality of video objects in an immersive environment; detecting, via a first input, that a firs...  
WO/2020/237211A1
A read path for a memory is provided that includes an integrated sense mixing and redundancy shift stage coupled between a sense amplifier and a data latch. The data latch is integrated with a level shifter. A first transistor is coupled...  
WO/2020/233265A1
A gate drive circuit (10) and a driving method therefor, a display panel (100), and a display device (1000). The gate drive circuit (10) is used to drive a pixel circuit, and comprises a plurality of gate driver on array (GOA) units (11)...  
WO/2020/236611A1
A process forms thin-film storage transistors (e.g., HNOR devices) with improved channel regions by conformally depositing a thin channel layer in a cavity bordering a source region and a drain region, such that a portion of the channel ...  
WO/2020/233673A1
A storage device and a method for writing data. The storage device can be applied to a neural network. The storage device comprises a memristor unit, a current limiting circuit, and a writing circuit. The memristor unit is of a one trans...  
WO/2020/233162A1
The present invention relates to a multi-machine wireless synchronous track-splitting recording machine, which comprises a power source module, an audio input module, an A/D conversion module, an SoC core module (including Bluetooth and ...  
WO/2020/237026A1
A non-volatile memory device includes a plurality of memory cells arranged in a matrix, a plurality of word lines extended in a row direction, and a plurality of bit lines extended in a column direction. Each of the memory cells is coupl...  
WO/2020/234397A1
A fire resistant cabinet (1) has a housing (15) delimiting an interior space (14) for accommodating a sanitizer container (16) holding a flammable liquid. The wall (4) of the housing (15) comprises at least one exterior shell part (3) ma...  
WO/2020/236166A1
An example system includes a portable storage device carrier to receive a plurality of drive trays. Each of the plurality of drive trays receives a storage device. The example system further includes a dock assembly to receive the portab...  
WO/2020/233175A1
Provided are a hard disk format conversion method, apparatus, and storage device, belonging to the technical field of storage. By means of converting the storage format of a storage unit from SMR to PMR, since in PMR, IOPS is higher than...  
WO/2020/236379A1
A system comprises an integrated circuit die substrate; volatile memory electrically coupled to the integrated circuit die substrate; a first integrated circuit die element electrically coupled to the integrated circuit die substrate, th...  
WO/2020/234689A1
A novel semiconductor device is provided. The semiconductor device includes: a first control circuit having a first transistor using a silicon substrate for a channel; a second control circuit provided on the first control circuit and ha...  
WO/2020/232574A1
Embodiments of three-dimensional (3D) memory devices with a 3D NAND memory array having a plurality of pages and an on-die data buffer coupled to the memory array on a same chip and configured to buffer a plurality of batches of program ...  
WO/2020/233161A1
The present utility model relates to a portable digital recorder, which is characterized in comprising a power module, an audio input module, an A/D conversion module, a SoC core module, a button module, an LED indicator module, and a di...  
WO/2020/232571A1
Embodiments of three-dimensional (3D) memory devices with a 3D NAND memory array having a plurality of pages, an on-die cache coupled to the memory array on a same chip and configured to cache a plurality of batches of program data betwe...  
WO/2020/233665A1
The present invention provides an optical system and an optical method. The optical system comprises a light source and a medium. The light source includes a first light and a second light, the first light being hollow light and the seco...  
WO/2020/205031A3
A magnetic Josephson junction (MJJ) device having (100) a ferrimagnetic/ferromagnetic (FIM/FM) exchange-biased bilayer (116, 118) used as the magnetic hard layer improves switching performance by effectively sharpening the hysteresis cur...  
WO/2020/232658A1
A method of programming a NAND flash memory device includes: a programming voltage generation circuit applying an initial programming voltage pulse to a predetermined page of NAND flash memory; a controller verifying a plurality of verif...  
WO/2020/236591A1
A system may include a first device and a second device. The second device may be configured to execute an application and validate that the application is able to cause the second device to (i) communicate with the first device and (ii)...  

Matches 451 - 500 out of 863,225