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Matches 501 - 550 out of 863,212

Document Document Title
WO/2020/230357A1
The present invention relates to: an information recording medium wherein at least one information layer among three or more information layers comprises a first dielectric film, a recording film and a second dielectric film sequentially...  
WO/2020/232007A1
Techniques for estimating raw bit error rate of data stored in a group of memory cells are described. Encoded data is read from a group of memory cells. A first population value is obtained based on a first number of memory cells in the ...  
WO/2020/231608A1
A memory device includes a memory array, a plurality of voltage generation systems, and a controller. The memory array includes a plurality of planes. Each voltage generation system of the plurality of voltage generation systems is elect...  
WO/2020/231472A1
A non-volatile storage system includes a mechanism to compensate for over programming during the programming process. That is, after the programming process starts for a set of data and target memory cells, and prior to the programming p...  
WO/2020/231247A1
The invention relates to a structure for aluminum houses, consisting of a set of parts which, when used in different combinations and according to specifications, form the structure of a house without requiring the use of heavy construct...  
WO/2020/229620A1
The present disclosure relates to a shiftable memory comprising: a plurality of memory cells arranged in rows and columns, wherein the memory cells of the rows are interconnected, thereby forming chains of memory cells; at least one firs...  
WO/2020/227296A1
The disclosure provides thermally reversible and reorganizable polymers for volume Bragg gratings. These polymers can be used in any volume Bragg gratings materials, but they are particularly useful in two-stage polymer materials where a...  
WO/2020/224422A1
A shift register, comprising an input sub-circuit (100). The input sub-circuit (100) is coupled to a signal input terminal (Iput). The input sub-circuit (100) comprises a first input control unit (101) and a boosting unit (102). The firs...  
WO/2020/226866A1
Methods and apparatus for NAND flash memory are disclosed. In an embodiment, a method is provided for programming a NAND flash memory. The method includes precharging selected bit lines of selected memory cells with a bias voltage level ...  
WO/2020/226283A1
A memory device for logic-in-memory may comprise, according to an example embodiment of the present invention: a cell array comprising a plurality of ternary memory cells; a row decoder for selecting at least one ternary memory cell from...  
WO/2020/226740A1
A circuit for multiplying a number N of first operands each by a corresponding second operand, and for adding the products of the multiplications, with N ≥ 2; the circuit comprising: N input conductors; N programmable conductance circu...  
WO/2020/226130A1
The present invention addresses the problem of providing a Ni-based sputtering target having little bias in magnetic distribution within the target, and a magnetic recording medium having a seed layer formed using the Ni-based sputtering...  
WO/2020/227294A1
A memory subsystem to schedule the transfer of data from a host system for write commands to reduce the amount and time of data being buffered in the memory subsystem. For example, after receiving a plurality of streams of write commands...  
WO/2020/226746A1
A method to record data in a solid substrate comprises modulating a polarization angle of a coherent optical pulsetrain, and, while the polarization angle is being modulated, focusing the coherent optical pulsetrain on a locus moving thr...  
WO/2020/227451A1
A method for forming a diamond-like carbon (DLC) coating on an article is provided, comprising: alternatingly performing a deposition process and an ashing process on the article a determined number of times, wherein during the depositio...  
WO/2020/225279A1
The invention concerns a quantum memory (10) comprising: - a memory space (12) comprising qubits, at least one qubit comprising at least one polypeptide comprising at least one alpha helix secondary structure.  
WO/2020/226949A1
A cascaded memory system includes a memory module having a primary interface coupled to a memory controller via a first communication channel and a secondary interface coupled to a second memory module via a second communication channel....  
WO/2020/223955A1
A function equivalence check method includes receiving a cell list, receiving an analog constraint of a cell in the cell list to generate the full-coverage input stimuli; performing a behavioral-level simulation using the full-coverage i...  
WO/2019/236118A8
Memory devices, memory systems, and methods of operating memory devices and systems are disclosed in which a single command can trigger a memory device to perform multiple operations, such as a single refresh command that triggers the me...  
WO/2020/226901A1
A memory processing unit can be configured to compute partial products between one or more elements of a first matrix stored in a given row of a memory cell array and sequential bits of one or more elements of a second matrix. The partia...  
WO/2020/223844A1
A double data rate circuit includes a clock generator, a clock divider and a multiplexer. The clock generator is used to receive a source clock signal to generate a pair of complementary clock signals. The clock divider is coupled to the...  
WO/2020/227305A1
The disclosure provides specific initiator/mediator chemistry for latent imaging polymers for volume Bragg gratings. Light mediated chemistry including the use of nitroxides allows a first step imaging to occur, where a light induced pat...  
WO/2020/227231A1
Techniques disclosed herein relate to holographic optical materials and elements. An example of a holographic recording material includes matrix monomers characterized by a first refractive index and configured to polymerize to form a po...  
WO/2020/223549A1
A method for manufacturing a magnetic memory element structure using a Ru hard mask and a post pillar thermal annealing process. A Ru hard mask is formed over a plurality of memory element layers and an ion milling is performed to transf...  
WO/2020/222883A1
A memory array is provided that includes a first memory level including a plane of first selector material, and a plurality of first memory cells each including a corresponding first magnetic memory element coupled in series with a corre...  
WO/2020/223007A1
Automatically recommending sound effects based on visual scenes enables sound engineers during video production of computer simulations, such as movies and video games. This recommendation engine may be accomplished by classifying (200) ...  
WO/2020/222869A1
Configurable input blocks and output blocks and physical layouts are disclosed for analog neural memory systems that utilize non-volatile memory cells. An input block can be configured to support different numbers of arrays arranged in a...  
WO/2020/222721A1
The invention relates to the field of video content editing and playback. A digital video editing and playback method in which a branched, structured stream of media material is produced and edited, and a user is presented, during viewin...  
WO/2020/223532A1
A magnetic tunnel junction is provided. The magnetic tunnel junction comprises an insulating tunnel barrier and a fixed ferromagnet layer adjacent the tunnel barrier. The fixed ferromagnet comprises a fixed magnetization along an easy ax...  
WO/2020/223022A1
In one embodiment, a printed circuit board (PCB) has a first central processing unit (CPU) socket and a second CPU socket substantially in line with the first CPU socket, and also has a first plurality of dual in-line memory module (DIMM...  
WO/2020/222881A1
A memory with asymmetric command latency characteristics for WRITE operations utilizing WOM coding methodologies to reduce programming latency across a number of WRITE operations.  
WO/2020/222884A1
A spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM) device includes a SOT MRAM cell containing a first two terminal selector element, a nonmagnetic metallic assist plate, and a magnetic tunnel junction located between ...  
WO/2020/197686A8
Systems and methods are disclosed for generating content. The system identifies first and second objects in a plurality of frames of a source content segment. The system creates a data structure for each object, where data structures com...  
WO/2020/223474A1
An electronic device comprises a multi-chip package including multiple memory dice that include a memory array, charging circuitry, polling circuitry and a control unit. The charging circuitry is configured to perform one or more memory ...  
WO/2020/222551A1
The present invention relates to a magnetic field or electric field generating device using electromagnetic wave holography in which, in an electromagnetic wave hologram, a reference wave and an object wave are irradiated on a permanent ...  
WO/2020/222059A1
Provided is an imaging device that can perform image processing. According to the present invention, analog data (image data) acquired with an imaging operation is retained in a pixel, and data derived by multiplying the analog data by a...  
WO/2020/222351A1
A serially arranged printed circuit board according to an embodiment of the present invention comprises: a first solid-state drive (SSD) semiconductor comprising a first terminal portion formed on one side thereof; an Nth SSD semiconduct...  
WO/2020/220274A1
A bias circuit includes a charging current reproduce unit, a cell current reproduce unit, a current comparator, and a bit line bias generator. The charging current reproduce unit generates a charging reference voltage according to a char...  
WO/2020/222068A1
This storage device comprises: m memory cell blocks; m×(k+1) word lines; n bit lines; and a word line driver circuit (m, k, and n are integers greater than or equal to 1). The memory cell block has: (k+1) rows × n columns of memory cel...  
WO/2020/222991A1
Methods, systems, and devices for performing safety event detection for a memory device are described. For example, a memory array of a memory device may operate in a first mode of operation (e.g., a normal mode of operation). An event a...  
WO/2020/222882A1
Techniques are described for detecting a short circuit between a word line and a source line in a memory device, and to a method for recovering from such a short circuit. In one aspect, the short circuit is detected in a program operatio...  
WO/2020/218744A1
The present application relates to a method for detecting an unauthorized copy of a content and a service server using same. The method for detecting an unauthorized copy of a content according to an embodiment of the present invention m...  
WO/2020/219333A1
Methods, systems, and devices for multi-voltage operation for driving a multi-mode channel are described. A transmitting device and a receiving device may be coupled via a channel, and the channel may support multiple modes such as a ter...  
WO/2020/219293A1
A compute system includes an execution unit (e.g. of a CPU) with a memory controller providing access to a hybrid physical memory. The physical memory is "hybrid" in that it combines a cache of relatively fast, durable, and expensive mem...  
WO/2020/215610A1
A magnetic tunnel junction device of a magnetic random access memory, comprising a reference layer (13), a tunneling dielectric layer (14), and a memory layer (15) stacked in sequence from bottom to top, wherein the memory layer (15) is ...  
WO/2020/215906A1
An array substrate, a driving method, and a display device. The array substrate comprises: a plurality of gate lines (G1, G2, …, Gn), each gate line (G1, G2, …, Gn) driving a row of pixel units (200); a plurality of cascaded shift re...  
WO/2020/219187A1
A Josephson memory array and logic circuits use quasi-long-Josephson-junction interconnects to propagate signals at fast speeds and low energy expense, while permitting for memory arrays as dense fabrics of relatively simple unit cell su...  
WO/2020/219397A1
An integrated circuit die element comprises one or more field-programmable gate arrays (FPGAs) elements; a reconfigurable dual function memory array, the reconfigurable dual function memory array including a plurality of reconfigurable m...  
WO/2020/219122A1
A memory array includes strings that are configured to store keywords and inverse keywords corresponding to keys according to content addressable memory (CAM) storages schemes. A read circuit performs a CAM read operation over a pluralit...  
WO/2020/216751A1
Systems and methods for generating media content include processing an audio file to determine one or more parameters of the audio file. Based on a skin associated with the audio file, one or more media effects are determined correspondi...  

Matches 501 - 550 out of 863,212