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Matches 501 - 550 out of 661,464

Document Document Title
WO/2021/259725A1
A deep-learning-based system for performing automated multitrack mixing based on a plurality of input audio tracks is described herein. The system comprises one or more instances of a deep-learning-based first network and one or more ins...  
WO/2021/262736A1
A compute-in-memory array is provided in which each neuron includes a capacitor and an output transistor. During an evaluation phase, a filter weight voltage and the binary state of an input bit controls whether the output transistor con...  
WO/2021/262407A1
Methods, apparatuses, and systems for in-or near-memory processing are described. Bits of a first number may be stored on a number of memory elements, wherein each memory element of the number of memory elements intersects a bit line and...  
WO/2021/260377A1
Various implementations described herein refer to a device having a memory structure with a substrate. The device may have a signal wire buried or partially buried 5 within at least one of the substrate and a dielectric for transmitting ...  
WO/2021/261858A1
Disclosed is an electronic device comprising a display, a semiconductor memory module, a memory controller, a processor, and a memory operatively connected to the processor. The electronic device may generate a test signal to detect a de...  
WO/2021/262730A1
A memristive device is described. The memristive device includes a first layer having a first plurality of conductive lines, a second layer having a second plurality of conductive lines, and memristive interlayer connectors. The first an...  
WO/2021/258926A1
A display substrate and a display device. The display substrate (10) comprises a base substrate (100) and a plurality of shift register units (200) provided on the base substrate, the plurality of shift register units (200) being arrange...  
WO/2021/259332A1
Disclosed are a hard disk mounting mechanism, a hard disk assembly and an electronic device, relating to the technical field of communications. The hard disk mounting mechanism comprises a support frame, an adapter circuit board, and a p...  
WO/2021/259826A1
A method (1) for preparing a laser marking system (100) to create a colored laser mark on a specimen comprising the following steps: a) Providing a laser marking system (100) and a specimen (105) comprising a surface layer (105a), wherei...  
WO/2021/262504A1
Methods and systems are described that enable manufacturing of holograms with high spatial frequencies and allow composite master holograms to be formed in reflection configurations. An example system for replicating transmission-type ho...  
WO/2021/260973A1
[Problem] To provide a record player and a tone arm capable of suppressing a tracking error and an inside force with a simple configuration. [Solution] A tone arm comprises: a first arm rotating about a rotational axis along a horizontal...  
WO/2021/259593A1
The invention relates to a method of protecting a DRAM memory device from the row hammer effect, the memory device comprising a plurality of banks composed of memory rows, the method being implemented by at least one logic prevention dev...  
WO/2021/262260A1
Aspects of a storage device including a master chip controller and a slave chip processor and memory including a plurality of memory locations are provided which allow for simplified processing of descriptors associated with host command...  
WO/2021/262441A1
Methods, systems, and devices for a read algorithm for a memory device are described. When performing a read operation, the memory device may access a memory cell to retrieve a value stored by the memory cell. The memory device may compa...  
WO/2021/262349A1
The present disclosure relates to pretreating a magnetic recording head for magnetic media drive. For a heat assisted magnetic recording (HAMR) head, a light source provides the necessary heat for the drive to operation. A vertical cavit...  
WO/2021/257260A1
Memory devices have an array of elements in two or more dimensions. The memory devices use multiple access lines arranged in a grid to access the memory devices. Memory cells are located at intersections of the access lines in the grid. ...  
WO/2021/253708A1
A memory fault handling method and apparatus, a device and a storage medium relate to the technical field of computers. The handling method comprises: obtaining a fault analysis result by analyzing historical fault information (101); and...  
WO/2021/257184A1
A system includes a development tool for adding electronically-driven effects to a dynamic user-influenced media experience. The development tool is adapted to receive first user input and second user input. The first user input defines ...  
WO/2021/256455A1
[Problem] To provide a destruction device management method capable of maximally suppressing the risk of an information recording medium, which is supposed to be treated as a waste, being taken out and distributed into a used-goods marke...  
WO/2021/257119A1
Methods and systems for navigating content are provided. A method includes detecting an input to perform a content navigation operation in a display interface, the input designating a two-dimensional path in a content display interface. ...  
WO/2021/257475A1
Methods, systems, and devices for operational monitoring for memory devices are described. Some memory devices may degrade over time, and this degradation may include or refer to a reduction of an ability of the memory device to reliably...  
WO/2021/253392A1
A display substrate and a manufacturing method therefor, and a display device. The display substrate comprises: a base substrate, comprising a display region and a peripheral region located on at least one side of the display region; and...  
WO/2021/254087A1
A shift register, a gate drive circuit and a driving method therefor. The shift register comprises a display pre-charge reset subcircuit, a sensing pre-charge reset subcircuit, a pull-down control subcircuit, an output subcircuit, a sens...  
WO/2021/257129A1
Apparatuses and techniques are described for performing an erase operation for a set of memory cells, where the erase operation includes an all word line erase phase to save time followed by an odd-even word line erase phase to improve d...  
WO/2021/253254A1
Disclosed are a chip, a chip encapsulation structure and an electronic device, which relate to the technical field of chips. In the chip, a secure area and a non-secure area are constructed, the secure area being connected to the non-sec...  
WO/2021/253826A1
A spin-orbit torque magnetic random access memory unit, an array, and a Hamming distance calculation method, the spin-orbit torque magnetic random access memory unit comprising: a magnetic tunnel junction, a first transistor and a second...  
WO/2021/253716A1
A storage unit (100) and a data reading and writing method therefor, and a storage array. The storage unit (100) comprises bit lines (BL), a tunnel junction (20), and four access transistors (11, 12, 13, and 14); the access transistors (...  
WO/2021/257371A1
The present disclosure is directed to systems and methods for performing a pattern matching operation in a memory device. The memory device may include a controller and memory arrays where the memory arrays store different patterns along...  
WO/2021/256127A1
Provided is a cartridge management system for managing a plurality of cartridges in which magnetic tapes are respectively housed, wherein the cartridge management system comprises a processor and a memory that is incorporated into the pr...  
WO/2021/253717A1
The present invention relates to the technical field of semiconductor manufacturing, and in particular, to a memory, and a forming method therefor and a control method therefor. The memory comprises: a substrate, wherein the substrate is...  
WO/2021/253870A1
A semiconductor integrated circuit and a memory, which relate to the technical field of semiconductors. The semiconductor integrated circuit comprises a first data line (Ldat) connected to a bit line (BL) by means of a column selection m...  
WO/2021/256197A1
This brain-type information processing device has an analog resistance changing element composed of a pair of electrodes and an oxide layer provided between the pair of electrodes, and a drive circuit that superimposes and supplies volta...  
WO/2021/248426A1
Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack and a plurality of memory strings. The memory stack includes interleaved conductive layers and die...  
WO/2021/252179A1
A memory controller includes a command queue and an arbiter for selecting entries from the command queue for transmission to a DRAM. The arbiter transacts streaks of consecutive read commands and streaks of consecutive write commands. Th...  
WO/2021/252819A1
A memory device includes a memory array comprising a first number of planes, a second number of independent plane driver circuits, wherein the second number is less than the first number, and a plane selection circuit to couple the secon...  
WO/2021/252163A1
Methods, systems, and devices for error control for memory device are described. A memory device may be configured to perform memory management operations including error control operations. For example, a memory device may be configured...  
WO/2021/007299A9
Described are circuits and techniques to increase the efficiency of radio-frequency (rf) amplifiers including rf power amplifiers (PAs) through "supply modulation" (also referred to as "drain modulation" or "collector modulation"), in wh...  
WO/2021/251621A1
A card holder-type recording device according to an embodiment of the present invention comprises: a case in which a card is received and within which a plurality of receiving spaces are provided; a back cover which seals the plurality o...  
WO/2021/252648A1
A flexure is described herein. The flexure includes a slider tongue with a proximal end and a distal end. The sliding tongue including a leading edge at the proximal end prone to contact an undersurface of a load beam attached to the fle...  
WO/2021/252030A1
Disclosed herein is a solid-state storage device that reduces read time for read time- sensitive data ("RTS data"). Data-characterizing logic characterizes incoming data from a host system as primary data including the RTS data or second...  
WO/2021/252265A1
Memory systems and techniques for efficiently storing data are described herein. A memory system may include a memory string of multiple dynamic memory cells, with each cell having an access transistor connecting a data-input-line to a c...  
WO/2021/252051A1
Methods, devices, non-transitory computer-readable medium, and systems are described for compressing audio data. The techniques involve obtaining a sequence of digitized samples of an audio signal, performing a transform using the sequen...  
WO/2021/251626A1
Disclosed are a ferroelectric material-based two-dimensional (2D) flash memory and a semiconductor film forming system for manufacturing same. The ferroelectric material-based 2D flash memory comprises: a substrate including a channel re...  
WO/2021/252830A1
Systems, apparatuses, and methods related to memory device sensors are described. Memory systems can include multiple types of memory devices including memory media and can write data to the memory media. Some types of memory devices inc...  
WO/2021/248614A1
A GOA circuit and a display panel. In terms of a circuit structure, the number of thin film transistors required for an inverter is reduced, and the reduction of the number of transistors can effectively reduce the area occupied by a GOA...  
WO/2021/251318A1
Provided is a fluorine-containing ether compound represented by the following formula. R1-R2-O-CH2-R3-CH2-O-R4-R5 (R3 is a perfluoropolyether chain; R2 is represented by formula (2), R4 is represented by formula (3), and R1 and R5 are ea...  
WO/2021/252862A1
A test and measurement instrument includes an input to receive a non-return-to-zero (NRZ) waveform signal from a device under test, a ramp generator to use the NRZ waveform signal to generate a ramp sweep signal, a gate to gate the ramp ...  
WO/2021/252128A1
Some embodiments include a capacitor having a container- shaped bottom portion. The bottom portion has a first region over a second region. The first region is thinner than the second region. The first region is a leaker region and the s...  
WO/2021/251335A1
This fluorine-containing ether compound is represented by formula: R1-CH2-R2-CH2-OCH2CH(OH)CH2O-CH2-R3-CH2-R4 (in the formula, R2 and R3 each represent a perfluoropolyether chain, and R1 and R4 each represent a terminal group including t...  
WO/2021/248667A1
Provided is a semiconductor structure, comprising a storage array unit, the storage array unit being provided with a substrate, a storage array located on the substrate, and a first bonding area located on the periphery of the storage ar...  

Matches 501 - 550 out of 661,464