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Patent Searching and Data


Matches 551 - 600 out of 863,225

Document Document Title
WO/2020/220274A1
A bias circuit includes a charging current reproduce unit, a cell current reproduce unit, a current comparator, and a bit line bias generator. The charging current reproduce unit generates a charging reference voltage according to a char...  
WO/2020/222068A1
This storage device comprises: m memory cell blocks; m×(k+1) word lines; n bit lines; and a word line driver circuit (m, k, and n are integers greater than or equal to 1). The memory cell block has: (k+1) rows × n columns of memory cel...  
WO/2020/222991A1
Methods, systems, and devices for performing safety event detection for a memory device are described. For example, a memory array of a memory device may operate in a first mode of operation (e.g., a normal mode of operation). An event a...  
WO/2020/222882A1
Techniques are described for detecting a short circuit between a word line and a source line in a memory device, and to a method for recovering from such a short circuit. In one aspect, the short circuit is detected in a program operatio...  
WO/2020/218744A1
The present application relates to a method for detecting an unauthorized copy of a content and a service server using same. The method for detecting an unauthorized copy of a content according to an embodiment of the present invention m...  
WO/2020/219333A1
Methods, systems, and devices for multi-voltage operation for driving a multi-mode channel are described. A transmitting device and a receiving device may be coupled via a channel, and the channel may support multiple modes such as a ter...  
WO/2020/219293A1
A compute system includes an execution unit (e.g. of a CPU) with a memory controller providing access to a hybrid physical memory. The physical memory is "hybrid" in that it combines a cache of relatively fast, durable, and expensive mem...  
WO/2020/215610A1
A magnetic tunnel junction device of a magnetic random access memory, comprising a reference layer (13), a tunneling dielectric layer (14), and a memory layer (15) stacked in sequence from bottom to top, wherein the memory layer (15) is ...  
WO/2020/215906A1
An array substrate, a driving method, and a display device. The array substrate comprises: a plurality of gate lines (G1, G2, …, Gn), each gate line (G1, G2, …, Gn) driving a row of pixel units (200); a plurality of cascaded shift re...  
WO/2020/219187A1
A Josephson memory array and logic circuits use quasi-long-Josephson-junction interconnects to propagate signals at fast speeds and low energy expense, while permitting for memory arrays as dense fabrics of relatively simple unit cell su...  
WO/2020/219397A1
An integrated circuit die element comprises one or more field-programmable gate arrays (FPGAs) elements; a reconfigurable dual function memory array, the reconfigurable dual function memory array including a plurality of reconfigurable m...  
WO/2020/219122A1
A memory array includes strings that are configured to store keywords and inverse keywords corresponding to keys according to content addressable memory (CAM) storages schemes. A read circuit performs a CAM read operation over a pluralit...  
WO/2020/216751A1
Systems and methods for generating media content include processing an audio file to determine one or more parameters of the audio file. Based on a skin associated with the audio file, one or more media effects are determined correspondi...  
WO/2020/219149A1
A motion-sensing circuit for determining a direction of motion and a velocity of an object includes a first photo-receptor for sensing the object, an excitatory active memristor neuron circuit coupled to the first photo-receptor, a secon...  
WO/2020/218809A1
A three-dimensional flash memory is disclosed. According to one embodiment, the three-dimensional flash memory has a structure in which a boosting area is reduced, a structure to which a small block is applied, a structure to which a COP...  
WO/2020/219150A1
Methods of operating a memory device are disclosed. A method may include determining a number of active commands associated with at least one memory bank of a memory device during a first time interval. The method may further include adj...  
WO/2020/217195A1
Magnetic element (10) comprising a first ferromagnetic layer (21) having a first magnetization (210) comprising a stable magnetization vortex configuration having a vortex core (211). The first ferromagnetic layer (21) comprises an inden...  
WO/2020/219140A1
A magnetoresistive device may include a first ferromagnetic region, a second ferromagnetic region, and an intermediate region positioned between the first ferromagnetic region and the second ferromagnetic region. The intermediate region ...  
WO/2020/217138A2
A semiconductor device for storing information as multivalued potentials is provided. The semiconductor device comprises memory cells, first and second reference cells, first and second sense amplifiers, and first to third circuits. The ...  
WO/2020/214434A1
Method of operating an integrated circuit device, and apparatus so configured, might include applying a first voltage level to a first conductor while applying a second voltage level to a second conductor, applying a third voltage level ...  
WO/2020/213311A1
The purpose of the present invention is to avoid invalid access due to snapback when simultaneously accessing a plurality of memory cells. A storage unit is provided with a plurality of first wires extending in a first direction, a plu...  
WO/2020/213240A1
In order to improve memory access parallelism without sacrificing the operation margin, a storage unit is provided with a plurality of first wires extending in a first direction, a plurality of second wires extending in a second directio...  
WO/2020/214782A1
Methods, systems, and devices for signal path biasing in an electronic system (e.g., a memory system) are described. In one example, a memory device, a host device, or both may be configured to bias a signal path, between an idle state a...  
WO/2020/212443A1
A memristor-based circuit is described in which a voltage generator is arranged to apply a series of voltage pulses to a memristor to progressively change the resistance of the memristor. A comparator is arranged: to receive an input ele...  
WO/2020/214217A1
Techniques are disclosed for reducing an injection type of read disturb in a memory device. During a program loop, when NAND strings in a selected sub-block are programmed, a pre-verify voltage pulse is applied to a selected word line an...  
WO/2020/212761A1
The present invention relates to a method for assisting the acquisition of a media content at a scene (S) provided with at least one main acquisition unit (C) connected to a server (2), characterized it comprises performing by a processi...  
WO/2020/211468A1
A read circuit of a memory, and the memory. The read circuit comprises an amplification unit. A first end of the amplification unit is connected to a first end of a resistive sense memory unit, a second end of the amplification unit is c...  
WO/2020/214827A1
A charge-transfer transistor couples between a bit line and a sense node for a sense amplifier. During a read operation, a charge -transfer driver drives a gate voltage of the charge-transfer transistor to control whether the charge -tra...  
WO/2020/214195A1
Systems and methods for repairing a memory. A method includes performing a repair analysis of the embedded memories to produce repair information. The method includes storing the repair information in the registers, where the registers a...  
WO/2020/139425A3
The disclosure relates in some aspects to on-chip processing circuitry formed within the die of a non-volatile (NVM) array to perform data searches. In some aspects, the die includes components configured to sense wordlines of stored dat...  
WO/2020/214358A1
Methods, systems, and devices for multi-component cell architectures for a memory device are described. A memory device may include self-selecting memory cells that include multiple self-selecting memory components (e.g., multiple layers...  
WO/2020/209906A1
Refreshing memory cells includes storing each bit of a B-bit word in a different sub-array of a memory device. Each of the bits is associated with a bit position, and the memory device includes a plurality of sub-arrays. The system and m...  
WO/2020/207404A1
A shift register unit (100, 200), a gate drive circuit (300) and a compensation method and drive method therefor, and a display device (400, 500). The shift register unit (100, 200) comprises: a shift register circuit (120, 220) provided...  
WO/2020/209910A1
Techniques are disclosed for reducing an injection type of program disturb in a memory device. In one aspect, a discharge operation is performed at the start of a program loop. This operation discharges residue electrons from the channel...  
WO/2020/210113A1
Apparatuses and methods for driving word driver lines in a gradual manner are disclosed herein. Word driver lines may be driven to intermediate potentials between high and low potentials. In some examples, the word driver lines may be dr...  
WO/2020/210680A1
A digital signal extraction device that includes an input configured to receive a digital audio input signal from an audio media player, an output configured to provide high-resolution digital audio output to an external digital-to-analo...  
WO/2020/209977A1
Disclosed herein is an apparatus that includes: a data terminal; a first output transistor connected between the data terminal and a first power line supplying a first power potential; a first tristate circuit including an output node co...  
WO/2020/209885A1
A method for programming a resistive random-access memory (ReRAM) cell includes passing a first current through the ReRAM device for a first period of time, the first current selected to create a leakage path through the ReRAM device, an...  
WO/2020/209994A1
Techniques are described for maintaining a stable voltage difference in a memory device, for example, during a critical operation (e.g., a sense operation). The voltage difference to be maintained may be a read voltage across a memory ce...  
WO/2020/209884A1
A ReRAM memory cell includes a ReRAM device including a solid electrolyte layer disposed between a first ion-source electrode and a second electrode and a select circuit including two series-connected select transistors connected in seri...  
WO/2020/210098A1
An apparatus (e.g., a content addressable memory system) can have a controller, a first content addressable memory coupled to the controller, and a second content addressable memory coupled to the controller. The controller can be config...  
WO/2020/210263A1
A semiconductor device comprises a transistor formed on a silicon substrate and a capacitor electrically connected to the transistor by a conductive via; the capacitor comprises a polar layer comprising a base polar material doped with a...  
WO/2020/206720A1
A GOA circuit (10) and a display panel. A relatively simple circuit design is adopted to output a negative pulse waveform signal, and the GOA circuit (10) is improved by means of a first capacitor (C1) and a second capacitor (C2), so tha...  
WO/2020/209947A1
A mounting system which includes a pocket for receiving a digital recorder or a wireless transmitter and a connector for connecting to the body of a microphone device, such as a hand held microphone. The pocket is made of a polyurethane ...  
WO/2020/210390A1
A quasi-volatile memory (QV memory) stack includes at least one semiconductor die, having formed thereon QV memory circuits, bonded to a second semiconductor on which a memory controller for the QV memory ("QV memory controller") is form...  
WO/2020/209968A1
Methods, systems, and devices for a memory device with multiplexed digit lines are described. In some cases, a memory cell of the memory device may include a storage component and a selection component that includes two transistors. A fi...  
WO/2020/210097A1
An apparatus (e.g., a content addressable memory system) can have a controller; a first content addressable memory coupled to the controller and a second content addressable memory coupled to the controller. The controller can be configu...  
WO/2020/209632A1
The present invention relates to a data group playback device, and a system and method for same. The object of the present invention is to provide a data group playback device, and a system and method for same, wherein the data group pla...  
WO/2020/199490A1
A dual-mode error detection memory, comprising an instruction processing module, a storage module, a control signal module, an encoding module, and a decoding module, wherein an error correction code switch flag is provided inside the in...  
WO/2020/204651A1
In a memory device comprising a ternary memory cell, the ternary memory cell may comprise: a first inverter and a second inverter which are cross-connected at a first node and a second node, and comprise a pull-up device and a pull-down ...  

Matches 551 - 600 out of 863,225