Login| Sign Up| Help| Contact|

Patent Searching and Data


Matches 601 - 650 out of 661,464

Document Document Title
WO/2021/242444A1
Systems and methods related to a memory system with a predictable read latency from media with a long write latency are described. An example memory system includes an array of tiles configured to store data corresponding to a cache line...  
WO/2021/232821A1
A hard disk fixing device and a main unit. The hard disk fixing device comprises a handle (4), a locking member (2), a drive member (3), and a hard disk holder (5). A locking hole (52) is disposed on a first side surface of the hard disk...  
WO/2021/232981A1
The present invention relates to the technical field of hard disk devices, specifically to a blockchain-based hard disk device. The hard disk device comprises a storage unit and a protection unit; a hard disk body is used for storing inf...  
WO/2021/232871A1
Disclosed is a gate drive circuit, comprising: a frequency multiplication control circuit (1) and an effective output circuit (2), the effective output circuit (2) comprising a plurality of cascaded first shift registers, wherein the fir...  
WO/2021/237106A1
The present disclosure relates to systems, methods, and computer readable media for implementing fault isolation in memory without incurring a die size penalty. For example, systems disclosed herein may involve identifying row addresses ...  
WO/2021/232259A1
An integration method for a 3D NAND flash memory device includes disposing a plurality of 3D triple-level cell (TLC) NAND flash memories on a CMOS die; disposing at least a NOR Flash memory on the CMOS die of the 3D NAND flash memory dev...  
WO/2021/232154A1
A system and method are provided for generating a factory layout to dynamically optimize a media content production in a real-time environment. The system includes a media production optimizer with a widget controller that provides widge...  
WO/2021/232223A1
An operation method for a 3D NAND flash includes writing data into a WLn layer of the plurality of wordline layers of an unselect bit line of the plurality of bit lines in a write operation; and applying a first pass voltage on at least ...  
WO/2021/236280A1
The present disclosure includes apparatuses, methods, and systems for preventing parasitic current during program operations in memory. An embodiment includes a sense line, an access line, and a memory cell. The memory cell includes a fi...  
WO/2021/235164A1
A linear optical material according to an aspect of the present disclosure is represented by formula (1). At least one selected from the group consisting of R1 to R5, at least one selected from the group consisting of R6 to R10, and at l...  
WO/2021/232280A1
A redundant power supply circuit for a vehicle, the power supply comprising electronic devices (10), a controller (20), a first power supply (30) and a second power supply (40). The electronic devices (10) are disposed on a vehicle for u...  
WO/2021/233324A1
In certain aspects, a memory device includes a memory string including a drain select gate (DSG) transistor, a plurality of memory cells, and a source select gate (SSG) transistor, and a peripheral circuit coupled to the memory string. T...  
WO/2021/233398A1
Embodiments of the present application provide a wireless communication method. The negotiation of the audio effect processing is performed after a wireless connection between a master device and a slave device is established. The master...  
WO/2021/235380A1
Provided are: a magnetic recording medium having a high magnetocrystalline anisotropy constant Ku and coercive force Hc; and a sputtering target used to produce this magnetic recording medium. This Pt-oxide sputtering target is formed ...  
WO/2021/232990A1
A method for generating memory address data, a computer readable storage medium, and a computer device. The method for generating memory address data comprises: presetting mapping relationships between a physical address and a row, a col...  
WO/2021/232233A1
A control method, for a memory array, the control method comprises programming the bit-cell of the memory array in a programming stage; and discharging the bit-cell of the memory array in a discharge stage; wherein the programming stage ...  
WO/2021/236287A1
A system for customizing text messages in modifiable videos of a multimedia messaging application (MMA) is provided. In one example embodiment, the system includes a processor and a memory storing processor-executable codes, wherein the ...  
WO/2021/235165A1
A nonlinear optical material according to one aspect of the present invention is represented by formula (1).  
WO/2021/236152A1
A self-timed sensing architecture for reading a selected cell in an array of non-volatile cells is disclosed. The sensing circuitry generates a signal when a stable sensing value has been obtained from the selected cell, where the stable...  
WO/2021/231069A1
Methods, systems, and apparatuses related to training neural networks are described. For example, data management and training of one or more neural networks may be accomplished within a memory device, such as a dynamic random-access mem...  
WO/2021/230459A1
The present invention provides a sound source file structure, a recording medium in which same is recorded, and a sound source file creating method, wherein a sound source output device for outputting lyrics together with melody starts a...  
WO/2021/231953A1
A suspension is described. The suspension includes a base plate and a load beam coupled to the base plate. The base plate includes a distal elongated element and a proximal elongated element. The distal elongated element includes at leas...  
WO/2021/231031A1
Some embodiments include an integrated assembly having a stack of alternating first and second levels. The first levels contain conductive material and the second levels contain insulative material. At least some of the first and second ...  
WO/2021/231020A1
In general, techniques are described regarding initiating a recursive blending of a plurality of frames following a camera transition. One or more processors may, subsequent to a transition from a first camera mode to a second camera mod...  
WO/2021/228935A1
Described herein is a method for improving dialogue intelligibility during playback of audio data on a playback device, wherein the audio data comprise dialogue audio data, and at least one of music and effects audio data, the method inc...  
WO/2021/231384A1
Memory system configured to perform write assist, the memory system including: a first head switch, a second head switch and a plurality of memory control circuits, each having: a first column selection switch, the first head switch bein...  
WO/2021/229841A1
In the present invention, a record playback system (1) comprises a record player (100) and a playback device (10) (measurement device). The playback device (10): measures, when a plurality of test signals for measuring characteristics of...  
WO/2021/231076A1
A memory controller an arbiter which causes streaks of read commands and streaks of write commands over the memory channel. During a streak, the arbiter monitors an indicator of data bus efficiency of the memory channel. Responsive to th...  
WO/2021/229260A1
The present disclosure relates to a method for accessing an array of memory cells, comprising the steps of storing user data in a plurality of memory cells of a memory array, storing, in a counter associated to the array of memory cells,...  
WO/2021/226811A1
An optical storage, comprising: a chassis; an optical disc cartridge assembly, comprising a plurality of optical disc cartridge sets, the plurality of optical disc cartridge sets being stacked and the adjustable number of optical disc ca...  
WO/2021/230015A1
Provided are a magnetic recording medium, a magnetic tape cartridge, and a magnetic recording playback device. In the magnetic recording medium: the arithmetic mean roughness Ra of a surface of a magnetic layer is 2.2 nm or less; a fluor...  
WO/2021/231067A1
Embodiments of the present disclosure generally include spin-orbit torque magnetoresistive random -access memory (SOT-MRAM) devices and methods of manufacture thereof. The SOT-MRAM devices described herein include an SOT layer laterally ...  
WO/2021/227766A1
A shift register unit and a control method therefor, and a gate drive circuit and a display apparatus. The shift register unit comprises: a first control circuit (110) and an energy storage circuit (150), which directly control the poten...  
WO/2021/231484A1
A learning system receives a video stream of a learning environment and generates predictions on whether participants in the learning environment have achieved a desired learning state. The learning system obtains annotations identifying...  
WO/2021/231075A1
A memory controller interfaces with a dynamic random access memory (DRAM) over a memory channel. A refresh control circuit monitors an activate counter which counts a rolling number of activate commands sent over the memory channel to a ...  
WO/2021/230907A1
Numerous embodiments of analog neural memory arrays are disclosed. Certain embodiments contain improved mechanisms for pulling source lines down to ground expeditiously. This is useful, for example, to minimize the voltage drop for a rea...  
WO/2021/231026A1
Methods, systems, and devices for delay calibration oscillators for a memory device are described. In some examples, a memory device may include a delay chain operable (e.g., for a calibration operation) in a ring oscillator configuratio...  
WO/2021/231493A1
Systems and methods are provided herein for encoding and storing information in nucleic acids. Encoded information is partitioned and stored in nucleic acids having native key-value pairs that allow for storage of metadata or other data ...  
WO/2021/228953A1
The present disclosure relates to a precharge circuitry for bit lines of an array of memory cells, the precharge circuitry comprising a precharge and limiting unit configured to precharge a first bit line and a second bit line, the prech...  
WO/2021/226813A1
A storage device, comprising: a cabinet; a storage drawer group, the storage drawer group comprising at least two layers of storage drawers that are sequentially stacked and detachably installed in the cabinet, and the storage drawers be...  
WO/2021/227788A1
A pixel driving circuit and a driving method therefor, and a display panel. The pixel driving circuit comprises a data write circuit (1), a driving circuit (2), a light-emission control circuit (3), a compensation circuit (4) and a stora...  
WO/2021/227310A1
A three-dimensional memory includes a bottom cell layer of memory cells, a top cell layer of memory cells, and at least one middle cell layer of memory cells. The bottom cell layer is coupled to bottom cell bit lines, bottom cell bit lin...  
WO/2021/231116A1
Methods, systems, and devices for a refresh operation of a memory cell are described. A memory device may include a plurality of rows of memory cells. Each row of memory cells may undergo a quantity of access operations (e.g., read opera...  
WO/2021/228448A1
A multipath bootstrapped sampling circuit includes a sampling capacitor, a sampling transistor interposed between the sampling capacitor and the analog input signal voltage, two bootstrap capacitors, and a bootstrap switching network per...  
WO/2021/230905A1
Numerous embodiments of analog neural memory arrays are disclosed. Two or more physical memory cells are grouped together to form a logical cell that stores one of N possible levels. Within each logical cell, the memory cells can be prog...  
WO/2021/223075A1
A control method of a non-volatile memory device is provided. The non-volatile memory device comprising a memory array comprising a plurality of memory strings, each memory string comprising a plurality of memory cells connected in serie...  
WO/2021/223565A1
A shift register, a driving method, a driving control circuit, and a display device. The method comprises: at a data refresh stage (T10), applying to an input signal end (IP) an input signal having a pulse level, applying a control clock...  
WO/2021/226397A1
Systems and methods are disclosed including a memory component and a processing device, coupled to the memory component. The processing device can program a block of the memory component using a first type of memory cells storing a first...  
WO/2021/223547A1
A subunit for analog and digital combined in-memory computing, which is used for 1-bit multiplication calculation and only needs nine transistors; on this basis, it is proposed that a plurality of subunits share a calculation capacitor a...  
WO/2021/225782A1
One example provides a computer-implemented method for reading data stored as birefringence values in a storage medium. The method comprises acquiring an image of a voxel of the storage medium, applying a first low-pass filter with a fir...  

Matches 601 - 650 out of 661,464