Login| Sign Up| Help| Contact|

Patent Searching and Data


Matches 651 - 700 out of 661,464

Document Document Title
WO/2021/225730A1
Techniques and mechanisms for coupling chiplets to microchips utilizing active bridges. The active bridges include circuits that provide various functions and capabilities that previously may have been located on the microchips and/or th...  
WO/2021/225783A1
An example apparatus includes a three-dimensional (3D) memory array including a sense line and a plurality of vertical stacks. Each respective on of the vertical stacks includes a different respective portion of the sense line, a first m...  
WO/2021/225839A1
Apparatuses and methods can be related to generating an asynchronous process topology in a memory device. The topology can be generated based on the results of a number of processes. The processes can be asynchronous given that the proce...  
WO/2021/223099A1
A control method of a programming process for a three-dimensional (3D) NAND flash memory array comprises programming a bit-cell of the 3D NAND flash memory array in a programming stage; and verifying whether the bit-cell of the 3D NAND f...  
WO/2021/226165A1
An activation device includes a wireless communication interface, an activation circuitry, and a trigger device. The wireless communication interface is configured to communicate with a mobile phone in a personal area network. The activa...  
WO/2021/223583A1
A shift register unit, a signal generation unit circuit, a driving method, and a display device. The shift register unit comprises a first node control circuit (11), a second node control circuit (12), and an output circuit (13). The fir...  
WO/2021/224944A1
A circuit for recycling energy in bit lines (BL and BLB) of SRAM during write operation by (i) storing the charges BL and BLB to an intermediate voltage source (VLB) in a discharge phase and (ii) restoring the charges from the intermedia...  
WO/2021/225629A1
A data storage drive includes a magnetic recording media comprising a ferroelectric layer between a bottom electrode layer and a top electrode layer. An applied voltage to the ferroelectric layer generates a strain that is transferred to...  
WO/2021/225716A1
A bit cell circuit of a most-significant bit (MSB) of a multi-bit product generated in an array of bit cells in a compute-in-memory (CIM) array circuit is configured to receive a higher supply voltage than a supply voltage provided to a ...  
WO/2021/225706A1
One example provides a system (800) for reading birefringent data. The system comprises one or more light sources (802, 804), a first polarization state generator (808) positioned to generate first polarized light from light of a first w...  
WO/2021/223098A1
Disclosed are systems and methods that determine whether instances of data (e.g., forward activations, backward derivatives of activations) that are used to train deep neural networks are to be stored on-chip or off-chip. The disclosed s...  
WO/2021/223819A2
The invention relates to a system box for receiving a video stream, wherein the video stream is sent from a studio, characterised in that the system box comprises at least the following components: a computer; a decoder; a receiving unit...  
WO/2021/221757A1
A data storage device is disclosed comprising a top head actuated over a top surface of a first disk, a bottom head actuated over a bottom surface of the first disk, a top head actuated over a top surface of a second disk, and a bottom h...  
WO/2021/221096A1
Provided is an in-plane magnetized film with which magnetic performance such as a coercive force Hc of at least 2.00 kOe and a residual magnetization Mrt per unit area of at least 2.00 memu/cm2 can be achieved without performing heating-...  
WO/2021/222742A1
Lateral programmable metallization cells may comprise a solid electrolyte layer, an anode coupled to the solid electrolyte layer, and a cathode coupled to the solid electrolyte layer. Exemplary solid electrolyte layers may comprise a fir...  
WO/2021/221095A1
The present invention provides an in-plane magnetized film multilayer structure which is capable of achieving magnetic properties, namely a coercivity Hc of 2.00 kOe or more and a remanent magnetization Mrt per unit area of 2.00 memu/cm2...  
WO/2021/220548A1
This memory device comprises: a first non-volatile memory die; a second non-volatile memory die that is layered above the first non-volatile memory die; a controller; and first and second temperature sensors included in the first and sec...  
WO/2021/218626A1
The method disclosed in the present application comprises: acquiring travel data during a travel, the travel data comprising recording data and heartbeat data; splitting the travel data into n travel segments, each travel segment compris...  
WO/2021/221726A1
A spin-orbit torque (SOT) magnetic tunnel junction (MTJ) device includes a substrate, a seed layer over the substrate, and a bismuth antimony (BiSb) layer having (0120) orientation on the seed layer. The seed layer includes a silicide la...  
WO/2021/221727A1
The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller, random-access memory (RAM), and a NVM unit, where in the NVM unit comprises a plurality of zones. The RAM unit c...  
WO/2021/219822A1
The invention relates to an arrangement for performing a vector-matrix multiplication by means of synaptic components, consisting of: - a matrix arrangement of components in a differential arrangement, which are periodically charged and ...  
WO/2021/222846A1
A memory device includes a memory array comprising a plurality of wordlines and a regulator circuit selectively coupled to the plurality of wordlines, wherein the regulator circuit is configured to perform a detection routine to sample a...  
WO/2021/218779A1
Disclosed is a shift register circuit (RS), comprising a denoising control sub-circuit (20) and a denoising sub-circuit (30), wherein the denoising control sub-circuit (20) is configured to generate an alternating voltage signal accordin...  
WO/2021/221756A1
A method of operating a data storage device is disclosed comprising an enclosure comprising a first head actuated over a first disk surface and a second head actuated over a second disk surface. A manufacture printed circuit board (RGB) ...  
WO/2021/217386A1
A memory device includes a plurality of memory blocks, and a control circuit. A selected memory block of the plurality of memory blocks comprises a top select gate, a bottom select gate, a plurality of word lines, a common-source line, a...  
WO/2021/222926A1
Methods and apparatuses having an improved write assist scheme are presented. An apparatus includes a power supply node configured to provide power from a power supply to one memory cell to store data; a bitline configured to provide wri...  
WO/2021/217468A1
A display panel, a driving method, and a display device, wherein the display panel comprises: a base substrate (1000), a plurality of subpixels (spx), a plurality of driving lines, a plurality of data lines, and a gate driving circuit (0...  
WO/2021/221955A1
A case for use with a portable computing device is provided. The case comprises a housing for protecting the portable computing device. The housing is configured to attach to the portable computing device. The case further comprises a mu...  
WO/2021/219977A1
Various implementations described herein are related to a device having memory circuitry having an array of memory cells. The device may include output circuitry coupled to the memory circuitry, and the output circuitry may have a first ...  
WO/2021/222521A1
A sensing circuit for detecting hardware trojans in a target integrated circuit is provided. The sensing circuit includes an array of magnetic tunnel junction circuits where each magnetic tunnel junction circuit including one or more mag...  
WO/2021/218569A1
Provided are an array substrate and a fabrication method therefor, a shift register unit, and a display panel. The array substrate comprises a first transistor (T1) having a double gate structure. The array substrate further comprises a ...  
WO/2021/217501A1
A programming method for a memory device is disclosed. The programming method comprises moving a plurality of first charge carriers at a shallow energy level to a channel in a substrate layer before a fine programming operation for a fir...  
WO/2021/222001A1
A system and method for the automatic management of the presentation of information from two or more media sources. This automatic management includes the selective viewing of video information on a prescribed screen, screen window or sc...  
WO/2021/221998A1
A method of setting multi-state memory elements into at least one low-power state may include receiving a command to cause a memory element to transition into one of three or more states; applying a first signal to the memory element to ...  
WO/2021/217359A1
Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes an N-type doped region of a substrate, an N-type doped semiconductor layer on the N-type doped region, a memory s...  
WO/2021/212393A1
A low-leakage memory array (310). The memory array (310) comprises: a read bit line (RBL), a read bit line switch (M0) connecting the ground (VSS) and the read bit line (RBL), and a plurality of memory circuits, wherein each memory circu...  
WO/2021/216130A1
The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a storage unit divided into a plurality of zones. Each zone comprises a plurality of dies, where each die com...  
WO/2021/216602A1
Methods, systems and devices are disclosed to detect and compensate wavefront errors associated with light that spans a large range of wavelengths and different polarization states. One example system includes an optical wavefront sensor...  
WO/2021/217067A1
A system and methods for facilitating transactions relating to slots in a content promoter's performance. The system allows content promoters to publish available slots in their performances and receive submissions from artists requestin...  
WO/2021/212584A1
Systems, apparatus and methods are provided for multi‐drop multi‐load NAND interface topology where a number of NAND flash devices share a common data bus with a NAND controller. A method for controlling on‐die termination in a non...  
WO/2021/216784A1
A set of memory management operations is executed on multiple memory dies of a memory sub-system. Voltage parameter levels corresponding to the set of memory management operations are determined. Information representing a voltage parame...  
WO/2021/216224A1
Methods of operating a memory device are disclosed. A method may include receiving a write command, and in response to the write command, performing a write operation without precharging a local input/output line subsequent to receipt of...  
WO/2021/216566A1
Systems and methods for video analysis are provided. The systems and methods may utilize machine learning to recognize steps of a medical procedure as they are being performed, and compare them with expected steps. The systems and method...  
WO/2021/214663A1
An authentication method comprising requesting (101), by a verifying device (5), an identifier from an end node device (2); verifying (105), in a centralized code registration system, the identifier received from the end node device; inc...  
WO/2021/216766A1
A PZT microactuator such as for a hard disk drive has a restraining layer bonded on its side that is opposite the side on which the PZT is mounted. The restraining layer comprises a stiff and resilient material such as stainless steel. T...  
WO/2021/216523A1
A field deployable soundproof booth for remote audio dubbing including a collapsible support structure onto which a plurality of soundproof material sections are attached after the support structure has been assembled into a deployed pos...  
WO/2021/216137A1
A magnetoresistive memory device includes a first electrode, a second electrode, and a layer stack located between the first electrode and the second electrode. The layer stack may include a ferroelectric material layer and a metamagneti...  
WO/2021/212207A1
Systems and methods for processing image data to coincide in a point of time with audio data to create a master timeline coordinating audio timeline playback and image data display to generate a synchronized multimedia presentation using...  
WO/2021/215112A1
The present invention performs a product-sum operation having high power efficiency while maintaining a small area of a memory cell. This semiconductor device includes a memory cell array in which a plurality of memory cells are arranged...  
WO/2021/215854A1
Disclosed in one embodiment of the present invention is an electronic device comprising: a first electrode part containing a conductive material; a second electrode part spaced apart from the first electrode and containing a conductive m...  

Matches 651 - 700 out of 661,464