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Patent Searching and Data


Matches 751 - 800 out of 665,358

Document Document Title
WO/2023/132653A1
Various embodiments herein provide a method for managing an audio based on a spectrogram. The method includes generating, by a transmitter device, the spectrogram of the audio. The method includes identifying a first spectrogram correspo...  
WO/2023/133114A1
An apparatus and method including a command input to receive a command with a macro identifier from a channel processor, a macro memory storing a plurality of flash control commands, each comprising a corresponding duration and a corresp...  
WO/2023/133600A1
In some embodiments, a computer system displays a caption for a media item at different depths depending on the depth of the portion of the media item over which the caption is displayed. In some embodiments, a computer system displays a...  
WO/2023/124002A1
Provided are a Linux-based audio control method and apparatus, a device, and a storage medium. The method comprises: receiving an audio control instruction sent by an application program in a Linux system by means of a Linux audio servic...  
WO/2023/123667A1
Provided in the embodiments of the present disclosure are a control amplification circuit, a sense amplifier and a semiconductor memory. The control amplification circuit comprises: a power consumption control circuit used for receiving ...  
WO/2023/124096A1
A memory and a read circuit thereof. The memory comprises a plurality of storage arrays. Each storage array comprises a first array and a second array symmetrical to the structure of the first array. The read circuit of the memory compri...  
WO/2023/123666A1
A control amplification method and circuit, a sensitive amplifier and a semiconductor memory. The method comprises: receiving a preset instruction, and determining an isolation power value and a control instruction signal according to th...  
WO/2023/129197A1
Various embodiments are directed to frequency and voltage tuning for systems with multiple application-specific integrated circuits (ASICs) and disclosed herein may be applied to multi-AIC systems in a variety of applications, such as hi...  
WO/2023/129432A1
A system and method for efficiently resetting data stored in a memory array are described. In various implementations, an integrated circuit includes a memory for storing data, and a processing unit that generates access requests for the...  
WO/2023/123649A1
The embodiments of the present disclosure relate to the technical field of semiconductors. Provided are an integrated circuit structure, a memory and an integrated circuit layout. The integrated circuit structure comprises: a data pad; a...  
WO/2023/123158A1
Provided are an apparatus and method for testing solid state drives. The apparatus comprises: a test board, which comprises test ports; a first positioning portion, which is arranged on the test board; and an adapter box, which comprises...  
WO/2023/126111A1
A controller of a non-volatile memory detects errors in data read from a particular physical page of the non-volatile memory. Based on detecting the errors, the controller performs a read voltage threshold calibration for a page group in...  
WO/2023/123796A1
The present application discloses a method for adjusting the phase of a bidirectional data strobe (DQS) signal, which is applied to the field of field-programmable gate arrays and is used for solving the problem of temperature drift of D...  
WO/2023/126385A1
The invention relates to a tunnel junction (12) having a stack formed by a barrier (18) and two electrodes (14, 16), the barrier (18) comprising a layer made of a ferroelectric material, referred to as the ferroelectric layer, the ferroe...  
WO/2023/125446A1
A DRAM refresh circuit and refresh method, and a proof-of-work chip. The DRAM refresh circuit comprises a row address recording unit, which is configured to record a row that has been accessed in a DRAM within the current refresh cycle; ...  
WO/2023/128450A1
A method for generating a time-lapse video may be provided. Specifically, a method may be provided, the method comprising the steps of: identifying an image saving mode; obtaining a first image; obtaining a first time difference and a fi...  
WO/2023/123668A1
The embodiments of the present disclosure provide a control amplification circuit, a sense amplifier and a semiconductor memory. The control amplification circuit comprises: a power supply output circuit used for receiving a power supply...  
WO/2023/123305A1
An enhanced TL-TCAM look-up table hardware search engine. Each word circuit comprises multiple enhanced TL-TCAM cell circuits. An enhanced TL-TCAM cell circuit comprises four memory cells and thirteen N-type transistors. A memory cell MC...  
WO/2023/129398A1
Methods and systems are disclosed for calibrating, by a memory interface system, an interface with dynamic random-access memory (DRAM) using a dynamically changing training clock. Techniques disclosed comprise receiving a system clock ha...  
WO/2023/129242A1
Techniques are described for pre-exporting chunks of video content during video editing of a video editing project. For example, the chunks of the video editing project can be monitored for changes. When a change is detected to a chunk, ...  
WO/2023/129632A2
Methods, apparatus, and systems for high-resolution image storage and analysis are disclosed. In one disclosed embodiment, a method includes analyzing a high-resolution image; partitioning the high- resolution image into logical blocks; ...  
WO/2023/129205A1
A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to determine an error correction code (ECC) code length for KV pair data and/or an ECC code rate for the KV pair d...  
WO/2023/129841A1
Methods, systems, and devices for error detection signaling are described. In some examples, a memory device may include circuitry to detect one or more error conditions. As the memory device is operated, it may store or output a value (...  
WO/2023/129442A2
Aspects of the present disclosure involve a system comprising a computer-readable storage medium storing a program and a method for performing operations comprising: receiving a video that includes a depiction of a real-world object in a...  
WO/2023/119142A1
Superconducting bipolar thermoelectric memory (1) comprising: - a memory cell, a connection in parallel between a bipolar thermoelectric element (2) and a predetermined resistive load (4), and - a writing element, a current generator (6)...  
WO/2023/122445A1
Various embodiments include a memory device that recovers from write errors and read errors more quickly relative to prior memory devices. Certain patterns of write data and read data may result on poor signal quality on the memory inter...  
WO/2023/115400A1
A display substrate, and a display apparatus corresponding thereto and a manufacturing method therefor. The display substrate comprises: a display region and a non-display region, wherein the non-display region is provided with a gate dr...  
WO/2023/121865A1
Techniques for redaction of data that is incidentally recorded are provided. A request for information is received from a user. The requested information includes confidential information. The request is received via a first device. The ...  
WO/2023/121839A1
An approach provides indirect addressing support for PIM. Indirect PIM commands include address translation information that allows memory modules to perform indirect addressing. Processing logic in a memory module processes an indirect ...  
WO/2023/115889A1
An antifuse programming control circuit based on a master-slave charge pump structure, relating to the technical field of antifuse. In the circuit, a main charge pump module obtains an external voltage and is connected to slave charge pu...  
WO/2023/115401A1
A display substrate. The display substrate comprises: a display region and a non-display region, wherein the non-display region is provided with a gate driving circuit. The gate driving circuit comprises a plurality of cascaded shift reg...  
WO/2023/121733A1
A column in a memory array includes one bit cell circuit in each row for storing information about the row. The bit cell circuits store data in a data node and a complement data node in a cross-coupled inverter circuit. Toggling the node...  
WO/2023/119039A1
Provided is a novel semiconductor device. The present invention provides a semiconductor device including a first component, a second component, and an instruction unit, wherein: the first component includes a first storage circuit that ...  
WO/2023/120578A1
This non-volatile memory device (1) comprises: a first current mirror (CM1), a second current mirror (CM2), a first resistor unit (R10) which is connected to a first MOS transistor (M1) included in the first current mirror; a second resi...  
WO/2023/115953A1
The present disclosure provides a storage block and a memory. The storage block comprises a plurality of storage arrays arranged in a first direction, each storage array being divided into at least two array cells in a second direction, ...  
WO/2023/122116A1
An integrated circuit includes a latch array including a plurality of latches logically configured in rows and columns, a plurality of repair latches operatively coupled to the plurality of latches and latch array built in self-test and ...  
WO/2023/121752A1
Systems and methods for providing memory' access commands to memory circuitry using a multi-clock cycle memory command protocol is described. A. command decoder (or controller) of the memory circuitry may efficiently receive a. memory ac...  
WO/2023/115102A1
The creation of a composite electronic video is disclosed. Multiple expert content videos on a range of topics are prepared and stored (5). Multiple intro scripts (4) and multiple outro scripts (6) are also stored. An expert content vide...  
WO/2023/122361A1
Apparatuses and techniques for operating devices with multiple differential write clock signals having different phases are described. For example, a memory controller (114) (e.g., of a host device) can provide two differential write clo...  
WO/2023/118047A1
The present invention relates to a device for information processing, comprising a magnon reservoir made of a material with spontaneous magnetic order, in which two-dimensionally quantized magnon states are present, an input unit (2), an...  
WO/2023/121717A1
The present disclosure generally relates to spin-orbit torque (SOT) magnetic tunnel junction (MTJ) devices comprising a doped bismuth antimony (BiSbE) layer having a (012) orientation. The devices may include magnetic write heads, read h...  
WO/2023/120333A1
Provided is a recording device which can suppress inclination of a spindle shaft. The recording device comprises a base 7 which accommodates a disk 5, a cover 9 attached to the base 7, a spindle shaft 15 which includes one side in an a...  
WO/2023/116212A1
A memory and a memory repair method. The memory comprises a storage region, a failure recording region, and a repair circuit. The storage region is provided with redundant bits; the failure recording region is provided with multi-state b...  
WO/2023/119669A1
This rotary operator (2) comprises: a first rotator (5) that is able to rotate about a virtual rotation axis (Rx); a second rotator (9) that is provided in an attachable/detachable manner, that is rotated integrally with the first rotato...  
WO/2023/115765A1
The embodiments of the present disclosure relate to an automatic storage array extension method and apparatus, and a device and a medium. The method comprises: acquiring the total number of word lines of a target extended storage array, ...  
WO/2023/120106A1
A semiconductor memory device (100) comprises: a normal cell array (11a) that includes a plurality of normal cells (11) each of which is constituted by a nonvolatile memory cell; and a plurality of dummy cells (12) which are disposed in ...  
WO/2023/118519A1
The invention relates to an assembly (1a) of non-volatile resistive memories associated with a selector, comprising: - a selector layer (11) and an upper electrode (12); - a first memory stack (20) comprising a first active layer (21), e...  
WO/2023/121842A1
An approach is provided for managing PIM commands and non-PIM commands at a memory controller. A memory controller enqueues PIM commands and non-PIM commands and selects the next command to process based upon various selection criteria. ...  
WO/2023/122595A1
A system and a method for generating an automated GIF file generation system is described. In one aspect, the method includes accessing an animated GIF file, identifying a plurality of elements displayed in the animated GIF file, applyin...  
WO/2023/115849A1
A storage block and a memory, relating to the technical field of semiconductors. The storage block comprises: a plurality of storage arrays (101) arranged along a first direction and used for storing data and check codes, each storage ar...  

Matches 751 - 800 out of 665,358