Login| Sign Up| Help| Contact|

Patent Searching and Data


Matches 51 - 100 out of 863,225

Document Document Title
WO/2021/059079A1
Provided is a semiconductor device having a large storage capacity. The semiconductor device has first to sixth insulators, first to third conductors, and first to third material layers. The first insulator and the first material layer o...  
WO/2021/025743A3
Superconducting computing system housed in a liquid hydrogen environment and related aspects are described. An example superconducting computing system includes a housing, arranged inside a liquid hydrogen environment, where a lower pres...  
WO/2021/061254A1
An embodiment of a novel memory circuit is described that improves post aging performance of a shared VCC node with a write pre-charge on the supply line. A write pre-charge PMOS device is added to the shared VCC node in some embodiments...  
WO/2021/062220A1
A machine-readable medium and methods of reading and writing same are disclosed. The machine-readable medium comprises a substrate having an array of addressable locations thereon. Each addressable location is adapted to be physically as...  
WO/2021/059542A1
Provided is a magnetic recording medium capable of achieving higher-density recording. This magnetic recording medium is tape-shaped and comprises: a base body mainly containing polyester; and a magnetic layer provided over the base body...  
WO/2021/056804A1
A memory and an addressing method therefor. The memory comprises: an input module for receiving an address/command input signal at least containing an access address, a command and a decoding selection instruction; a storage array, compr...  
WO/2021/056958A1
An anti-fuse storage unit circuit and array circuit and a read/write method therefor. The anti-fuse storage unit circuit comprises: an anti-fuse device; a switch module coupled to the anti-fuse device; a selection module coupled to the s...  
WO/2021/057179A1
A memory, and a writing method and a reading method for the memory. The memory comprises a spin-orbit torque providing layer (10), two storage bits (20), two diodes (30), a first bit line (40), a second bit line (50), a word line (60), a...  
WO/2021/061365A1
Methods, systems, and devices for imprint recovery management for memory systems are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic sta...  
WO/2021/061656A1
The disclosed computer-implemented method for smoothing audio gaps using adaptive metadata identifies an initial audio segment and a subsequent audio segment that follows the initial audio segment. The method accesses a first set of meta...  
WO/2021/054244A1
Provided is a recording device provided with: an acquisition unit which, with respect to accompanying information accompanying to each of a plurality of pieces of data to be recorded that are to be recorded in a recording medium, acquire...  
WO/2021/055207A1
A memory chip having a predefined memory region configured to store program data transmitted from a microchip. The memory chip also having a programmable engine configured to facilitate access to a second memory chip to read data from th...  
WO/2021/054136A1
Provided is a target which has high magnetic flux leakage, undergoes the generation of a reduced amount of particles during sputtering, and is useful for, for example, the manufacturing of a magnetic recording medium. A target represen...  
WO/2021/055206A1
A memory chip having a first set of pins configured to allow the memory chip to be coupled to a first microchip or device via first wiring. The memory chip also having a second set of pins configured to allow the memory chip to be couple...  
WO/2021/055469A1
A computer system includes physical memory devices of different types that store randomly-accessible data in a main memory of the computer system. In one approach, an operating system allocates memory from a namespace for use by an appli...  
WO/2021/055000A1
A method comprises first generating a plane wave light beam. At least one orbital angular momentum is applied to the plane wave light beam to generate and OAM light beam. Transitions of electrons between quantized states within a semicon...  
WO/2021/054202A1
A fluorine-containing ether compound represented by formula (1). (1): R1-R2-CH2-R3-CH2-R4 (In the formula, R1 represents an organic group having an alicyclic structure and from 3 to 13 carbon atoms; R2 represents a group expressed by for...  
WO/2021/053091A1
A memory device is disclosed. The memory device comprises a memory element (2) comprising antiferromagnet (3) having first and second contacts (4, 5), and a circuit (8) for driving a current through the antiferromagnet between the first ...  
WO/2021/054737A1
A resistive switching element is disclosed. The resistive switching element comprises: a first oxide layer and a second oxide layer stacked to each other so as to form an interface, and made of different metal oxides; a two-dimensional e...  
WO/2021/055853A1
Systems and methods are disclosed including a processing device operatively coupled to a first and a second memory device. The processing device can receive a set of data access requests, from a host system, in a first order and execute ...  
WO/2021/051548A1
Disclosed are a read-write circuit and a read-write method for a memristor. The read-write circuit mainly comprises a read circuit and a write circuit, and the write circuit comprises: a first voltage follower circuit and a first voltage...  
WO/2021/053682A1
Compositions comprising a) one or more amorphous superconductor layers bound to one or more flexible substrate layers, or b) one or more superconductor layers bound to one or more layers of a high dielectric material are disclosed. Furth...  
WO/2021/055012A1
Techniques are described for programming memory cells without performing a verify test, where the programming is followed by a short circuit test. In one aspect, an initial programming is performed on memory cells of a first word line of...  
WO/2021/055209A1
A system having a string of memory chips that can implement flexible provisioning of a multi-tier memory. In some examples, the system can include a first memory chip in a string of memory chips of a memory, a second memory chip in the s...  
WO/2021/055113A1
An integrated circuit (IC) device includes a logic portion including logic circuits in multiple vertically stacked metal layers interconnected by one or more via layers, and a memory portion with a plurality of magnetoresistive devices. ...  
WO/2021/051742A1
Provided are a method and device for audio mixing, and a terminal apparatus. The method comprises: acquiring a current system volume parameter of a terminal apparatus; adjusting an audio mixing parameter for audio material according to t...  
WO/2021/051231A1
Disclosed is a new class of photo-responsive coordination compounds with at least one photochromic unit on a coordinating ligand. The photo-responsive coordination compounds are shown to be capable of acting as electroactive materials fo...  
WO/2021/054992A1
Numerous embodiments of a precision tuning algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplicatio...  
WO/2020/159628A3
A memory sub-system comprises a power management component comprising a plurality of regulators configured to supply respective operating voltages for components of the memory sub-system. The power management component is configured to a...  
WO/2021/053453A1
Provided is a semiconductor device that has reduced energy needs for data transfer between a calculation device and a memory. This semiconductor device has a peripheral circuit and a memory cell array. The peripheral circuit has a calcul...  
WO/2021/053537A1
A magnetic recording tape, in accordance with one approach, includes a substrate (604) comprising a poly ether ether ketone (PEEK). An underlayer (606) is positioned above the substrate (604). A recording layer (608) is positioned above ...  
WO/2021/051551A1
A memristor chip and an operation method therefor. The chip comprises a power supply management module (6), a decoding module, a memory module (1), a logic control module (4), a read/write module (5), and an I/O module (7); the read/writ...  
WO/2021/051651A1
Disclosed are a sense amplifier and a control method therefor, a memory read-write circuit and a memory. The sense amplifier comprises two PMOS transistors, two NMOS transistors, a first input/output end and a second input/output end, wh...  
WO/2021/055281A1
A computer system stores metadata that is used to identify physical memory devices that store randomly-accessible data for memory of the computer system. In one approach, access to memory in an address space is maintained by an operating...  
WO/2021/051487A1
An inverter, a GOA circuit and a display panel. The inverter comprises a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a first test transistor (T31), a second test transistor (T32) an...  
WO/2021/055721A1
Circuitry for an ultrasound device is described. The ultrasound device may include a symmetric switch positioned between a pulser and an ultrasound transducer. The pulser may produce bipolar pulses. The symmetric switch may selectively i...  
WO/2021/054898A1
Herein provided is a multilayered structure including one or more nanocrystalline layers each comprising a transition metal dichalcogenide, one or more substantially amorphous electrically insulating layers each comprising a transition m...  
WO/2021/055006A1
A memory device that includes a memory array having pluralities of non-volatile memory cells, a plurality of index memory cells each associated with a different one of the pluralities of the non-volatile memory cells, and a controller. T...  
WO/2021/051550A1
Disclosed in the present invention are an anti-overwrite circuit and method for a memristor. Said circuit comprises a signal control module configured to acquire a current of a write circuit of a memristor and generate a circuit turn-off...  
WO/2021/053455A1
A method for forming an MRAM device includes: forming MTJs (202) on interconnects (106) embedded in a first dielectric (102); depositing an encapsulation layer (204) over the MTJs (202); burying the MTJs (202) in a second dielectric (206...  
WO/2021/053423A1
Magnetic structures including magnetic inductors and magnetic tunnel junction (MTJ)-containing structures that have tapered sidewalls are formed without using an ion beam etch (IBE). The magnetic structures are formed by providing a mate...  
WO/2021/055675A1
Systems and methods are disclosed including a first memory component, a second memory component having a lower access latency than the first memory component and acting as a cache for the first memory component, and a processing device o...  
WO/2021/054243A1
This recording device is provided with: a derivation unit that, on the basis of condition information including the size of data items recorded in a recording medium, the size of metadata regarding each of the data items, and a expected ...  
WO/2021/051270A1
A GOA unit circuit is provided with an input sub-circuit configured to set a turn-on voltage to a first node and a turn-off voltage to a second node in response to an input signal and a first clock signal; a first pull-down sub-circuit, ...  
WO/2021/050428A1
A Dynamic Random Access (DRAM) memory device includes a plurality of DRAM cells arranged into rows and columns, a row select module, and a plurality of cell processing circuits. The cell processing circuit includes: a comparison circuit ...  
WO/2021/047591A1
Provided in the present application are a spin random access memory and a method. A second magnetic tunnel junction is provided in each storage partition, the second magnetic tunnel junction is kept in an anti-parallel state by means of ...  
WO/2021/047472A1
An error correction method and apparatus based on a NAND FLASH memory. The method comprises: when data is written, generating an original error correction code according to original data, and writing the original data and the original er...  
WO/2021/049777A1
A memory device according to the present invention may comprise: a memory cell array in which memory cells of a latch structure are connected in matrix form to word lines and bit line pairs composed of bit lines and inverted bit lines; a...  
WO/2021/050108A1
Embodiments of the present disclosure generally relate to a magnetic media drive employing a magnetic recording device. The magnetic recording device comprises a trailing gap disposed adjacent to a first surface of a main pole, a first s...  
WO/2021/047527A1
The present application provides a circuit structure for a PUF, a PUF data obtaining method, and an electronic device. The circuit structure comprises: a storage matrix which comprises a plurality of storage units, wherein a formation vo...  

Matches 51 - 100 out of 863,225