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Patent Searching and Data


Matches 51 - 100 out of 661,464

Document Document Title
WO/2022/093562A1
Techniques are described for identifying patterns of memory cells in a memory array that are predictive of non-correctable errors ("corruption patterns"). The techniques described herein identify patterns of cell errors that are likely t...  
WO/2022/090841A1
In various embodiments, enabling short video platform for creators, advertisers and users for producing contents from creators and publishing contents for users based on target criteria and making payments for producing and advertising c...  
WO/2022/093976A1
The disclosed technology is a system and computer-implemented method for assembling and editing a video program from spoken words or soundbites. The disclosed technology imports source audio/video clips and any of multiple formats. Spoke...  
WO/2022/094423A1
A processing device establishes a first data group of memory cells of a memory subsystem and a second data group of memory cells of the memory sub-system. A first portion of the first data group is programmed at a threshold voltage level...  
WO/2022/094038A1
An analog memory device includes a first node and a second node. The first node includes a first floating gate, a second floating gate, and a capacitor. The first node first floating gate is connected to the first node second floating ga...  
WO/2022/093557A1
A method includes monitoring a temperature of a memory component of a memory sub-system to determine that the temperature of the memory component corresponds to a first monitored temperature value; writing data to the memory component of...  
WO/2022/092583A1
Disclosed is a three-dimensional flash memory having a structure which includes an air gap, a method for manufacturing same, and a method for improving vertical hole defects in a three-dimensional flash memory. In order to form the air g...  
WO/2022/084782A1
Provided is a semiconductor device that has reduced power consumption and is capable of non-destructive readout. This semiconductor device has first to fourth transistors, and first and second ferroelectric tunnel junction (FTJ) elements...  
WO/2022/083146A1
A repair circuit and a memory, the repair circuit comprising: a plurality of redundant storage units, each redundant storage unit being configured with a status signal; and a repair module, which is separately connected to the plurality ...  
WO/2022/087024A1
A trace gimbal is described. The trace gimbal includes outer struts including a front outrigger at a distal end of the trace gimbal and a rear outrigger at a proximal end of the trace gimbal. The front outrigger includes a distal front o...  
WO/2022/082718A1
A three-dimensional memory including a substrate (310), a stack of alternating stack buffer layers (320) and stack conductor layers (330) formed on the substrate (310), and a channel formed in the stack and extending in a depth direction...  
WO/2022/084682A1
According to one implementation of the present disclosure, an integrated circuit includes a memory macro unit, and one or more through silicon vias (TSVs) at least partially coupled through the memory macro unit. According to one impleme...  
WO/2022/087196A1
In described examples, a sample and hold circuit (200) is configured to periodically connect one input (221) of an op-amp (220) to a reference voltage (CML) through a switch (204) while a second input (222) of the op-amp is connected to ...  
WO/2022/085036A1
A method and a system are provided, for sharing digital content on portable electronic devices (D) through a functionality (1), adapted to be executed by said devices (D) and activated by the user from the screen (S) for managing the cam...  
WO/2022/085470A1
This memory cell array unit according to one embodiment comprises a micro-controller which, on the basis of read/write control from a memory controller, performs reading/writing on a memory cell array by using n-bit allocated memory cell...  
WO/2022/082743A1
A new cell structure to implement 3D ferroelectric field effect transistor (FeFET) to enable 3D ferroelectric nonvolatile data storage is presented to increase data storage density and reduce memory bit cost. The 3D FeFET is a vertical g...  
WO/2022/086597A1
A memory cell includes an ovonic threshold switch (OTS) selector containing a first electrode, a second electrode, an OTS located between the first electrode and the second electrode, and a current focusing layer containing discrete elec...  
WO/2022/082732A1
A method for accessing memory cells of a three-dimensional memory comprising a plurality of bottom cell blocks, a plurality of top cell blocks, a plurality of bottom cell bit lines coupled to the bottom cell blocks, a plurality of top ce...  
WO/2022/084800A1
Provided is a semiconductor device capable of reading data with high accuracy. This semiconductor device has first and second memory cells and a switch. The first memory cell has first and second transistors and a first capacitor, and th...  
WO/2022/082796A1
A memory and a data migration method, which relate to the field of storage, and can shorten the time for implementing data migration between adjacent memory cell subarrays during in-memory computing in a DRAM, thereby reducing the power ...  
WO/2022/087181A1
Methods and apparatus for memory operations disclosed. In an embodiment, a method is provided for programming multiple-level-cells. The method includes programming data to single-level-cells (SLC) on SLC word lines using SLC programming ...  
WO/2022/084779A1
A device includes at least one tunable resistive element. Each tunable resistive element comprises a first terminal, a second terminal, and a dielectric layer arranged between the first and second terminals. The device is configured to a...  
WO/2022/084785A1
The present invention read data in a memory cell having a ferroelectric capacitor without destroying the data. During a reading operation for a memory cell having the ferroelectric capacitor, a readout operation is performed so that the ...  
WO/2022/083633A1
A memory reading method. A memory comprises a plurality of word lines and a plurality of multi-bit storage units, which are connected to the plurality of word lines, wherein the multi-bit storage units are used for reading storage values...  
WO/2022/082750A1
A three-dimensional memory architecture including a top cell array of memory cells, a bottom cell array of memory cells, a plurality of word lines coupled to the arrays, and a plurality of word line decoders coupled to the word lines and...  
WO/2022/086703A1
A flash memory cell of a flash memory device is illuminated with light during programming and/or erasing. The wavelength of the light is selected such that the photons impinging on the flash memory cell have an energy that approaches the...  
WO/2022/082703A1
Provided are a display panel (1) and a display apparatus, the display panel (1) comprising: a plurality of rows of subpixels (P) arranged on a base substrate and located in a display region (10), each subpixel (P) comprising a pixel driv...  
WO/2022/083137A1
A word line (WL) drive circuit and a dynamic random access memory. The WL drive circuit comprises a first transistor (N1), a second transistor (N2), a third transistor (N3), and a fourth transistor (P1). A gate of the first transistor (N...  
WO/2022/087307A1
An example deformable mirror includes a number of cells defining an aperture plane of the mirror. Each of the cells includes a first transparent electrode layer and a second reflective electrode layer, with a solid crystal electro-optica...  
WO/2022/086559A1
An electronic device is described that may include an integrated circuit, a volatile memory coupled to the integrated circuit, a non-volatile memory controller coupled to the integrated circuit, and a non-volatile memory coupled to the n...  
WO/2022/084802A1
Provided is a novel semiconductor device. A semiconductor device having a memory cell that includes a transistor and a capacitance element including a ferroelectric body, a word line, a bit line, and a plate line, the gate of the transis...  
WO/2022/087142A1
Techniques for refreshing memory cells of a stack of random-access memory are provided. In an example, a method can include exchanging data between a host processor and a buffer die at a first data speed, exchanging data between the buff...  
WO/2022/085218A1
This method for constructing a database, in which there is used an information processing device that includes a memory and a processor that executes a first program, comprises first to third steps. In the first step, one bit of data in ...  
WO/2022/086641A1
An OTP memory cell circuit includes a read access switch coupled to a fuse in a read current path to allow a read current to flow through the fuse during a read operation. The read access switch, which can be shut off in a write operatio...  
WO/2022/085471A1
A memory cell array unit according to one embodiment of the present disclosure comprises a memory cell array and a microcontroller. The memory cell array is configured by including: n assignment bits to be assigned from the memory contro...  
WO/2022/085472A1
A hard disk drive (1) with a built-in thin substrate pertaining to the present invention comprises: a disc-shaped magnetic disk (30) having a through-hole at the center; a spindle motor (20) inserted in the through-hole of the magnetic d...  
WO/2022/077943A1
A data writing method and a memory. The data writing method is used for writing data into a storage array of a memory and the data writing method comprises: reading old data from target columns in the storage array; updating the old data...  
WO/2022/079089A1
A data storage apparatus comprises an integrated circuit further comprising a control unit (100) and a memory array (400) of charge-based memory cells. The memory array (400) comprises a first subsection (410) which is operable as a memo...  
WO/2022/077499A1
Embodiments of the present application relate to the technical field of memories, and provide a memory and an electronic device, which can solve the problems of heavy current required for free layer reversal in a magnetic tunnel junction...  
WO/2022/080774A1
The present invention relates to a speech disorder assessment device, and comprises: a communication unit which receives recording data including an utterance voice recorded while performing at least one utterance task by a person subjec...  
WO/2022/080202A1
An optical disk device (2) comprises: an optical pickup (4) which includes a first laser beam source (10) that emits a laser beam, an objective lens (24) that converges, onto an optical disk (8), the laser beam emitted from the first las...  
WO/2022/079870A1
Provided is an in-vehicle device that can prevent the occurrence of distortion in an information display surface of a display device. This in-vehicle device (1) comprises a display device (101), a main body device (102), and a support pl...  
WO/2022/077971A1
A memory test method, comprising: determining a refresh period T, a designed attack defense frequency F and a single-row read time t of a target repository (S1); determining the number N of attack rows according to the refresh period T, ...  
WO/2022/077979A1
Provided are a parasitic capacitance measurement method, a memory and a readable storage medium, which relate to the technical field of semiconductors. The measurement method comprises: providing a plurality of semiconductor devices for ...  
WO/2022/077147A1
A 3D crosspoint memory is bonded to a central processing unit chip. Faster data processing and transferring with higher efficiency is achieved by introduction of 3D crosspoint into both VM and NVM systems. There is direct bonding of the ...  
WO/2022/081559A1
Provided herein are systems and methods for performing dynamic adaption and correction for internal delays in devices (130, 150) connected to a common time-multiplexed bus (120). The methods allow devices (130, 150) to operate reliably a...  
WO/2022/080964A1
According to various embodiments, an electronic device comprises a wireless communication module, a memory, and a processor, wherein the memory may include instructions that cause the processor to: be connected to a wireless audio input/...  
WO/2022/079463A1
Methods, systems, and devices related to 3D self- selecting-memory array of memory cells are described. The method relates to a solution for improving the fault-tolerant capability of memory devices, comprising: applying a triple-modular...  
WO/2022/076423A1
An ultrafast non-volatile memory cell for wafer-scale integration includes a voltage divider that outputs an output voltage. The voltage divider includes a reference resistive device that is a reference magnetic tunnel junction or anothe...  
WO/2022/074968A1
In the present invention, a memory cell includes first and second transistors. A driving circuit includes: a boost circuit configured to generate a boosted voltage on a boost line by boosting a prescribed reference voltage; and an adjust...  

Matches 51 - 100 out of 661,464