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WO/2024/065889A1 |
Embodiments of the present invention relate to the technical field of semiconductors, and provide a semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises: a substrate and a magnetic tunnel jun...
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WO/2024/066521A1 |
The embodiments of the present application relate to the technical field of computers. Disclosed are a memory refresh method and apparatus, which can reduce the power consumption of a memory. The method comprises: acquiring target inform...
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WO/2024/066190A1 |
A display apparatus, a gate drive circuit, and a shift register unit and a drive method therefor. The shift register unit comprises an input sub-circuit (1), a first control sub-circuit (2), a second control sub-circuit (3), a third cont...
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WO/2024/069769A1 |
The present disclosure provides a computation device equipped with a first signal line, a first capacitor which is connected to the first signal line, one or more sub-arrays which are connected to the first signal line, and a readout cir...
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WO/2024/065658A1 |
A gate driving circuit and a driving method therefor, and a display panel and a display apparatus. A gate driving circuit (10) comprises M groups of shift register units, wherein each group of shift register units comprises a first shift...
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WO/2024/072971A1 |
A memory system includes a PHY embodied on an integrated circuit, the PHY coupling to a memory over conductive traces on a substrate. The PHY includes a reference clock generation circuit providing a reference clock signal to the memory,...
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WO/2024/072497A1 |
A non-volatile memory system comprises a plurality of non-volatile memory cells divided into three or more tiers. The memory cells can be programmed, erased and read. In order to achieve uniform erase speed for the three or more tiers, t...
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WO/2024/065909A1 |
The present disclosure relates to the field of semiconductors, and in particular, to an anti-fuse circuit, structure, array, programming method and memory. The anti-fuse circuit comprises: an anti-fuse, a select transistor and a clamping...
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WO/2024/073231A1 |
Systems, apparatuses, and methods for prefetching data by a display controller are proposed. From time to time, a performance-state change of a memory is performed. During such changes, a memory clock frequency is changed for a memory su...
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WO/2024/072981A1 |
A memory controller includes a first arbiter for selecting memory commands for dispatch to a memory over a first channel, a second arbiter for selecting memory commands for dispatch to the memory over a second channel, and a test circuit...
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WO/2024/066383A1 |
The embodiments of the present application relate to the field of storage device applications, and disclose a flash memory management method and a flash memory device; the flash memory management method involves: obtaining a logic word l...
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WO/2024/064239A1 |
In some implementations, at least a partial view of a jog wheel user interface (UI) element is displayed on a graphical user interface (GUI). The jog wheel UI element is operable to manipulate one or more secondary elements. In response ...
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WO/2024/064010A1 |
Methods and devices for reading and programming a state of a switch device are presented. The programming of the state of the switch device is performed by providing driving pulses to the switch device. The amplitude and the width of the...
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WO/2024/060405A1 |
A dynamic random access memory test method and device, relating to the technical field of memories. A dynamic random access memory comprises a base substrate (402) and a plurality of memory cells (3062, 3064); each memory cell (3062, 306...
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WO/2024/060367A1 |
The embodiments of the present disclosure provide a memory and a storage system. The memory comprises: a substrate; a control circuit layer, which is located in the substrate, wherein the control circuit layer comprises at least part of ...
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WO/2024/063822A1 |
The present disclosure generally relates partial speed changes to improve in-order data transfer. Rather than determining an ECC decoder on a first available decoder basis, the ECC decoder may be based on the ECC decoder level. A memory ...
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WO/2024/062252A1 |
A motor for a turntable, comprising: a stator comprising a plurality of conductive coils, the conductive coils comprising a plurality of coil windings; and a rotor comprising a plurality of permanent magnets, wherein: the stator and the ...
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WO/2024/064075A1 |
Methods, systems, and media for providing automated assistance during a video recording session are provided. In some embodiments, the method comprises: receiving, at a first user device, user input to initiate a video recording session,...
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WO/2024/063794A1 |
Numerous examples are disclosed of programming multiple rows in an array in an artificial neural network as part of a single programming operation. In one example, a method comprises ramping up an output of a high voltage generator to a ...
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WO/2024/060315A1 |
Provided in the present disclosure are a built-in self-test method, a built-in self-test apparatus and a semiconductor memory. The method comprises: acquiring temperature data of a storage unit, and according to the temperature data, adj...
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WO/2024/060059A1 |
A memory device includes a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines, and a charge control circuit coupled to the memory cell array. The plurality of ...
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WO/2024/060611A1 |
A method of realizing a content-addressable memory (CAM) based on field effect transistors having bipolar characteristics. By inserting a storage layer between a gate dielectric layer and a control gate of a field effect transistor havin...
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WO/2024/063793A1 |
Numerous examples are disclosed of input circuitry and associated methods in an artificial neural network. In one example, a system comprises a plurality of address decoders to receive an address and output a plurality of row enabling si...
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WO/2024/060323A1 |
Embodiments of the present disclosure provide a counting circuit, a semiconductor memory, and a counting method. The counting circuit comprises a first decoding module and a first counting module, and the first decoding module is connect...
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WO/2024/060365A1 |
Provided in the embodiments of the present disclosure are a word-line driver, and a storage apparatus. The word-line driver comprises: a first holding transistor and a second holding transistor; an active area, comprising a main body por...
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WO/2024/063792A1 |
Numerous examples are disclosed of verification circuitry and associated methods in an artificial neural network. In one example, a system comprises a vector-by-matrix multiplication array comprising a plurality of non-volatile memory ce...
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WO/2024/060317A1 |
Embodiments of the present disclosure provide a command decoding circuit and a method thereof, and a semiconductor memory. The command decoding circuit comprises: a clock processing module, which is configured to receive an initial clock...
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WO/2024/060378A1 |
The present disclosure relates to the technical field of memories. Provided are a dynamic random access memory test method and apparatus. A dynamic random access memory comprises a substrate and a plurality of storage units, wherein each...
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WO/2024/060316A1 |
A built-in self-test method and device. The built-in self-test method comprises: acquiring a first initial address of a storage region (110) of data to be written, and masking at least one bit address of the first initial address, so as ...
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WO/2024/061005A1 |
A read processing method and apparatus for an audio and video buffer. The data read-write mode of the audio and video buffer is improved. Consumer modules create respective handles for reading data. Using a read handle as a unique identi...
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WO/2024/062978A1 |
A magnetoresistive element according to one embodiment of the present disclosure comprises a multilayer structure, a memory layer disposed on the multilayer structure and changeable in magnetization direction, a nonmagnetic layer dispose...
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WO/2024/063315A1 |
Disclosed is a three-dimensional memory having a dual junction structure. According to an embodiment, the three-dimensional memory may comprise: gate electrodes spaced apart and stacked in a vertical direction while extending in the hori...
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WO/2024/062539A1 |
This memory device, in which in a plan view on a substrate, a page is formed by a plurality of memory cells arranged in the row direction and a plurality of the pages are arranged in the column direction, is characterized in that: the me...
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WO/2024/060478A1 |
The embodiments of the present disclosure disclose a data sampling circuit, a delay detection circuit and a memory. The data sampling circuit comprises a first signal path and a second signal path. The first signal path is configured to ...
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WO/2024/060325A1 |
A decoding circuit (10), a decoding method and a semiconductor memory. The decoding circuit (10) comprises a decoding module (11) and a register module (12). The decoding module (11) is configured to perform decoding processing on an ini...
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WO/2024/060219A1 |
In certain aspects, a method for forming a three-dimensional (3D) memory device is disclosed. A stack structure including interleaved first dielectric layers and second dielectric layers is formed. Channel structures extending through th...
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WO/2024/060555A1 |
The application discloses a chip test method and apparatus, a chip and a computer readable storage medium. The method comprises: a main controller sends a test instruction to each sub-controller in a storage built-in self-test circuit; a...
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WO/2024/058321A1 |
The present invention relates to a memory device including memory cells in which data is stored by the operation of word lines and bit lines, the memory device comprising: a first switch which has one end connected to a bit line connecte...
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WO/2024/055358A1 |
A data processing method, an electronic device, and a computer readable storage apparatus. The method comprises: determining a target layer corresponding to a target storage unit; and operating a storage unit in a non-target layer to imp...
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WO/2024/055832A1 |
Provided in the present disclosure are a non-volatile memory and an erasing method therefor, and a computer system. The non-volatile memory comprises a first area, which needs to be erased, and a second area, which does not need to be er...
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WO/2024/059428A1 |
A device includes a memory configured to store data corresponding to a media stream including video recorded at a first frame rate and multiple audio segments includes the multiple audio segments include one or more first audio segments ...
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WO/2024/058909A1 |
Technology is disclosed for programmatically determining, for a segment of a meeting recording, a user-specific adaptive playback speed, and generating a time-stretched segment playable at the adaptive playback speed. The adaptive playba...
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WO/2024/055685A1 |
The present application relates to the technical field of semiconductor chips, and provides a ferroelectric memory, a three-dimensional integrated circuit, and an electronic device, which improve the anti-interference capability of capac...
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WO/2024/055611A1 |
The present application relates to the technical field of firmware emulation, and in particular to a fault site backtracking method based on firmware emulation, and a device and a readable storage medium. The method comprises: upon recei...
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WO/2024/055484A1 |
The embodiments of the present disclosure provide a programmable storage array, a programming method and a semiconductor memory. The programmable storage array comprises a plurality of storage units. Each storage unit comprises a first t...
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WO/2024/057519A1 |
In the present invention, a first string includes a first memory cell transistor, one end of the first string being connected to a first wire, the other end being connected to a second wire. A second string includes a second memory cell ...
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WO/2024/057114A1 |
A 3D compute-in-memory accelerator system (100) and method for efficient inference of Mixture of Expert (MoE) neural network models. The system includes a plurality of compute-in-memory cores (102), each in-memory core including multiple...
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WO/2024/055373A1 |
Embodiments of the present disclosure relate to the technical field of semiconductors, and provide a voltage regulating circuit and a memory thereof. The voltage regulating circuit comprises: a reference voltage generation module, config...
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WO/2024/057947A1 |
Provided are a magnetic recording medium and a magnetic recording cartridge. An average thickness of the magnetic recording medium tT is tT ≦ 5.3 μm, and a width of the magnetic recording medium is stabilized in 24 minutes or less a t...
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WO/2024/055655A1 |
Disclosed in the present invention is a memory read-write verification method, comprising: firstly, performing margin verification on all IOs of a memory according to input data, and according to a verification result, acquiring read-out...
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