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Patent Searching and Data


Matches 101 - 150 out of 863,225

Document Document Title
WO/2021/050114A1
A three-dimensional ferroelectric memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, where each of the electrically conductive layers contains a transition metal ...  
WO/2021/050984A1
Circuits and methods are disclosed for voltage-mode bit line precharge for random-access memory cells. A circuit includes an array of random access memory cells; a low-impedance voltage source configured to provide a precharge voltage; a...  
WO/2021/051017A1
A playback application is configured to analyze audio frames associated with transitions between segments within a media title to identify one or more portions of extraneous audio. The playback application is configured to analyze the on...  
WO/2021/050902A1
A computerized method is provided that enables an interactive multimedia session between a group of geographically distributed musicians. The method includes song arrangements for the interactive multimedia session being specified as a s...  
WO/2021/046756A1
A two-dimensional bosk constraint-based encoding and decoding method and device, relating to the field of data storage and data communication. The encoding method comprises: caching one-dimensional data stream, and dividing the one-dimen...  
WO/2021/047577A1
The present application provides a spin random access memory and a method. A second magnetic tunnel junction is arranged in each storage partition, and the second magnetic tunnel junction maintains an anti-parallel state by means of curr...  
WO/2021/050020A1
The present invention relates to a dynamic random access memory structure (1), which enables to apply bias voltages in adaptive manner to the access transistors (211) of the cells (21) in dynamic random access memory structures depending...  
WO/2021/050113A1
An apparatus comprising strings of non-volatile memory cells is disclosed. Each string comprises non-volatile memory cells, an operative select gate, and a dummy select gate. The apparatus comprises a select line connected to the operati...  
WO/2021/045795A1
A method for providing error correction for a memory array includes for each memory word stored in a data memory portion of the memory array (12) having at least one bit error, storing in an error PROM (24) error data identifying a memor...  
WO/2021/045474A1
Disclosed are a method and system for playing back streaming content. A method for playing back streaming content according to an embodiment may include: a step in which a streaming player client sets an initial bitrate for a player modu...  
WO/2021/042264A1
A non-volatile memory device includes a plurality of memory blocks grouped into pages, page buffer regions corresponding to the pages of the plurality of memory blocks; and a peripheral circuit region for supporting operations of the pag...  
WO/2021/045799A1
A method of improving stability of a memory device having a controller configured to program each of a plurality of non-volatile memory cells within a range of programming states bounded by a minimum program state and a maximum program s...  
WO/2021/045860A1
Methods, apparatuses, and systems for staggering refresh operations to memory arrays in different dies of a three-dimensional stacked (3DS) memory device are described. A 3DS memory device may include one die or layer of that controls or...  
WO/2021/042873A1
A gate driving circuit. The gate driving circuit comprises: an input sub-circuit (110) configured to convert the potential of a first node (N1) from a first level to a second level under the control of a first input signal (SIN1); an out...  
WO/2021/046568A1
Methods, apparatuses, and systems for in-or near-memory processing are described. Strings of bits (e.g., vectors) may be fetched and processed in logic of a memory device without involving a separate processing unit. Operations (e.g., ar...  
WO/2021/045934A1
A memory device that includes a plurality of non-volatile memory cells and a controller. The controller is configured to erase the plurality of memory cells, program each of the memory cells, and for each of the memory cells, measure a t...  
WO/2021/042364A1
Provided in the present application are a method and device for taking a picture. The method comprises: determining a first snap photography mode among multiple preset snap photography modes on the basis of multiple captured pictures; an...  
WO/2021/046566A1
Systems, apparatuses, and methods of operating memory systems are described. Processing-in-memory capable memory devices are also described, and methods of performing fused-multiply-add operations within the same. Bit positions of bits s...  
WO/2021/045816A1
Redundancy information can be included in nucleotide symbol strings encoding underlying data. To avoid propagation of errors during the decoding process, during encoding, a constrained encoding can be performed before the redundancy info...  
WO/2021/045619A1
Method for testing an integrated circuit device (1), by defect modelling of the integrated circuit device (1), fault modelling of the integrated circuit device (1) based on the information obtained from the defect modelling, test develop...  
WO/2021/044822A1
A semiconductor circuit according to the present disclosure comprises: a first circuit capable of applying a turnover voltage of a voltage at a first node to a second node; a second circuit capable of applying a turnover voltage of a vol...  
WO/2021/046000A1
Methods, apparatuses, and systems for in-or near-memory processing are described. Spiking events in a spiking neural network may be processed via a memory system. A memory system may store data corresponding to a group of destination neu...  
WO/2021/045933A1
A memory device having non-volatile memory cells and a controller. In response to a first command for erasing and programming a first group of the memory cells, the controller determines the first group can be programmed within substanti...  
WO/2021/039215A1
It is an object of the present disclosure to provide a memory chip capable of detecting disturb defects, and a control method of the memory chip. The memory chip is provided with: a memory cell having a variable-resistance element capabl...  
WO/2021/041752A1
A semiconductor memory device designed to mitigate degradation due to heat, and methods of forming such a device, are described. In one example, a memory cell in a memory device includes an insulating layer formed over a substrate, a hor...  
WO/2020/247509A3
A dual-mode memory is provided that includes a self-timed clock circuit for asserting a sense enable signal for a sense amplifier. In a low-bandwidth read mode, the self-timed clock circuit asserts the sense enable signal only once durin...  
WO/2021/041084A1
Methods, systems, and devices for error correction for content-addressable memory (CAM) are described. A CAM may store bit vectors as a set of subvectors, which each subvector stored in an independent aspect of the CAM, such as in a sepa...  
WO/2021/040891A1
Apparatuses and methods for implementing artificial synapses utilizing SSM cells. A leaky-integrate-and-fire circuit can provide a feedback signal to an SSM cell responsive to a threshold quantity of pulses being applied to the gate from...  
WO/2021/036104A1
The present disclosure relates to the technical field of storage. Provided is a sense amplifier. The sense amplifier comprises: a first phase inverter, a second phase inverter, a first switch unit, a second switch unit, a third switch un...  
WO/2021/041630A1
The present disclosure includes apparatuses and methods related to defining activation functions for artificial intelligence (AI) operations. An example apparatus can include a number of memory arrays and a controller, wherein the contro...  
WO/2021/040822A1
Some embodiments include an integrated assembly having a base comprising sense-amplifier-circuitry, a first deck over the base, and a second deck over the first deck. The first deck includes a first portion of a first array of first memo...  
WO/2021/041390A1
Devices and methods related to spiking neural units in memory. One device includes a memory array and a complementary metal-oxide semiconductor (CMOS) coupled to the memory array and located under the memory array, wherein the CMOS inclu...  
WO/2021/040805A1
A memory system is provided with technology for performing temperature dependent impedance mitigation, in addition to or instead of other techniques to compensate for differences in impedance. For example, the memory system comprises a p...  
WO/2021/041563A1
Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a conductive region, a first data line, a second data line, a first memory cell coupled to the first data line and the conductiv...  
WO/2021/040883A1
Latch circuitry (13) configured to latch data for use in the memory device (10). The latch circuitry (13) includes latch cells (52) each configured to store a bit of the data. The latch circuitry (13) also includes a data line (72) coupl...  
WO/2021/040154A1
A current memory device according to an embodiment of the present invention comprises: a first current mirror circuit which uses a plurality of N-type MOSs and which is formed as a cascode circuit; a second current mirror circuit which u...  
WO/2021/041567A1
Some embodiments include apparatuses and methods using a substrate, a pillar having a length perpendicular to the substrate, a first conductive plate, a second conductive plate, a memory cell located between the first and second conducti...  
WO/2021/035436A1
A memory device and method of operation are described. The memory device may include memory cells of a first type that each store a single bit of information and memory cells of a second type that each store multiple bits of information....  
WO/2021/041109A1
Apparatuses and methods can be related to performing operations in memory. Operations can be performed in the background while the memory is performing different operations. For example, comparison operations can be performed by the memo...  
WO/2021/037021A1
Proposed by the present invention are a shift register and a driving method therefor, a gate driving circuit, and a display panel. The shift register comprises: a display control circuit, which is separately connected to a pull-up node, ...  
WO/2021/041019A1
Methods of operating a die might include determining an expected peak current magnitude of the die for a period of time, and outputting the expected peak current magnitude from the die prior to completion of the period of time. Apparatus...  
WO/2021/040964A1
Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a host device may directly access a portion of memory array that is otherwise reserved for ECC functionality of a memory de...  
WO/2021/035803A1
A dynamic dangerous block screening method for an NAND Flash. All readable voltages are used for a page in a block that is subjected to ECC Fail under a default voltage, and whether there is a voltage capable of reducing an Error Bit of ...  
WO/2021/041587A1
The present disclosure includes apparatuses and methods related to memory with an artificial intelligence (AI) accelerator. An example apparatus can include receive a command indicating that the apparatus operate in an artificial intelli...  
WO/2021/041003A1
Methods, systems, and devices for architecture-based power management for a memory device are described. Aspects include operating a first memory bank within a memory device in a first mode and a second memory bank within the memory devi...  
WO/2021/036094A1
A chip (300) and an electronic apparatus. The chip (300) comprises a storage module, pins (302), a control module (303), first connecting lines (306, 307) and second connecting lines (304, 305). The storage module comprises a first stora...  
WO/2021/038086A1
Methods, systems, and computer-readable storage media are provided for automatically generating customizable advertisements based on user preferred musical selection. In some aspects, a process can include steps for receiving a first vid...  
WO/2021/041054A1
A random number generator selects addresses while a 'scoreboard' bank of registers (or bits) tracks which addresses have already been output (e.g., for storing or retrieval of a portion of the data.) When the scoreboard detects an addres...  
WO/2021/041041A1
The memory banks of a memory device are arranged and operated in groups and the groups are further arranged and operated as clusters of these groups. Successive accesses to banks that are within different bank group clusters may be issue...  
WO/2021/041526A1
Certain aspects of the present disclosure are directed to methods and apparatus for programming a device having one or more programmable circuits to implement, for example, a machine learning model. One example apparatus generally includ...  

Matches 101 - 150 out of 863,225