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WO/2023/137845A1 |
A test method for a storage chip, a test apparatus for a storage chip, and a computer readable storage medium and an electronic device, which belong to the technical field of semiconductors. The method comprises: on the basis of a target...
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WO/2023/141013A1 |
An example device (100) includes: converter circuitry (104 A) having an output configured to couple to a first memory circuit (106 A) from a plurality of memory circuits (106A, 106B, 106C), the converter circuitry (104 A) configured to: ...
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WO/2023/137855A1 |
Embodiments of the present application provide a test method for a memory chip and a device. The method comprises: writing test data into memory cells of a memory chip to be tested; reading stored data from the memory cells; and generati...
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WO/2023/141389A1 |
he present disclosure provides systems, apparatus, methods, and computerreadable media that support linking paused video recordings captured over a period of time. In a first aspect, a method of image processing may include determining a...
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WO/2023/138850A1 |
A magnetic recording tape comprises a tape substrate, a perpendicular magnetic recording layer disposed over the tape substrate, and a soft-magnetic underlayer disposed between the recording layer and the tape substrate. The perpendicula...
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WO/2023/134002A1 |
A memory detection method and apparatus, and a detection simulation method. The method comprises: writing, by means of a sense amplifier, first data to a storage unit to be detected; writing second data different from the first data into...
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WO/2023/133992A1 |
The present invention relates to the field of semiconductor circuit design, and in particular to a refresh circuit and a memory. The refresh circuit comprises: a preprocessing module (101) for receiving a word line enabling command and a...
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WO/2023/134001A1 |
Embodiments of the present disclosure provide a clock circuit, a clock alignment system and a clock alignment method. The clock circuit comprises a signal receiving end, an equalization circuit and an analog test circuit. The signal rece...
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WO/2023/133753A1 |
Provided in the present disclosure are a driving circuit, a driving method and a display apparatus. The driving circuit comprises scanning driving circuits at a plurality of stages and pixel driving circuit in a plurality of rows, wherei...
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WO/2023/136242A1 |
Provided are a magnetic disk substrate having a pair of front and back main surfaces, wherein each of the front and back main surfaces has a fixing site which is brought into contact with a fixing jig when the magnetic disk substrate mad...
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WO/2023/134009A1 |
The present disclosure provides a readout circuit architecture and a sense amplification circuit, comprising: a readout amplification unit, comprising a first P-type transistor and a second P-type transistor; a first offset compensation ...
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WO/2023/134297A1 |
A peripheral circuit of a memory device is configured to: in the process of programming a first physical page, perform a programming verification to a programming corresponding to the 2 (N-M) th memory state; when the program verificatio...
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WO/2023/133975A1 |
A readout circuit layout, comprising: a first PMOS layout used for forming a first PMOS tube , a source of the first PMOS tube being connected to a first signal end, and the first signal end being used for receiving a first level signal;...
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WO/2023/133877A1 |
A method of data protection for a NAND memory includes programming first and second pages of a NAND flash memory device according to programming data such that data stored in the first and second pages are redundant. The programming of t...
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WO/2023/134138A1 |
A sensitivity amplifier and a driving method therefor, and a memory. The sensitivity amplifier comprises an amplification circuit and a voltage equalization circuit, wherein the amplification circuit comprises a first P-type transistor, ...
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WO/2023/135739A1 |
According to an embodiment of the present invention, a semiconductor storage device comprises: a non-volatile memory cell; a sensing circuit that senses a first voltage and selects one of a first mode and a second mode on the basis of th...
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WO/2023/134005A1 |
Disclosed in embodiments of the present disclosure are a semiconductor structure and a forming method therefor. The semiconductor structure comprises: a substrate; an integrated circuit device layer, the integrated circuit device layer b...
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WO/2023/134299A1 |
A peripheral circuit of a memory device includes page buffers. Each page buffer includes a main latch, a bias latch, (N-1) data latches, and a cache latch coupled to a data path. The peripheral circuit is further configured to: in the pr...
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WO/2023/133967A1 |
Provided is an antifuse memory; an inverting input end of an operational amplifier is connected to a feedback end of a bias voltage generation module; a voltage of a second input end can be obtained according to a voltage of the feedback...
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WO/2023/136925A1 |
Latch array with mask-write functionality including: a first set of master latches including a first set of clock inputs configured to receive a master clock, a first set of data inputs configured to receive a first set of data, and a fi...
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WO/2023/133973A1 |
The present disclosure relates to the field of semiconductor circuit design, and in particular to a local amplification circuit, a data readout method, and a memory. The local amplification circuit comprises: a write control transistor (...
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WO/2023/134023A1 |
Embodiments of the present disclosure provide an inductive amplifier circuit, a method, and a semiconductor memory. The inductive amplifier circuit comprises: a transmission circuit for receiving a signal to be processed, performing tran...
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WO/2023/133776A1 |
Embodiments of the present application provide a magnetic storage unit, a memory, and a manufacturing method. The magnetic storage unit comprises: an electrode layer; a magnetic tunnel junction disposed on the electrode layer, the magnet...
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WO/2023/133974A1 |
The present invention relates to the field of semiconductor circuit design, and in particular to a local amplification circuit, a data read-out method, and a memory. The local amplification circuit comprises: write control transistors (1...
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WO/2023/135019A1 |
The invention relates to a magneto resistive memory de device (100) comprising a memory array (10) comprising at least one bit line (BL) and at least one source line (SL, SLB), the bit line (BL) and the at least one source line (SL, SLB)...
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WO/2023/133952A1 |
The present disclosure provides a memory structure and a storage system. The memory structure has an array structure, comprising: a storage controller and a plurality of memories; at least one storage redistribution layer is provided on ...
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WO/2023/136853A1 |
A data storage device has a closed loop extended park mode during spin down operation. A data storage device comprises a spindle motor configured to rotate one or more disks, and one or more processing devices. The one or more processing...
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WO/2023/133774A1 |
Embodiments of the present application provide a magnetic memory cell and a manufacturing method therefor. The magnetic memory cell comprises a magnetic tunnel junction and an electrode layer. The magnetic tunnel junction comprises a fre...
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WO/2023/130578A1 |
A testing method and a testing apparatus for a memory. The method comprises: after at least one word line is activated, executing a reading operation at least twice on a memory unit to be tested, said memory unit being connected to the a...
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WO/2023/130487A1 |
Provided in at least one embodiment of the present disclosure are a data processing method based on a memristor array, and an electronic apparatus. The data processing method based on a memristor array comprises: acquiring a plurality of...
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WO/2023/132855A1 |
A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to store a plurality of codewords in the memory device. Each codeword of the plurality of codewords includes host ...
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WO/2023/130582A1 |
Provided in the present disclosure is a data extraction circuit. The data extraction circuit comprises: a first input circuit, wherein an input end of the first input circuit establishes first input data under the triggering of a first d...
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WO/2023/132857A1 |
A data storage device and method for memory-die-state-aware host command submission are provided. In one embodiment, a data storage device comprises a memory comprising a plurality of memory dies and a controller. The controller is confi...
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WO/2023/133237A1 |
A video is generated from an audio file by transcribing the audio file into texts and breaking the audio file into one or more segments or shots used as scenes. A media piece is then matched to each shot; the media pieces are properly co...
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WO/2023/131864A1 |
A method (700) for real-time audio/video synchronization, comprising steps of: uploading (701), by a central electronic computer, a video content received by means of a user interface provided by the central electronic computer usable on...
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WO/2023/132653A1 |
Various embodiments herein provide a method for managing an audio based on a spectrogram. The method includes generating, by a transmitter device, the spectrogram of the audio. The method includes identifying a first spectrogram correspo...
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WO/2023/133114A1 |
An apparatus and method including a command input to receive a command with a macro identifier from a channel processor, a macro memory storing a plurality of flash control commands, each comprising a corresponding duration and a corresp...
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WO/2023/133600A1 |
In some embodiments, a computer system displays a caption for a media item at different depths depending on the depth of the portion of the media item over which the caption is displayed. In some embodiments, a computer system displays a...
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WO/2023/124002A1 |
Provided are a Linux-based audio control method and apparatus, a device, and a storage medium. The method comprises: receiving an audio control instruction sent by an application program in a Linux system by means of a Linux audio servic...
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WO/2023/123667A1 |
Provided in the embodiments of the present disclosure are a control amplification circuit, a sense amplifier and a semiconductor memory. The control amplification circuit comprises: a power consumption control circuit used for receiving ...
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WO/2023/124096A1 |
A memory and a read circuit thereof. The memory comprises a plurality of storage arrays. Each storage array comprises a first array and a second array symmetrical to the structure of the first array. The read circuit of the memory compri...
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WO/2023/123666A1 |
A control amplification method and circuit, a sensitive amplifier and a semiconductor memory. The method comprises: receiving a preset instruction, and determining an isolation power value and a control instruction signal according to th...
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WO/2023/129197A1 |
Various embodiments are directed to frequency and voltage tuning for systems with multiple application-specific integrated circuits (ASICs) and disclosed herein may be applied to multi-AIC systems in a variety of applications, such as hi...
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WO/2023/129432A1 |
A system and method for efficiently resetting data stored in a memory array are described. In various implementations, an integrated circuit includes a memory for storing data, and a processing unit that generates access requests for the...
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WO/2023/123649A1 |
The embodiments of the present disclosure relate to the technical field of semiconductors. Provided are an integrated circuit structure, a memory and an integrated circuit layout. The integrated circuit structure comprises: a data pad; a...
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WO/2023/123158A1 |
Provided are an apparatus and method for testing solid state drives. The apparatus comprises: a test board, which comprises test ports; a first positioning portion, which is arranged on the test board; and an adapter box, which comprises...
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WO/2023/126111A1 |
A controller of a non-volatile memory detects errors in data read from a particular physical page of the non-volatile memory. Based on detecting the errors, the controller performs a read voltage threshold calibration for a page group in...
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WO/2023/123796A1 |
The present application discloses a method for adjusting the phase of a bidirectional data strobe (DQS) signal, which is applied to the field of field-programmable gate arrays and is used for solving the problem of temperature drift of D...
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WO/2023/126385A1 |
The invention relates to a tunnel junction (12) having a stack formed by a barrier (18) and two electrodes (14, 16), the barrier (18) comprising a layer made of a ferroelectric material, referred to as the ferroelectric layer, the ferroe...
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WO/2023/125446A1 |
A DRAM refresh circuit and refresh method, and a proof-of-work chip. The DRAM refresh circuit comprises a row address recording unit, which is configured to record a row that has been accessed in a DRAM within the current refresh cycle; ...
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