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WO/2022/068263A1 |
Provided are a memory and a memory testing method. The memory comprises: a storage module, which is used for storing data information, the storage module comprising a main storage module and a check bit storage module, the main storage m...
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WO/2022/072043A1 |
Systems, methods, and apparatus including conductive line contact regions having multiple multi-direction conductive lines and staircase conductive line contact structures for semiconductor devices. One memory device comprises arrays of ...
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WO/2022/068125A1 |
Provided are a memory circuit structure and method for operation thereof; the memory circuit structure comprises: a storage array, containing at least two memory cells; a decoder, separately connected to the bit and word lines of the mem...
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WO/2022/070965A1 |
Provided are a magnetic recording medium, a magnetic tape cartridge comprising the magnetic recording medium that is a magnetic tape, and a magnetic recording reproduction device comprising the magnetic recording medium. The magnetic rec...
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WO/2022/072207A1 |
Methods, apparatuses, and systems related to die-to-die communications are described. An apparatus may include a master die and a set of slave dies communicatively coupled to each other through an internal bus. The master die may be conf...
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WO/2022/064303A1 |
Provided is a semiconductor device the power consumption of which is reduced and which is capable of non-destructive readout. This semiconductor device has a first transistor, a second transistor, a third transistor, a first FTJ element,...
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WO/2022/066436A1 |
Methods, systems, and devices for temperature monitoring for memory devices are described for monitoring one or more temperature ranges experienced by a memory device. The memory device may include monitoring circuitry or logic that may ...
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WO/2022/064315A1 |
Provided is a semiconductor device that has reduced power consumption and is capable of non-destructive readout. The semiconductor device has: a first circuit that has a first transistor and a first FTJ element; and a second circuit that...
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WO/2022/064314A1 |
Provided is a display system that has high display quality. Provided is a display system that has low power consumption. A display system that has a processing unit, a display unit, and a storage unit. The storage unit holds correction d...
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WO/2022/062556A1 |
Embodiments of the present disclosure relate to the technical field of semiconductors. Disclosed is an integrated circuit. The integrated circuit comprises: a first data line group comprising multiple local data lines arranged in an arra...
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WO/2022/062544A1 |
The present application provides an integrated circuit memory and a forming method therefor. The memory comprises: a substrate, multiple active regions arranged in an array being provided in the substate; a conductive line group formed i...
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WO/2022/065013A1 |
When this host-slave system comprising a host device and a slave device transitions to a power-down mode, the host device drives a CMD line in the order of high level, low level, high level, and after the passage of a specified amount of...
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WO/2022/062550A1 |
A memory test circuit and a test method therefor. In the memory test circuit, a switch control circuit (100) is connected between a discharge end (301) and a negative bias signal end (302) of a word line drive circuit (300), and is used ...
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WO/2022/066371A1 |
Memory devices, systems including memory devices, and methods of operating memory devices are described, in which security locks are implemented to control access to secure functions of the memory devices. In one embodiment, the memory d...
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WO/2022/064308A1 |
In the present invention, a highly reliable semiconductor device is provided. This semiconductor device is provided with: a memory cell having a first ferroelectric capacitor; and a reference memory cell having a second ferroelectric cap...
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WO/2022/064302A1 |
A highly reliable storage device is provided. A storage device comprising a memory control unit, which has an input/output unit, a control unit, and a first management unit, and a plurality of memory blocks, wherein: the first management...
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WO/2022/062467A1 |
The present application provides a dual reference voltage generator, an equalization circuit, and a memory. The dual reference voltage generator receives an original code, a first code, and a second code, generates a first reference volt...
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WO/2022/062263A1 |
The present disclosure belongs to the technical field of memory, and mainly relates to a magneto-resistive device, a method for changing a resistance state thereof and a synaptic learning module. The magneto-resistive device comprises a ...
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WO/2022/066462A1 |
In some examples, a subword driver block of a memory device includes a first active region and a second active region adjacent to each other. The first active region forms drains/sources of a first and second transistors in a first regio...
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WO/2022/064505A1 |
The technology subject of the present application concerns methods and systems for manufacturing and producing stable polarized or ferroelectric layered materials.
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WO/2022/066585A1 |
A pseudo-triple-port memory is provided with read datapaths and write datapaths. The pseudo-triple-port memory includes a plurality of pseudo-triple-port bitcells, each pseudo-triple-port first bitcell having a first read port coupled to...
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WO/2022/062504A1 |
The present disclosure relates to the technical field of semiconductors, and provides a method and apparatus for evaluating the performance of an interface circuit, an electronic device, and a computer-readable storage medium. An interfa...
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WO/2022/064870A1 |
This non-contact communication device comprises: a processor; and a transmission/reception device which induces power in a non-contact storage medium mounted on a magnetic tape cartridge by applying a magnetic field to the non-contact st...
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WO/2022/064309A1 |
Provided is a semiconductor device of reduced power consumption that is capable of non-destructive reading. The semiconductor device comprises a first transistor, a first FTJ element, and a second FTJ element. The first terminal of the f...
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WO/2022/062265A1 |
A readout circuit, and a debugging method and apparatus for a readout circuit of a memory chip. The readout circuit comprises a current comparator; a first input terminal of the current comparator is connected to the drain of a first gat...
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WO/2022/065044A1 |
Provided is a magnetic recording head including a magnetic film including a write gap. The write gap has: a recording surface-side gap width which is narrower than a back surface-side gap width; and an opening which is formed, by ion bea...
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WO/2022/063093A1 |
The present disclosure provides a method and apparatus for generating a video in a text mode, a device and a medium. The method comprises: receiving a request for generating a video from a user of an information sharing application; disp...
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WO/2022/063658A1 |
The invention relates to: a scalar product circuit for calculating a binary scalar product of an input vector with a weight vector; and an associated method. The scalar product circuit comprises one or more adders and at least one matrix...
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WO/2022/064316A1 |
Provided is a semiconductor device having extremely low power consumption. Provided is the semiconductor device for which high processing capacity and high-speed operation are possible. The semiconductor device has one or both of a CPU a...
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WO/2022/062927A1 |
Provided are a hard disk bracket, a hard disk, and an electronic device. The hard disk bracket is used for carrying and mounting a hard disk body. The hard disk bracket comprises an integrated sheet metal frame, which is a main body stru...
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WO/2022/062477A1 |
The present application provides a memory data refresh method and a controller therefor, and a memory. The method comprises: determining a target refresh row in a data row of the memory according to the running state of the controller, t...
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WO/2022/064548A1 |
A semiconductor storage device of an embodiment comprises a first pin, a first receiving circuit, and a first termination circuit. The first pin receives a first signal and a second signal having an amplitude smaller than an amplitude of...
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WO/2022/061803A1 |
A bank and a dynamic random access memory (DRAM). The bank comprises: N latch circuits, N word line address decoding circuits, and a dynamic random access memory (DRAM) array. The latch circuits may be arranged in the bank, and the latch...
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WO/2022/062468A1 |
Provided are an equalization circuit, a data collection method and a memory. The equalization circuit comprises a first input buffer circuit, a second input buffer circuit and a selection and sampling circuit, wherein the first input buf...
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WO/2022/062497A1 |
A data path interface circuit, a memory, and a storage system. The data path interface circuit comprises: a write path module (100), which is separately connected to an internal port (12) and an external port (11), and is used to transfe...
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WO/2022/066439A1 |
Methods, systems, and devices for operating frequency monitoring for memory devices are described for monitoring one or more operating frequency ranges experienced by a memory device. The memory device may include monitoring circuitry or...
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WO/2022/064304A1 |
Provided is a semiconductor device having a novel configuration. A memory cell having a capacitor with a ferroelectric layer between a first electrode and a second electrode is provided. Data is written to the memory cell by applying, to...
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WO/2022/061630A1 |
In a method of programming a memory device, inhibit information is stored to first latch structures and second latch structures. A first state programming voltage is applied to data lines of memory cells of the memory device to program t...
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WO/2022/064780A1 |
An automatic transaction device according to the present disclosure comprises: a card processing unit that reads magnetic data from and writes magnetic data to a magnetic storage part of an inserted medium, and that reads data stored in ...
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WO/2022/058511A1 |
A Vertical Field Effect Transistor (VFET) and/or a one transistor dynamic random access memory 1 T DRAM that has a substrate (101 102) with a horizontal substrate surface, a source (103) disposed on the horizontal substrate surface, a dr...
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WO/2022/060564A1 |
Methods, apparatuses, and systems related to combining and utilizing multiple memory circuits having complementary characteristics are described. An apparatus may include a first memory circuit having a first characteristic and a second ...
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WO/2022/060637A1 |
Various embodiments described herein provide for a printed circuit boards with one or more spaces for embedding components, which can be used to implement a memory sub-system. The printed circuit board comprises an outer layer that compr...
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WO/2022/058479A1 |
The invention relates to an antiferromagnetic memory structure (1) configured for use in a non-transitory antiferromagnetic memory device (2), characterized in that the antiferromagnetic memory structure (1) comprises an antiferromagneti...
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WO/2022/058757A1 |
An apparatus has a plurality of photonic elements. At least two photonic elements forming a cavity. At least one photonic element receives first electromagnetic radiation from outside the cavity and transmits the first electromagnetic ra...
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WO/2022/057539A1 |
A column selection signal unit circuit, a bit line sensing circuit, and a memory. The column selection signal unit circuit comprises four column selection units, each unit including 4*N input/output ports, 4*N bit line connection ports, ...
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WO/2022/058768A1 |
The present disclosure provides a memory apparatus and a method for operating the same. The method comprises performing a read operation on a set of memory cells, detecting an error in data read from the set of memory cells based on an e...
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WO/2022/058838A1 |
The purpose of the present invention is to provide a low power consumption semiconductor device. This semiconductor device comprises a first transistor, a second transistor, and capacitances. The first transistor has a first gate and a f...
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WO/2022/059176A1 |
This semiconductor device is provided with a memory element writing unit (10) having: a memory element (1) which can be electrically written one time only and stores a binary value; a writing control section (2) which is connected to the...
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WO/2022/059901A1 |
The present invention relates to a wireless microphone system with which a receiver user can transmit sound to a wireless microphone user and with which the sound of the receiver user can be recorded, without a separate communication mea...
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WO/2022/057333A1 |
A memory device, a testing method therefor and a usage method therefor, and a memory system, which belong to the technical field of semiconductors. The memory device comprises: multiple channels, wherein each channel comprises a memory c...
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