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Patent Searching and Data


Matches 201 - 250 out of 661,464

Document Document Title
WO/2022/057417A1
A memory, comprising a storage block (100), the storage block (100) comprising a U storage sub-block (101) and a V storage sub-block (102); and comprising a first error checking and correcting unit (103), which is connected to the U stor...  
WO/2022/060544A1
Methods, systems, and devices for signal sampling with offset calibration are described. For example, sampling circuitry may include an input pair of transistors where input signals may be provided to gate nodes of the transistors, and a...  
WO/2022/057392A1
Provided are a clock circuit and a memory. The clock circuit comprises: a data gating clock module for receiving a data gating clock signal and transmitting the data gating clock signal, wherein the data gating clock signal is used for c...  
WO/2022/057438A1
A bit-line sense circuit, and a memory. The bit-line sense circuit comprises: L storage unit groups, each of the storage unit groups comprising H bit lines, and L and H both being positive integers equal to or greater than 2; and M sense...  
WO/2022/059956A1
Disclosed is a three-dimensional flash memory using a ferroelectric layer on the basis of a back gate structure. According to an embodiment, a three-dimensional flash memory comprises: a plurality of word lines extending on a substrate i...  
WO/2022/056757A1
Aspects of the present technology are directed toward three-dimensional (3D) stacked processing systems characterized by high memory capacity, high memory bandwidth, low power consumption and small form factor. The 3D stacked processing ...  
WO/2022/056760A1
Embodiments of phase-change memory (PCM) devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells each dispose...  
WO/2022/056714A1
Disclosed are a data disaster recovery storage device and a vehicle. The vehicle comprises a data disaster recovery storage device, the data disaster recovery storage device comprising an inner container having a hollow cavity; the hollo...  
WO/2022/061153A1
A memory controller includes a command queue having a first input for receiving memory access requests, and a memory interface queue having an output for coupling to a memory channel adapted for connecting to at least one dynamic random ...  
WO/2022/059378A1
The present invention comprises: first and second transistors of which the gates are connected in common; a resistor having a first end and a second end, the first end being connected to a source of the first transistor; a lead voltage s...  
WO/2022/055637A1
Methods and systems include memory devices (100) with multiple access lines (104, 106) arranged in an array (130) to form a multiple intersections. Memory cells (102) are located at the intersections of the multiple access lines (104, 10...  
WO/2022/052549A1
A semiconductor memory, comprising: a plurality of storage arrays; at least one check module each corresponding to the plurality of storage arrays and configured to check whether an error occurs in data information of a corresponding sto...  
WO/2022/054401A1
This information processing device is provided with at least one processor. The processor performs control to: read out a plurality of objects recorded on a magnetic tape of a transfer source; construct, among the plurality of objects th...  
WO/2022/055087A1
A signal delay device disclosed in this specification may be configured by comprising: a delay circuit for outputting a delayed feedback signal by delaying a delay start signal by means of a plurality of unit delay units connected in ser...  
WO/2022/055885A1
The systems, devices, and methods described herein provide nucleic acid digital data storage encoding and retrieving methods that are less costly and easier to commercially implement than existing methods. The systems, devices, and metho...  
WO/2022/054571A1
[Problem] To provide a method for producing a dispersed iron oxide magnetic powder slurry that exhibits an excellent dispersity even in the weakly acidic region to medium alkaline region. [Solution] A dispersed iron oxide magnetic powder...  
WO/2022/055650A1
Various implementations disclosed herein include devices, systems, and methods that presents playback of application content within a three-dimensional (3D) environment. An exemplary process presents a first set of views of a scene that ...  
WO/2022/052554A1
A defect repair circuit and a defect repair method. The defect repair circuit comprises: a test module, which is used for performing a defect test on a storage unit array in a test mode, so as to determine defective storage units, and ou...  
WO/2022/054402A1
This information processing device performs a process of deriving a movement path of a magnetic head at the time of reading user data to be read recorded in a first area of magnetic tape having the first area, which is for recording user...  
WO/2022/054888A1
An image reproduction device 6 reproduces an image including N different parameters of a wavelength range or the like, and comprises: a multiplexed hologram acquisition unit 61 for acquiring N to 2N multiplexed holograms obtained by mult...  
WO/2022/055875A1
Devices and techniques are disclosed herein for predicting and optimizing energy usage of a device during low-power operation. In an example, a method can include storing a duration of a plurality of low-power intervals of a device, dete...  
WO/2022/052542A1
A method and apparatus for determining a fail bit repairing solution, applicable to a chip comprising a plurality of subdomains. The chip further comprises a redundancy circuit, and the redundancy circuit is used for repairing a fail bit...  
WO/2022/055881A1
Disclosed herein is an apparatus that includes a first shift register circuit including a plurality of first latch circuits coupled in series, and a second shift register circuit including a plurality of second latch circuits coupled in ...  
WO/2022/049831A1
An information processing device periodically performs processing of comparing, with a threshold value, a count or a total value of size of objects in an object group to be processed, regarding which bundling processing is unexecuted, an...  
WO/2022/048274A1
A test system and a test method. The test system comprises: a signal providing module configured to provide a first clock signal and a second clock signal for a memory to be tested, wherein the memory to be tested executes a write comman...  
WO/2022/048083A1
A magnetic random access memory device and a method for manufacturing same. The device comprises: a substrate, on which a first interlayer dielectric layer and bottom electrode contact parts, which extendingly pass through the first inte...  
WO/2022/051067A1
Methods, systems, and devices for selectable error control for memory device are described. An apparatus may include a memory array and a circuit configurable to perform a first error control operation and a second error control operatio...  
WO/2022/048246A1
A drive circuit, comprising: a pull-up transistor and a pull-down transistor, wherein a first terminal of the pull-up transistor is connected to a power supply, a second terminal of the pull-up transistor is connected to a first terminal...  
WO/2022/048074A1
A sense amplifier, a memory, and a method for controlling a sense amplifier, which relate to the technical field of semiconductor memories. The sense amplifier (1) comprises: an amplification module (11) used to read data of a storage un...  
WO/2022/051088A1
Aspects of the present disclosure relate to systems and methods for issuing and executing a clear content command within a memory. Certain embodiments provide a method of clearing content stored on a volatile memory, the memory comprisin...  
WO/2022/048227A1
A data protection apparatus, a storage device and a storage system. In the solution, an external power source is monitored by means of a power source monitoring module inside a host, and when it is determined that the external power sour...  
WO/2022/049448A1
Provided is a semiconductor device whereby long data retention time is achieved. The present invention pertains to a semiconductor device including a first transistor, a second transistor, a ferroelectric capacitor, a first capacitance, ...  
WO/2022/048238A1
A semiconductor device. The semiconductor device comprises multiple storage unit groups and multiple sensing amplification unit groups, and at least two storage unit groups share the same sensing amplification unit group, so that a sensi...  
WO/2022/051112A1
The present disclosure generally relates techniques and user interfaces for transmitting audio using a computer system in accordance with some embodiments.  
WO/2022/048235A1
A method and apparatus for determining a failed bit repair scheme, and a chip, which relate to the technical field of integrated circuits, and may be applied to a scenario of repairing failed bits in a chip. The method for determining th...  
WO/2022/048073A1
A sense amplifier, a memory, and a control method for the sense amplifier, relating to the technical field of semiconductor memories. The sense amplifier (1) comprises: an amplification module (11) used for reading data in a storage unit...  
WO/2022/051042A1
A device may include a first die having a first circuit and a second die having a second circuit. The die may be separated by a material layer. The material layer may include multiple through-silicon vias (TSVs) for electrically coupling...  
WO/2022/048217A1
The present disclosure relates to the field of storage technology, and proposes a semiconductor structure, and a fabrication method and control method therefor. The semiconductor structure comprises a base substrate, a plurality of bit l...  
WO/2022/051602A1
Methods and apparatus for utilizing non-traditional (e.g., probabilistic or statistically-based) refresh schemes in non-volatile memory. In one embodiment, the memory is characterized in terms of its performance, such as based on BER (bi...  
WO/2022/047802A1
A processing-in-memory (PIM) device includes a memory array configured to store data and a computing circuit. The computing circuit is configured to execute a set of instructions to cause the PIM device to: select between multiple comput...  
WO/2022/048286A1
A test fixture adapter board and a memory test device, the test fixture adapter board comprising a circuit board, and a first connection part, second connection part, plurality of capacitors and capacitor switching circuit that are provi...  
WO/2022/048240A1
The present application provides a read/write method for a storage device, and a storage device. The storage device comprises a storage chip. The read/write method for a storage device comprises, during running of a storage chip, measuri...  
WO/2022/047540A1
A method of generating a device fingerprint for a device that comprises at least one integrated circuit comprises: obtaining a plurality of raw bit values from the at least one integrated circuit; generating noise-resistant bits from the...  
WO/2022/047645A1
Semiconductor devices and methods for forming the same are disclosed. A first interlayer dielectric (ILD) layer (402) is formed on a first side of a substrate (408). A plurality of first contacts (404) each extending vertically through t...  
WO/2022/046300A1
Systems, apparatuses, and methods related to audio input prioritization are described. Systems may include to one or more sound devices. Audio input may be played on a sound device based on one or more settings applied to the audio input...  
WO/2022/042017A1
An interface circuit, a data transmission circuit and a memory, relating to the technical field of semiconductors. The interface circuit comprises a clock pad (102), data pads (101) and input buffer circuits (103), wherein the clock pad ...  
WO/2022/047159A1
Systems, apparatuses, and methods related to a memory device and an associated host device are described. The memory device (104) and the host device (102) can include control logic (112, 118) that allow the memory device and host device...  
WO/2022/047164A1
A memory is provided that is configured to practice both a normal read operation and also a burst mode read operation. A burst mode address comparator compares a current row address to a preceding row address from a preceding read operat...  
WO/2022/047422A1
A memory processing unit (MPU) can include a first memory, a second memory, a plurality of processing regions and control logic. The first memory can include a plurality of regions. The plurality of processing regions can be interleaved ...  
WO/2022/046219A1
Apparatuses and techniques are described for reducing read time in a memory device. A source voltage signal, Vcelsrc, and a body voltage signal, Vp-well, of a source region and a p-well, respectively, of a substrate of a NAND string are ...  

Matches 201 - 250 out of 661,464