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Patent Searching and Data


Matches 251 - 300 out of 863,225

Document Document Title
WO/2021/022226A1
A request to perform a write operation at a memory component can be received. A destination block of the memory component to store data of the write operation can be determined. A voltage pulse can be applied to the destination block tha...  
WO/2021/021494A1
A memory is provided that includes a negative bit line boost circuit for boosting a discharged bit line to a negative voltage during a negative bit line boost period for a write operation to a selected column in the memory. The memory al...  
WO/2021/021569A1
Various embodiments described herein use a plurality of capacitor sets (e.g., capacitor banks) in a power backup architecture for an electronic system (e.g., memory sub-system), where each capacitor set can be individually checked agains...  
WO/2020/264045A3
Apparatus and methods for enabling indexing and playback of media content before the end of a content capture. In one aspect, a method for enabling indexing of media data obtained as part of a content capture is disclosed. In one embodim...  
WO/2021/017348A1
An IGBT physical model parameter extraction method, characterized by comprising the following steps of: obtaining an initial value and a transformation range of an IGBT physical model parameter; and correcting a model parameter by means ...  
WO/2021/019998A1
Provided is a compound capable of realizing a lubricant having excellent adhesion to a magnetic disc, especially to a protective layer. A perfluoropolyether compound according to an embodiment of the present invention has a structure in ...  
WO/2021/021507A1
A memory is provided that is configured to practice both a normal read operation and also a burst mode read operation. A burst mode address comparator compares a current row address to a previous row address to determine whether a read o...  
WO/2021/021288A1
Systems, apparatuses, and methods related to performing operations within a memory device are described. Such operations may be performed using data latched in multiple sense amplifiers that are distributed among a plurality of sense amp...  
WO/2021/021301A1
Aspects of the present disclosure relate to techniques for identifying susceptibility to induced charge leakage. In examples, a susceptibility test sequence comprising a cache line flush instruction is used to repeatedly activate a row o...  
WO/2021/021574A1
Various embodiments described herein provide a system that uses a capacitor-based power converter to generate a gate voltage (e.g., boot strap voltage) for a buck converter. According to various embodiments described herein, the capacito...  
WO/2021/021645A1
Methods and apparatuses for memory device mode selection in a serial memory device are presented. Memory device configuration information may be retrieved in response to a memory device initialization condition, and a configuration regis...  
WO/2021/019322A1
The present invention relates to a device (200) for data storage and processing, comprising: - at least two input racetrack elements (210a, 210b, 210c) comprising a plurality of first magnetization regions (103); - at least one output ra...  
WO/2021/015812A1
Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks. The analog neural memory comprises one or more arrays of non-volatile memory cells. The testing circuitry and meth...  
WO/2021/015829A1
A heat-assisted magnetic recording (HAMR) head for recording data in data tracks of a HAMR disk has a gas-bearing slider that supports a near-field transducer (NFT) and a main magnetic pole formed of two layers. The first main pole layer...  
WO/2021/015813A1
Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks. The analog neural memory comprises one or more arrays of non-volatile memory cells. The testing circuitry and meth...  
WO/2021/015198A1
This optical structure is provided with: a spacer layer having translucency or transparency; an image-forming reflector formed in a first area at least on the spacer layer, the image-forming reflector having a reflective layer; and a pro...  
WO/2021/014760A1
Provided is a sputtering target member having excellent economy and being useful for the formation of non-magnetic layers have an hcp structure and constituting vertical magnetic recording media. This sputtering target member for non-mag...  
WO/2021/015830A1
A data storage device is disclosed comprising a head actuated over a disk, wherein the head comprises a write assist element. Data is written to the disk using the write assist element. A protrusion of the head toward the disk is measure...  
WO/2021/014136A1
A record player comprising a turntable, the turntable being adapted to rotate about a spindle axis; a pivot comprising a pivot point; a record arm connected to the pivot at the pivot point, the record arm being adapted to rotate at the p...  
WO/2021/016257A1
A magnetic processing unit ("MPU") includes a magnetic element with one or more input channels and one or more output channels. The magnetic element can acquire magnetic arrangement configured to perform a predetermined operation on the ...  
WO/2021/015940A1
An integrated circuit that includes a set of one or more logic layers that are, when the integrated circuit is stacked in an assembly with the set of stacked memory devices, electrically coupled to a set of stacked memory devices. The se...  
WO/2021/012620A1
An anti-fuse cell circuit and an integrated chip. The anti-fuse cell circuit comprises a programming unit (100) and a detection unit (200). The programming unit (100) is used for programming an anti-fuse cell according to a programming v...  
WO/2021/015240A1
Provided is a glass for magnetic recording medium substrates, which comprises an amorphous glass having an SiO2 content of 54 to 62 mol% inclusive, an MgO content of 15 to 28 mol% inclusive, an Li2O content of 0.2 mol% or more and an Na2...  
WO/2021/015882A1
Methods, systems, and devices for adaptive write operations for a memory device are described. In an example, the described techniques may include identifying a quantity of access operations performed on a memory array, modifying one or ...  
WO/2021/016500A1
A metrology tool includes a magnet to generate a magnetic field and a stage system to position a plurality of MRAM dies on an MRAM wafer in the magnetic field. The stage system includes a chuck on which to mount the MRAM wafer. The metro...  
WO/2021/011236A1
In an embodiment, a memory controller in an integrated circuit may generate refreshes for one or more DRAMs coupled to the integrated circuit according to a refresh rate. The integrated circuit may include one or more temperature sensors...  
WO/2021/010923A1
The present invention to relates to applying bias voltages to the access transistors (211) in the cells depending on the determined data retention time data of the cells in dynamic random access memory structures in an adaptive manner or...  
WO/2021/008350A1
Disclosed in the present application is an audio playback method, the method comprising: acquiring PCM data corresponding to audio data inputted into a sound card; performing frequency band separation on the PCM data and, on the basis of...  
WO/2021/011416A1
A request can be received to perform a read operation to retrieve data at a memory sub-system. A time to perform the read operation can be determined. A time a write operation was performed to store the data at the memory sub-system can ...  
WO/2021/009586A1
Provided is a semiconductor device capable of efficiently reading weighting factors and efficiently performing multiply-accumulate operations. The semiconductor device comprises multiply-accumulate circuitry and a storage device. The mul...  
WO/2021/011307A1
A system includes a plurality of memory devices and a processing device (e.g., a controller), operatively coupled to the plurality of memory devices. The processing device is to detect a power-on of the system and determine a read-retry ...  
WO/2021/011847A1
A refresh operation can be performed at a memory sub-system The refresh operation can performed at a current frequency. A write count associated with the memory sub-system can be received. A determination can be made as to whether the wr...  
WO/2021/011078A1
Disclosed in some examples are methods, systems, storage devices, and machine readable mediums that utilize the ability of ECC to correct errors to actively prevent errors. The memory device determines whether a request to place data of ...  
WO/2021/011263A1
An indication that an allocation unit of a memory sub-system has become unmapped can be received. In response to receiving the indication that the allocation unit of the memory sub-system has become unmapped, the allocation unit can be p...  
WO/2021/011234A1
Exemplary methods, apparatuses, and systems include a first die in a power network receiving, from each of a plurality of dice in the power network, a first signal indicating that the respective die is in a high current state or a second...  
WO/2021/011311A1
Methods, systems, devices, and other implementations to store fuse data in memory devices are described. Some implementations may include an array of memory cells with different portions of cells for storing data. A first portion of the ...  
WO/2021/011582A1
Methods and apparatus for reading NAND flash memory are disclosed. In an embodiment, a method is provided for reading a NAND flash memory that includes strings of memory cells that are coupled to bit lines and word lines. The method incl...  
WO/2021/008481A1
Provided in the present invention are an audio playback device, a central control system, and a method and a system for updating and playing audio, the method for playing audio comprising: when the current environment triggers a preset p...  
WO/2021/008121A1
A data storage device, relating to data storage technology. The present invention comprises a data memory, and is characterized by further comprising a sealed housing; the data memory is located in the sealed housing; a power supply inte...  
WO/2021/011849A1
A read operation can be performed to retrieve data of a write unit at a memory subsystem. An indication of a time of the performance of the read operation can be received. Another indication of another time of a performance of a write op...  
WO/2021/011315A1
Disclosed herein includes a system, a method, and a device for performing a convolution on data of a current layer of a neural network, including a plurality of channels arranged in a first order and partitioned into a plurality of first...  
WO/2021/011144A1
Disclosed herein are exemplary magnetic tunnel junction structures for magnetic random access memory applications. A magnetic tunnel junction stack includes a structure blocking layer and a magnetic reference layer. The magnetic referenc...  
WO/2021/011923A1
A memory system having a temperature effect compensation mechanism is provided. The memory system memory cells in an array having rows of memory cells arranged horizontally and columns arranged vertically. The memory cells have an operat...  
WO/2021/011414A1
A system includes a memory component, and a processing device coupled with the memory component. The processing device to identify a group of management units of the memory component, wherein the group of management units is included in ...  
WO/2021/009298A1
A video rendering device for displaying a video comprising: a flash detector which detect an abrupt brightness change of the video, and a signalling device which provides an acoustic signal in response to the detection of the brightness ...  
WO/2021/011708A1
Systems, devices, and methods transcribe words recorded in audio data. A computer-generated transcript is provided. The transcript comprises records for each word in the computer-generated transcript. At least one confirmation input is r...  
WO/2021/011202A1
A processing device is configured to: identify a first range of a plurality of write-to-read delay ranges for the memory component; identify a first set of the plurality of write-to-read delay times at a first end of the first range and ...  
WO/2021/009607A1
Provided is a storage device that reduces access time in data readout. The storage device includes a first layer, and a second layer which is located above the first layer. The first layer includes a readout circuit, and the second layer...  
WO/2021/011011A1
An approach to a reduced-head hard disk drive (HDD) involves a load/unload (LUL) ramp subsystem that includes a ramp assembly that includes a translatable lever member and a LUL ramp member coupled thereto, and interconnected elevator in...  
WO/2021/011241A1
A memory device comprises a block of ranged content-addressable memory (RCAM) including multiple RCAM memory elements, wherein each RCAM memory element is accessed by content that includes two values; a search register configured to stor...  

Matches 251 - 300 out of 863,225