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WO/2023/113880A1 |
Examples are disclosed that relate to a multi-port synchronous dynamic random access memory (SDRAM). One example provides a multi-port SDRAM comprising a first port, a second port, a first memory portion, and a second memory portion. At ...
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WO/2023/114533A1 |
A memory performing logic functions has two single transistor static ram memory (STSRAM) with drain, source, and gate terminal which can be written, read, and when read, generates an output current. The STSRAMs have drain and source conn...
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WO/2023/114071A1 |
A fine-grained dynamic random-access memory (DRAM) includes a first memory bank, a second memory bank, and a dual mode I/O circuit. The first memory bank includes a memory array divided into a plurality of grains, each grain including a ...
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WO/2023/111763A1 |
The present invention provides a semiconductor device having a novel configuration. The semiconductor device has a register. The register has a flip-flop and a plurality of data holding circuits. The flip-flop has a first transistor in w...
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WO/2023/108471A1 |
A driver circuit and a display apparatus. The driver circuit comprises a pull-up node (NA), an input module (11), a pull-up module (12), a first output module (13) and a second output module (14). The input module (11) is electrically co...
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WO/2023/112574A1 |
A memory circuit (11) is a memory circuit provided in an IC chip (100). The memory circuit (11) comprises a complementary cell (CL) provided with a first memory cell (MC1) including a first memory transistor (MT1) and a second memory cel...
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WO/2023/113855A1 |
A memory system identifies memory cells connected to a common word line that have had their threshold voltage unintentionally drift lower than programmed by determining whether memory cells meet two criteria: (1) the memory cells have th...
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WO/2023/111439A1 |
One aspect of the invention relates to a device (220) for controlling access to a non-volatile memory (230), access being requested by an electronic system (210), the device (220), the electronic system (210) and the volatile memory bein...
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WO/2023/113858A1 |
A system has been described that performs differential temperature compensation based on a differential between the temperature at time of programming and temperature at time of reading for a set of data. Differential temperature compens...
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WO/2023/113856A1 |
Various illustrative aspects are directed to a data storage device comprising one or more disks; an actuator arm assembly comprising one or more actuator arms, and configured to position the one or more actuator arms over disk surfaces o...
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WO/2023/112146A1 |
This memory device comprises a page composed of a plurality of memory cells arranged in a column shape on a substrate, and controls voltages applied to a first gate conductive layer, a second gate conductive layer, a first impurity area,...
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WO/2023/114285A1 |
A multi-bit, asynchronous e-fuse macro, the macro comprising: the following inputs: an input output enable, a power on reset, a write address, an input write enable, a ground clamp enable, and a write clock; a plurality of e-fuse bits; a...
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WO/2023/113859A1 |
A system has been described that performs differential temperature compensation based on a differential between the temperature at time of programming and temperature at time of reading for a set of data. Differential temperature compens...
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WO/2023/108383A1 |
A memory device includes an array of memory cells in a plurality of memory strings and arranged in a plurality of rows of memory cells. The memory device also includes a plurality of word lines respectively coupled to the plurality of ro...
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WO/2023/112122A1 |
This memory device is provided with a page comprising a plurality of memory cells arranged in columns on a substrate, and carries out: a page write operation for holding a hole group, which is formed by an impact-ionization phenomenon, i...
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WO/2023/114249A1 |
In examples, an electronic device (104) comprises an oscillator circuit (118) configured to provide an output signal and a controller (112) coupled to the oscillator circuit. The controller is configured to receive first and second targe...
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WO/2023/104891A1 |
The invention relates to a memory device that comprises: - a memory bank provided with n memory rows, each row i being liable to effect a row hammer having a range p; - a block for preventing the hammer effect which comprises counting me...
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WO/2023/107285A1 |
A multi-domain masked AND gate includes inner-domain calculations, re-sharing, register stage, cross-domain calculations, and compression. The inner-domain multiplication and the re-sharing are calculated prior to storing the re-shared v...
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WO/2023/103358A1 |
The present application provides a programming apparatus and method, and a novel memory. The programming apparatus comprises a programming control unit and a programming unit; the programming control unit is configured to respond to a co...
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WO/2023/107784A1 |
A method comprises receiving a read instruction and determining a read address in computer memory corresponding to the read instruction, where the read address references a cell within a row of read-destructive computer memory. The metho...
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WO/2023/107313A1 |
A read clock circuit selectively provides a read clock signal from a memory to a memory controller over a memory bus. A pulse-amplitude modulation (PAM) driver including an input and an output capable of driving at least three levels ind...
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WO/2023/102779A1 |
The present application relates to the technical field of computer storage, and discloses a memory, a memory test method, and an electronic device. The memory comprises a storage circuit and a test circuit, storage units for storing data...
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WO/2023/107311A1 |
A memory includes a read clock circuit and a mode register. The read clock circuit has an output for providing a hybrid read clock signal in response to a clock signal and a read clock mode signal. The mode register provides the read clo...
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WO/2023/104008A1 |
A data error correction method and device, a memory controller, and a system. In the present application, when needing to read target data in a memory, a memory controller reads the target data and a first verification code of the target...
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WO/2023/105376A1 |
A system and method for performing a low overhead refresh management of a memory device. The method includes receiving, by a controller from a dynamic random access memory (DRAM) device via a feedback interface, a signal indicative of an...
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WO/2023/103148A1 |
An address refresh circuit (10), a method, a memory, and an electronic device. The address refresh circuit (10) comprises a selector circuit (101) and a decoding circuit (102); the selector circuit (101) is used for acquiring a gating si...
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WO/2023/104735A1 |
The present description relates to a device (100) for testing a resistive-memory cell (10), comprising: - a conductive element (108) suitable for connecting the cell to the device; - a generator (102) of signals for writing to and readin...
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WO/2023/104737A1 |
The present invention relates to a system (200) for testing a variable resistance memory, suitable for implementing at least one test phase from the following test regimes: - quasi-static test regime; - pulse test regime, including an er...
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WO/2023/104733A1 |
The present invention relates to a magnetic field generation system (200) comprising: - a central pole (220) positioned above a plane (XY), the axis of said central pole extending in a direction orthogonal to the plane; - at least two pl...
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WO/2023/104011A1 |
The present application belongs to the technical field of data processing. Disclosed are a storage medium, a storage element, a storage medium configuration method and a data transmission method. For the storage medium, the storage mediu...
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WO/2023/104550A1 |
Embodiments of the present dislcosure include a phase change memory (PCM) array (102). The PCM array includes a plurality of PCM cells (104a, 104b). Each PCM cell in the plurality of PCM cells include a top electrode (122a, 122b), a resi...
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WO/2023/103183A1 |
Provided in the present invention are a switch device and a memory. The switch device comprises a lower electrode, an upper electrode and a switch material layer sandwiched between the lower electrode and the upper electrode, wherein the...
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WO/2023/102760A1 |
A method for analyzing integrated circuits, includes: performing a first resistor capacitor (RC) extraction process on a power-receiving circuit and producing a first RC model; scanning a netlist of a power distribution network, the powe...
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WO/2023/103555A1 |
A stacked phase change memory structure having a cross-point architecture is provided. The stacked phase change memory structure includes at least two phase change material element-containing structures (MS1, MS2) stacked one atop the ot...
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WO/2023/107769A1 |
In accordance with an embodiment, a circuit includes a plurality of comparators disposed on an integrated circuit, the plurality of comparators having inputs coupled to a monitored power supply line; and a voting circuit having inputs co...
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WO/2023/107392A1 |
In some embodiments, a memory device implements a tile-based architecture including an arrangement of independently and concurrently operable arrays or tiles of memory transistors where each tile includes memory transistors that are arra...
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WO/2023/106105A1 |
A semiconductor memory device (100) is provided with: a plurality of memory cells (112); a first power supply line (VDD); a second power supply line (VDDMC); a first transistor (T01) and a second transistor (T02) connected in parallel be...
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WO/2023/107304A1 |
A memory includes a read clock state machine and a read clock driver circuit. The read clock state machine has a first input for receiving a read command signal, a second input for receiving a read clock mode signal, and an output for pr...
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WO/2023/105604A1 |
This memory device is provided with a page formed from multiple memory cells arranged in columns on a substrate, and carries out: a page write operation for holding a hole group, which is formed by an impact-ionization phenomenon, inside...
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WO/2023/107390A1 |
A memory system including a memory device of storage transistors organized in multiple memory banks where the memory device interacts with a controller device to perform read and write operations. In some embodiments, the controller devi...
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WO/2023/107310A1 |
A memory controller monitors memory command selected for dispatch to the memory and sends commands controlling a read clock state. A memory includes a read clock circuit and a mode register. The read clock circuit has an output for provi...
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WO/2023/107218A1 |
A high-bandwidth dual-inline memory module (HB-DIMM) includes a plurality of memory chips, a plurality of data buffer chips, and a register clock driver (RCD) circuit. The data buffer chips are coupled to respective sets of the memory ch...
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WO/2023/102785A1 |
Embodiments of the present application provide a memory and a memory manufacturing method. The memory comprises a write word line, a write bit line, a read word line, a read bit line, and a storage unit; the storage unit comprises a writ...
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WO/2023/106434A1 |
Provided is a method for correcting a memory error of a dynamic random-access memory module (DRAM) by using a double data rate (DDR) interface. The method comprises the steps of: performing a memory transaction including multiple bursts ...
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WO/2023/100874A1 |
Provided is a magnetic-tape cartridge group containing a plurality of magnetic tape cartridges. A magnetic tape included in the magnetic tape cartridges contains a polyethylene-naphthalate support element having a widthwise Young's modul...
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WO/2023/101791A1 |
Disclosed herein are systems and methods for self-isolation of power-management integrated circuits (PMICs) of memory modules under and in response to fault conditions. In an embodiment, a PMIC is operably engaged with a memory module th...
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WO/2023/100870A1 |
Provided is a magnetic tape housing body which includes a winding core on which a magnetic tape is wound. In this invention, the magnetic tape has a non-magnetic support and a magnetic layer containing a ferromagnetic powder, wherein the...
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WO/2023/100879A1 |
Provided is a magnetic tape having a non-magnetic support and a magnetic layer containing a ferromagnetic powder. The non-magnetic support is a polyethylene naphthalate support that has a Young's modulus of at least 10,000 MPa in the wid...
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WO/2023/100878A1 |
Provided is a magnetic tape which includes a non-magnetic support and a magnetic layer containing ferromagnetic powder. In this invention, the non-magnetic support is a polyethylene naphthalate support having a Young's modulus of 10,000 ...
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WO/2023/100872A1 |
Provided are: a magnetic tape cartridge in which a magnetic tape is accommodated; and a magnetic recording/playback device including the magnetic tape cartridge. The magnetic tape includes a polyethylene naphthalate support having a Youn...
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