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Patent Searching and Data


Matches 251 - 300 out of 661,464

Document Document Title
WO/2022/043041A1
A system for determining an order for reproducing light scripts is configured to select at least three songs from a collection of songs and obtain at least three light scripts (51-58) for the at least three songs. The system is further c...  
WO/2022/043270A1
A cutter unit (3) for carrying a cutter (6) for cutting a phonographic record comprises a cutter carrier (31) and a cutter head (4), the cutter head (4) being carried by the cutter carrier (31) and arranged to be displaced relative to th...  
WO/2022/041957A1
The embodiments of the present application provide an adjustment method and an adjustment system for a memory, and a semiconductor device. The adjustment method for a memory comprises: acquiring a mapping relationship between the tempera...  
WO/2022/044161A1
The present invention increases the proportion of acceptable chips on a wafer. A storage wafer according to one embodiment of the present invention is provided with: a first semiconductor (71W); a first element layer (72W) which is provi...  
WO/2022/047265A1
Systems, apparatuses, and methods related to a memory device, such as a low-power dynamic random-access memory (DRAM) and an associated host device are described. The memory device (104) and the host device (102) can include control logi...  
WO/2022/042023A1
Provided are a memory adjustment method and adjustment system, and a semiconductor device. The memory adjustment method comprises: acquiring a mapping relationship between the temperature of a transistor, the substrate bias voltage of a ...  
WO/2022/042836A1
There is provided a verifiable OTP memory device, the memory device comprising an MTP memory block and an OTP memory block for storing data, and a memory controller. The memory controller is configured to handle write requests and read r...  
WO/2022/044603A1
This information processing device: uses a prescribed order derivation algorithm to derive a read order when reading a plurality of data pieces to be read from one among a plurality of magnetic tapes on which a plurality of data pieces a...  
WO/2022/041033A1
A method of cache programming of a NAND flash memory in a triple-level-cell (TLC) mode is provided. The method includes discarding an upper page of a first programming data from a first set of data latches in a plurality of page buffers ...  
WO/2022/046754A1
The present disclosure relates to systems that capture a combination of image data and environmental data of the environment. The system uses the environmental data to create a detailed virtual scan of the environment. Computer generated...  
WO/2022/047084A1
Methods and apparatus for NAND flash memory are disclosed. In an embodiment, a NAND flash memory is provided that includes a plurality of bit lines connected to a plurality of bit line select gates, respectively, and a page buffer connec...  
WO/2022/047060A1
In some examples, a subword driver block of a memory device includes a plurality of active regions of a first type and a plurality of active regions of a second type adjacent to the plurality of active regions of the first type. The subw...  
WO/2022/046171A1
Numerous embodiments of analog neural memory systems that enable concurrent write and verify operations are disclosed. In some embodiments, concurrent operations occur among different banks of memory. In other embodiments, concurrent ope...  
WO/2022/046535A1
The present disclosure includes apparatuses, methods, and systems for increase of a sense current in memory. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to apply, prior to sensing a data s...  
WO/2022/041198A1
Disclosed in the present invention is a temperature change calculation method for a three-dimensional stacked memory chip. The method comprises: combining a heat transfer theory with the structure of a three-dimensional stacked memory ch...  
WO/2022/042099A1
Embodiments of the present application provide a memory adjustment method and system, and a semiconductor device. The memory adjustment method comprises: obtaining a mapping relationship among a temperature of a transistor, an equivalent...  
WO/2022/043077A1
The invention relates to an electricity metering circuit for a matrix operation circuit, having a circuit input for an electrical input current that is an output current of the matrix operation circuit. The electricity metering circuit i...  
WO/2022/041032A1
A 3D memory device (100, 400) includes multiple decks vertically stacked over a substrate (330), wherein each deck includes a plurality of memory cells (340). An erase method (900) includes checking states of the plurality of memory cell...  
WO/2022/041962A1
A data transmission circuit and a memory. The data transmission circuit comprises: a normal reading module connected to a normal storage array and used for reading data from the normal storage array and outputting same; a redundant readi...  
WO/2022/046224A1
A memory device comprises a memory array, a counter unit, and a service unit. The memory array comprises cells arranged in rows and columns. A subset of the cells in each of the rows holds a row activation count for each row. The counter...  
WO/2022/044705A1
This magnetic tape cartridge comprises a case in which a magnetic tape is accommodated, and a storage medium provided in the case. For the magnetic tape drawn from the case, at least one of reading and writing of data is performed by mea...  
WO/2022/047438A1
In some aspects, a controller may obtain a back electromotive force (BEMF) signal associated with a haptic feedback component, wherein the BEMF signal is generated by movement of the haptic feedback component. The controller may determin...  
WO/2022/046218A1
Apparatuses and techniques are described for increasing channel boosting of NAND string during programming by applying a periodic low word line bias during programming. In one aspect, a low pass voltage, VpassL, is applied to designated ...  
WO/2022/041973A1
Provided are a transmission circuit, an interface circuit and a memory. The transmission circuit comprises: an upper-layer clock pad (101), which is used for transmitting a clock signal; M upper-layer data pads (102), which are used for ...  
WO/2022/046125A1
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for generating variants/versions of an audio digital component and providing a particular variant for displaying/playing on a client devic...  
WO/2022/042151A1
A distributed audio recording method and device (1700). A distributed audio recording instruction is sent by a receiver to control one or more transmitters for audio recording, and audio data obtained by audio recording is sent to an upp...  
WO/2022/041278A1
Embodiments of the present application relate to the field of storage. Provided is a memory. The area and power consumption of the memory can be reduced while ensuring the writing flexibility. The memory comprises a plurality of storage ...  
WO/2022/046451A1
Methods, systems, and devices for programming techniques for polarity-based memory cells are described. A memory device may use a first type of write operation to program one or more memory cells to a first state and a second type of wri...  
WO/2022/043727A1
The present disclosure relates to a method for accessing of memory cells wherein a set of user data is stored in a plurality of memory cells of the memory array, comprising at least the steps of: - latching a current row address of a sel...  
WO/2022/041956A1
Provided are a processing method for wafer detection data and a computer-readable storage medium, which relate to the technical field of wafer manufacturing. The processing method for wafer detection data comprises: determining new failu...  
WO/2022/040853A1
The present disclosure provides a symmetrical type memory cell and a BNN circuit. The symmetrical type memory cell comprises a first complementary structure and a second complementary structure; the second complementary structure is symm...  
WO/2022/046593A1
The present disclosure includes apparatuses, methods, and systems for memory cell programming that cancels threshold voltage drift. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a...  
WO/2022/041944A1
The embodiments of the present application provide a memory, comprising: a control chip; and a plurality of memory chips; the plurality of memory chips share a channel and are electrically connected to the control chip, the plurality of ...  
WO/2022/044435A1
This information processing device: derives, in accordance with the number or total size of objects received per unit time, a time interval for periodically executing a process for combining a group of to-be-processed objects that have n...  
WO/2022/047423A1
A memory processing unit (MPU) configuration method can include mapping operations of one or more neural network models to sets of cores in a plurality of processing regions. In addition, dataflow of the one or more neural network models...  
WO/2022/041920A1
A memory array self-refresh frequency test method and a memory array test device. The test method comprises: providing a memory array; determining the shortest duration of electric leakage of each memory unit in the memory array, and mar...  
WO/2019/147859A9
Synaptic resistors (synstors), and their method of manufacture and integration into exemplary circuits are provided. Synstors are configured to emulate the analog signal processing, learning, and memory functions of synapses. Circuits in...  
WO/2022/047181A1
A charge-transfer transistor couples between a bit line and a sense node for a sense amplifier. During a read operation, a charge-transfer driver drives a gate voltage of the charge-transfer transistor to control whether the charge-trans...  
WO/2022/041052A1
Methods, systems, and devices for external power functionality techniques for memory devices are described. A memory system, which may be coupled to a first power source associated with a first voltage, may detect whether a second power ...  
WO/2022/041216A1
Methods, systems, and devices for debug capabilities of a memory system with a pin are described. An apparatus may include a memory system that includes a plurality of pins of a first type that are configured to communicate information a...  
WO/2022/046285A1
Systems, apparatuses, and methods related to chiplets are described. A chiplet-based system may include a memory controller chiplet to control accesses to a storage array, and the memory controller chiplet can facilitate error correction...  
WO/2022/040949A1
A method of cache programming of a NAND flash memory in a triple-level-cell (TLC) mode is provided. The method includes discarding a lower page of a first programming data from a first set of data latches in a plurality of page buffers w...  
WO/2022/046318A1
Memory device systems and methods for using methods include multiple access lines arranged in a grid. Multiple memory cells are located at intersections of the access lines in the grid. Multiple drivers are included with each configured ...  
WO/2022/046044A1
Examples of a chamber for noise cancellation emitted by a cooling device operating at an operational speeds, are described.  
WO/2022/040859A1
A complementary memory cell and a production method therefor, and a complementary memory. The complementary storage cell (100) comprises a control transistor (101), a pull-up diode (201), and a pull-down diode (301); the control transist...  
WO/2022/044704A1
A magnetic tape cartridge comprising a case in which a magnetic tape on which a plurality of servo bands are formed is accommodated, and a storage medium provided in the case, wherein the plurality of servo bands are formed along a direc...  
WO/2022/046304A1
A memory system (10) is provided. The memory system (10) includes a memory system (22) and a data bus (24) electrically coupled to the memory system (22). The memory system (10) further includes one or more memory devices (12, 14, 16) co...  
WO/2022/046288A1
Static random access memory (SRAM) bit cells employing asymmetric width read and write word lines (WWL) for reduced memory write latency and improved memory write access performance, and related fabrication methods are disclosed. In exem...  
WO/2022/047062A1
Memory subword driver circuits with common transistors are disclosed. In some examples, a subword driver block of a memory device includes a plurality of subword drivers each having an output configured to be coupled to a word line coupl...  
WO/2022/046371A1
Approaches are provided for implementing hardware-software collaborative address mapping schemes that enable mapping data elements which are accessed together in the same row of one bank or over the same rows of different banks to achiev...  

Matches 251 - 300 out of 661,464