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Patent Searching and Data


Matches 301 - 350 out of 863,225

Document Document Title
WO/2021/010490A1
This sputtering target for a magnetic recording medium comprises: a metallic phase including at least one selected from among Mn and V, and Pt, with the balance comprising Co and inevitable impurities; and an oxide phase containing at le...  
WO/2021/011132A1
Techniques herein may allow a row of a subarray in a bank of a memory device to be activated before a precharge operation has been completed for a previously opened row of memory cells in the same bank. Each subarray within the bank may ...  
WO/2021/004543A1
Disclosed are a range information encoding and matching method, and a computer storage medium. The method comprises: acquiring a new basic range, wherein the new basic range is used for decomposing range information of an entry stored in...  
WO/2021/006012A1
Provided is a photosensitive composition capable of realizing further improvement in diffraction characteristics. The present technology provides a photosensitive composition containing at least a compound represented by general formula ...  
WO/2021/006970A1
Methods, systems, and devices for input/output line sharing for memory subarrays are described. I/O lines may be shared across subarrays, which may correspond to separate memory tiles. The sharing of I/O lines may allow an I/O line to ca...  
WO/2021/007169A1
Methods, systems, and devices for circuitry borrowing in memory arrays are described. In one example, a host device may transmit an access command associated with data for a first memory section to a memory device. The first memory secti...  
WO/2021/006969A1
Methods, systems, and devices for circuit partitioning for a memory device are described. In one example, a memory device may include a set of memory tiles that each include a respective array of memory cells (e.g., in an array level or ...  
WO/2021/004342A1
Disclosed in the present invention are a method and system for obtaining a threshold voltage of a data interface, relating to the technical field of communications. By scanning a signal eye pattern to extract valid voltage pairs falling ...  
WO/2021/005956A1
The OTP readout circuit is provided with: an OTP circuit (1a) having a first OTP cell such that data can be programmed only once; and a read-possible signal output part (2) for generating a read-possible voltage for readout of the data a...  
WO/2021/007246A1
A method for generating mastered audio content, the method comprising obtaining an input audio content comprising a number, M1, of audio signals, obtaining rendered presentation of the input audio content, the rendered presentation compr...  
WO/2021/007299A1
Described are circuits and techniques to increase the efficiency of radio-frequency (rf) amplifiers including rf power amplifiers (PAs) through "supply modulation" (also referred to as "drain modulation" or "collector modulation"), in wh...  
WO/2021/002387A1
This storage device unit comprises: a substrate that has a main surface, and that has a plurality of laminated wiring layers; and a storage device that has a plate shape having a first surface, the storage device being such that the firs...  
WO/2021/002995A1
In an example, an apparatus can include an array of variable resistance memory cells and a neural memory controller coupled to the array of variable resistance memory cells and configured to apply a sub-threshold voltage pulse to a varia...  
WO/2019/240893A8
A method and apparatus are disclosed for reducing the coupling that otherwise can arise between word lines and control gate lines in a flash memory system due to parasitic capacitance and parasitic resistance. The flash memory system com...  
WO/2021/002933A1
The described technology provides a method for dynamically adjusting operating voltage of a device, including receiving device characteristics data related to a device, performing a margining test for the device to generate a performance...  
WO/2021/002176A1
This non-volatile memory device comprises: a memory unit that stores data in a non-volatile manner; a power supply unit that generates an internal voltage and supplies the internal voltage to the memory unit; a control unit that controls...  
WO/2021/002178A1
The present invention provides: a magnetic disk; and a compound which enables the achievement of a lubricant that exhibits particularly excellent heat resistance and particularly excellent solubility in a fluorine-based solvent. A perflu...  
WO/2021/002648A1
The objective of the present invention is to provide a photopolymer composition comprising: a polymer matrix having a predetermined chemical structure or a precursor thereof; a photoreactive monomer; and a photoinitiator, a holographic r...  
WO/2021/000748A1
Provided is a magnetic tunnel junction, comprising a reference layer, a tunnel layer, a free layer, a covering layer, a polarization layer, and a first coupling layer that are sequentially arranged in a stacked manner, wherein the refere...  
WO/2021/002985A1
Described are mechanisms and methods for amortizing the cost of address decode, row-decode and wordline firing across multiple read accesses (instead of just on one read access). Some or all memory locations that share a wordline (WL) ma...  
WO/2021/003085A1
An apparatus may include multiple memory devices. Each memory device may include multiple memory banks. Addresses of accessed word lines for a particular portion of memory and the number of times those word lines are accessed may be trac...  
WO/2021/002990A1
A charge sharing Compute In Memory (CIM) may comprise an XNOR bit cell with an internal capacitor between the XNOR output node and a system voltage. Alternatively, a charge sharing CIM may comprise an XNOR bit cell with an internal capac...  
WO/2021/002883A1
A ReRAM memory cell includes a ReRAM element, a programming circuit coupled to the ReRAM element and defining a programming circuit path in the ReRAM memory cell, and an erase circuit coupled to the ReRAM element and defining an erase ci...  
WO/2021/003147A1
An example apparatus can include a memory array and a memory controller. The memory array can include a first portion including a first plurality of memory cells. The memory array can further include a second portion including a second p...  
WO/2021/003190A1
Memory components can be determined to store one or more stripes of data. Data for one or more stripes of data can be stored based on the determined memory components. An indication that an endurance condition of the memory components ha...  
WO/2021/000272A1
A shift register unit, a driving method therefor, and an apparatus. The shift register unit comprises: an input circuit (10), a node control circuit (20), a first control output circuit (30), a second control output circuit (40), and an ...  
WO/2021/000372A1
A magnetic random access memory (MRAM) device and a manufacturing method therefor, and an electronic device comprising an MRAM. The MRAM device may comprise a first number of first MRAM cells and a second number of second MRAM cells, whe...  
WO/2021/000092A1
Disclosed is a data processing method, comprising: acquiring a first read disturb count value of a flash memory block; if the first read disturb count value is not greater than a first threshold and falls within an adjustment interval, a...  
WO/2021/002950A1
Disclosed herein are mechanisms and methods for reducing power consumed by various DRAM technologies (e.g., high-capacity DRAM and/or 3D DRAM) which may impact battery life of the platform. These mechanisms and methods may opportunistica...  
WO/2021/003017A1
Methods, systems, and devices for memory cell selection to enable a memory device to select a targeted memory cell during a write operation are described. The memory device may apply a first pulse to a selected bit line of the targeted m...  
WO/2021/002965A1
Described herein is a user interface and method for playback of a highlight video comprising a plurality of video segments. The user interface has one or more of: 1) an area for displaying playback of video; 2) a plurality of segment sec...  
WO/2020/260849A1
A multiply-accumulate method and architecture are disclosed. The architecture includes a plurality of networks of non-volatile memory elements arranged in tiled columns. Logic digitally modulates the equivalent conductance of individual ...  
WO/2020/223742A3
A computer process provide for users employing a conversation program to dynamically program automated assistants with information and processes that can later be invoked to accomplish task(s) on one or more of the users' devices. The co...  
WO/2020/263319A1
A method and system are provided for reading a non-transitory memory array. When a default read operation is performed and has failed, a dynamic sensing bit line voltage (VBLC) enhanced read or a dynamic sense time read is performed. Acc...  
WO/2020/263655A1
The disclosed computer-implemented method may include receiving, as an input, segmented video scenes, where each video scene includes a specified length of video content. The method may further include scanning the video scenes to identi...  
WO/2020/263583A1
Methods, apparatuses, and systems for repairing defective memory cells in regions of a memory array associated with high or low priority levels are disclosed. A repair address generator may be configured to generate a memory address map ...  
WO/2020/263927A1
Systems and methods, e.g., optical apparatuses, for digital optical information storage systems that improve the speed, signal to noise, controllability, and data storage density for fluorescent and reflective multilayer optical data sto...  
WO/2020/263340A1
A ferroelectric memory unit cell includes a series connection of select gate transistor that turns the ferroelectric memory unit cell on and off, and a ferroelectric memory transistor. Data is stored in a ferroelectric material layer of ...  
WO/2020/260848A1
In a particular implementation,a method of storing dynamic random-access memory (DRAM) data in respective magneto-electric magnetic tunnel junctions (ME-MTJ) of D-MRAM bit-cells of a D-MRAM bit-cell memory array, the method comprising:fo...  
WO/2020/263338A1
A memory cell includes a ferroelectric memory transistor, and a select gate transistor which shares a common semiconductor channel, a common source region and a common drain region with the ferroelectric memory transistor. The select gat...  
WO/2020/263330A1
A methodology and structure for a bit line boost during a programming operation in a nonvolatile memory are described. The inhibit bit line is driven for a first precharge time period with a constant current. The program bit line boost i...  
WO/2020/227451A4
A method for forming a diamond-like carbon (DLC) coating on an article is provided, comprising: alternatingly performing a deposition process and an ashing process on the article a determined number of times, wherein during the depositio...  
WO/2020/258360A1
Provided are a compute-in-memory chip and a memory unit array structure. The memory unit array comprises: multiple memory unit sub-arrays arranged in an array. The memory unit sub-arrays comprise: multiple switch units and multiple memor...  
WO/2020/262702A1
When processing the shape of the end face of a disk-shaped glass plate using a laser beam, the disk-shaped glass plate is caused to float above the base in order to suppress distortion (retardation value) in the main surface of the glass...  
WO/2020/263313A1
In non-volatile memory circuit, the area devoted to the cache buffer of the read and write circuitry is reduced through the sharing of data latches. In an array structure where memory cells are connected along bit lines, and the bit line...  
WO/2020/263360A1
A phase change memory cell includes a first electrode, a second electrode located over the first electrode, a vertical pillar structure located between the first and second electrodes, the pillar structure containing a first phase change...  
WO/2020/263586A1
A memory sub-system configured to manage programming mode transitions to accommodate a constant size of data transfer between a host system and a memory sub-system. The memory sub-system counts single-page transitions of atomic programmi...  
WO/2020/263318A1
A magnetoresistive random access memory (MRAM) memory cell comprises a pinned layer having fixed direction of magnetization that is perpendicular to a plane of the pinned layer, a first free layer having a direction of magnetization that...  
WO/2020/263329A1
A methodology and structure for driving a selected wordline to a negative voltage without the need for a negative wordline voltage generator. The methodology includes the step of boosting a non-selected wordline to a first positive volta...  
WO/2020/263339A1
A memory device includes a semiconductor channel extending between a source region and a drain region, a plurality of pass gate electrodes, a plurality of word lines, a gate dielectric located between the semiconductor channel and the pl...  

Matches 301 - 350 out of 863,225