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Patent Searching and Data


Matches 301 - 350 out of 661,464

Document Document Title
WO/2022/042100A1
Embodiments of the present application provide a memory adjusting method, an adjusting system, and a semiconductor device. The memory adjusting method comprises: obtaining a mapping relationship among the temperature of a transistor, a g...  
WO/2022/046237A1
A magnetic memory device includes a first electrode, a second electrode, and a layer stack located between the first electrode and the second electrode. The layer stack includes a reference layer, a tunnel barrier layer, a free layer, an...  
WO/2022/046440A1
Methods, systems, and devices for techniques for error detection and correction in a memory system are described. A host device may perform an error detection procedure on data received from the memory device, in addition to one or more ...  
WO/2022/041855A1
A data reading/writing apparatus and an electronic device, relating to the field of data storage, and capable of improving data reading/writing performance. The data reading/writing apparatus comprises: a first laser (201) used for outpu...  
WO/2022/047266A1
Described apparatuses and methods provide automated error correction with memory refresh. Memory devices can include error correction code (ECC) technology (306) to detect or correct one or more bit-errors in data. Dynamic random-access ...  
WO/2022/047403A1
A memory processing unit (MPU) can include a first memory, a second memory, a plurality of processing regions and control logic. The first memory can include a plurality of regions. The plurality of processing regions can be interleaved ...  
WO/2022/043726A1
The present disclosure relates to a method for operating a non-volatile memory, the method comprising obtaining a plurality of temperature values of at least one region of the non-volatile memory, each temperature value being obtained at...  
WO/2022/042014A1
A word line drive circuit defect testing method and apparatus. The method comprises: selecting from a memory cell array and a word line drive circuit array corresponding thereto m word lines as word lines to be tested, setting one of the...  
WO/2022/044433A1
This information processing device: receives a consistency level that is designated by a user and that indicates the level of consistency of data among a plurality of storage pools constituted from a plurality of magnetic tapes; performs...  
WO/2022/047040A1
Described apparatuses and methods provide error correction code (ECC) circuitry (112) that is shared between two or more memory banks (404) of a memory, such as a low-power dynamic random-access memory (DRAM). A memory device (110) may i...  
WO/2022/046386A1
A microelectronic device comprises first digit lines, second digit lines, and multiplexer devices. The first digit lines are coupled to strings of memory cells. The second digit lines are coupled to additional strings of memory cells. Th...  
WO/2022/037198A1
A method and apparatus for repairing fail bits, relating to the technical field of integrated circuits, and able to be applied to a scenario in which fail bits in a chip are to be repaired. The method comprises: determining regions to be...  
WO/2022/037197A1
Provided are a method and apparatus for determining a failed-bit repair scheme, which relate to the technical field of integrated circuits and which can be applied to a scenario of repairing a failed bit in a chip. The method for determi...  
WO/2022/039940A1
A system includes a processing device and trigger circuitry to signal the processing device responsive, at least in part, based on a determination that a trigger event has occurred. The system can further include a memory device communic...  
WO/2022/039979A1
Methods, systems, and devices for enhanced data reliability in multi-level memory cells are described. For a write operation, a host device may identify a first set of data to be stored by a set of memory cells at a memory device. Based ...  
WO/2022/037199A1
A method and apparatus for repairing fail bits, relating to the technical field of integrated circuits, and able to be applied to a scenario in which fail bits in a chip are to be repaired. The method comprises: determining regions to be...  
WO/2022/037225A1
A memory, comprising a plurality of storage groups, first signal lines, and second signal lines. The plurality of storage groups are arranged along a first direction; each storage group comprises a plurality of storage blocks that are ar...  
WO/2022/039780A1
A method includes storing configuration files of a Multi-Core Neural Network Inference (MCNNI) model having Independent Categorized-Core-Portions (ICCP's). Each ICCP corresponds to one of a plurality of categories for each parameter. A f...  
WO/2022/036575A1
A method for accessing memory cells of a three-dimensional memory comprising a plurality of bottom cell blocks, a plurality of top cell blocks, a plurality of bottom cell bit lines coupled to the bottom cell blocks, a plurality of top ce...  
WO/2022/039458A1
A multifunctional convergence computer according to the present invention comprises: a case; an electronic component mounted in the case to perform a computer function; a wireless charger installed on the upper surface of the case; an ai...  
WO/2022/040028A1
Apparatuses, systems, and methods for ferroelectric memory (FeRAM) cell operation. An FeRAM cell may have different charge regions it can operate across. Some regions, such as dielectric regions, may operate faster, but with reduced sign...  
WO/2022/039929A1
A method includes writing received data sequentially to a particular location of a cyclic buffer of a memory device according to a first set of threshold voltage distributions. The method further includes performing a touch up operation ...  
WO/2022/039945A1
Described are integrated circuits for equalizing parallel write-data and address signals from a memory controller. The integrated circuits each include a set of decision-feedback equalizers, one equalizer for each received signal. Each e...  
WO/2022/037201A1
A method and apparatus for repairing fail bits, relating to the technical field of integrated circuits, and able to be applied to a scenario in which fail bits in a chip are to be repaired. The method comprises: determining regions to be...  
WO/2022/037977A1
The present description relates to a method for processing television multimedia content data, the method being implemented by at least one device configured to execute a specific application, the device being connected to a memory capab...  
WO/2022/036648A1
Disclosed is a mechanical hard disk drive heating circuit. The mechanical hard disk drive heating circuit (100) comprises a heating film module (10), a first switch module (30), a temperature measurement module (20), and a control module...  
WO/2022/036540A1
A three-dimensional memory including bit line contacts arranged in two portions, a first portion of bit line contacts coupled to the bit lines at positions proximate a first edge of the array of memory cells and a second portion of bit l...  
WO/2022/036623A1
A non-external magnetic field oriented spin flip SOT-MRAM and an array. The SOT-MRAM comprises in sequence from top to bottom: a gating device (1) for turning the SOT-MRAM on or off under the action of an external voltage; a magnetic tun...  
WO/2022/040003A1
An apparatus for power supply mode switching includes a first voltage regulator to output a first voltage, a second voltage regulator to output a second voltage, a third voltage regulator to output a third voltage, an electronic load, a ...  
WO/2022/039079A1
A fluorine-containing ether compound represented by formula (1). (1) R1-O-R2-CH2-R3-CH2-R4-R5 (in which R3 is a perfluoropolyether chain, R1 is a C2–8 alkenyl group or a C3–8 alkynyl group, R2 and R4 are each independently a bivalent...  
WO/2022/038355A1
A tonearm (200a; 200b; 200c; 200d; 200e) including an elongate member (8a; 8b; 8c; 8d; 8e), a suspension means (4a, 5a; 4b, 5b; 4c, 5c; 4d, 5d; 4e, 5e), a protrusion (1a; 1b; 1c; 1d; 1e) and a contact surface (2a; 2b; 2c; 2d; 2e). The su...  
WO/2022/038611A1
Devices for sensing and manipulating magnetic fields based on spin current interactions independent of the Spin Hall Effect (SHE) in heavy metal. Spin current is generated in ordinary metals by conversion of out-of-plane orbital current ...  
WO/2022/039813A1
Apparatuses and techniques are described for providing separate source regions in the substrate below a block of memory cells. The source regions can be separately driven by respective voltage drivers to provide benefits such as more uni...  
WO/2022/037022A1
An online parallel processing soft error real-time error detection and recovery method and system. The method comprising: dividing a protected RAM space into multiple protected areas; dividing all of the protected areas into one or more ...  
WO/2022/034873A1
The present invention addresses the problem regarding particle generation in a Fe-Pt-BN-based sputtering target having a high relative density. This Fe-Pt-BN-based sputtering target is characterized by containing carbon (C) and boron oxi...  
WO/2022/032967A1
A sense amplifier, a memory device, and a control method for the sense amplifier, relating to the technical field of semiconductor memory devices. The sense amplifier (1) comprises an amplification module (11) and a control module (12) w...  
WO/2022/035986A1
A variety of applications can include memory devices designed to provide stabilization of selector devices in a memory array of the memory device. A selector stabilizer pulse can be applied to a selector device of a string of the memory ...  
WO/2022/032965A1
A sense amplifier (1), a memory, and a control method for a sense amplifier (1), which relate to the technical field of semiconductor memories. The sense amplifier (1) comprises: an amplification module (11); and a control module (12), w...  
WO/2022/035958A1
The present disclosure includes apparatuses, methods, and systems for multi-state programming of memory cells. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the p...  
WO/2022/036008A1
An imaging system for performing a hybrid spiral scan pattern includes a scanner, a scanner controller in communication with the scanner to direct the scanner to perform a hybrid spiral scan pattern, wherein the hybrid spiral scan patter...  
WO/2022/035955A1
The present disclosure includes apparatuses and methods for programming memory cells using asymmetric current pulses. An embodiment includes a memory having a plurality of self-selecting memory cells, and circuitry configured to program ...  
WO/2022/032489A1
Three-dimensional memory architecture has a new replacement bit line and word line scheme. In a 2 stack array, a top word line (WL) is formed in a self-aligned scheme with low resistivity copper, while a bottom bit line (BL) is formed wi...  
WO/2022/032551A1
Aspects of the disclosure provide a semiconductor memory device. The semiconductor memory device includes a memory cell array and peripheral circuitry coupled with the memory cell array. The memory cell array includes a plurality of memo...  
WO/2022/033800A1
The present invention relates to a method for recording data in a layer of a ceramic material and to a device for recording data in a layer of a ceramic material.  
WO/2022/035488A1
An active termination circuit comprising an input node connected to a transmission line, a first transistor, and a second transistor. The transmission line supplies a signal to the input node. The first transistor is diode connected betw...  
WO/2022/035522A1
Apparatuses and methods can be related to implementing a transformer neural network in a memory. A transformer neural network can be implemented utilizing a resistive memory array. The memory array can comprise programmable memory cells ...  
WO/2022/034335A1
A voice controlled studio apparatus comprising a presenter interface unit and a producer interface unit, the presenter interface unit and the producer interface unit each adapted to generate commands and each unit comprising a voice inpu...  
WO/2022/035892A1
Control logic in a memory device initiates an erase operation on a memory array and causes an erase voltage signal to be applied to a source terminal of a string of memory cells in a data block of the memory array during the erase operat...  
WO/2022/032562A1
Embodiments of the present application provide a storage unit and a related device. A first electrode of a first MTJ comprised in the storage unit is connected in series to a first electrode of a second MTJ by means of a first metal wire...  
WO/2022/032512A1
A three-dimensional memory including a top cell array of memory cells, an an upper-middle cell array of memory cells, a lower-middle cell array of memory cells, and a bottom cell array of memory cells. The memory has a multiple of top ce...  

Matches 301 - 350 out of 661,464