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WO/2023/249717A1 |
The memory device includes a plurality of memory blocks that can individually operate in either a multi-bit per memory cell mode or a single-bit per memory cell mode. Certain voltage parameters during programming and reading are shared b...
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WO/2023/207216A9 |
A shift register (ASG), a gate drive circuit (141), a display panel (10) and an electronic device. The shift register (ASG) comprises: a node control module (142), which is electrically connected to a first level signal receiving end (VG...
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WO/2023/245942A1 |
An SSD finite window data deduplication identification method and apparatus, a computer device, and a storage medium. The method comprises: if a command is a write command, allocating a write buffer area and receiving data from a host, d...
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WO/2023/249738A1 |
Computer memory arrays employing memory banks and integrated serializer/de-serializer circuits for supporting serialization/de-serialization of read/write data in burst read/write modes, and related methods are disclosed. The memory arra...
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WO/2023/250032A1 |
Technologies and implementations for a wake-up circuit. The wake-up circuit may be configured to reduce a peak value of current draw during waking up of an electronic device. The reduction of the peak value of current draw facilitates a ...
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WO/2023/249703A1 |
The present disclosure generally relates to a magnetic recording head comprising a spintronic device. The spintronic device is disposed between a main pole and a trailing shield of the magnetic recording head. The spintronic device compr...
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WO/2023/245729A1 |
Provided in the embodiments of the present disclosure are an impedance calibration circuit, an impedance calibration method and a memory. The impedance calibration circuit comprises a parameter module, an initial value generation module ...
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WO/2023/245765A1 |
Provided in the embodiments of the present disclosure are a data receiving circuit, a data receiving system and a storage apparatus. The data receiving circuit comprises: a first amplification module, which is configured to receive a dat...
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WO/2023/245750A1 |
Provided in the embodiments of the present disclosure are a data receiving circuit, a data receiving system and a storage apparatus. The data receiving circuit comprises: a first amplification module, which is configured to receive a dat...
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WO/2023/245863A1 |
The present disclosure provides a data receiving circuit, a data receiving system, and a storage device. The data receiving circuit comprises: a receiving module configured to receive a data signal and a reference signal, compare the dat...
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WO/2023/245920A1 |
Provided in the present disclosure are a word line driving circuit, a word line driver and a storage apparatus. The word line driving circuit comprises: at least two sub-word-line drivers, which are connected to a main word line and a su...
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WO/2023/249719A1 |
The memory device includes a memory block with an array of memory cells. The memory device also includes control circuitry that is in communication with the memory cells. The control circuitry is configured to program a group of the memo...
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WO/2023/245922A1 |
The present disclosure provides a single-loop memory device, a double-loop memory device, and a ZQ calibration method. The single-loop memory device comprises a master chip and a plurality of slave chips each provided with a first transm...
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WO/2023/245822A1 |
Embodiments of the present disclosure provide a test structure, a formation method therefor and a semiconductor memory. The test structure comprises multiple word lines and multiple bit lines, and a vertical transistor is formed at the i...
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WO/2023/245925A1 |
Provided are a memory device and a ZQ calibration method. The memory device comprises: two calibration resistor interfaces, which are connected to the same ZQ calibration resistor; and a first master chip, first slave chips, a second mas...
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WO/2023/245749A1 |
Provided in the embodiments of the present disclosure are a data receiving circuit, a data receiving system and a storage apparatus. The data receiving circuit comprises: a first amplification module, which is configured to receive a dat...
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WO/2023/245727A1 |
Embodiments of the present application provide a random data generation circuit and a read-write training circuit. The random data generation circuit comprises: a first shift register and a second shift register, the first shift register...
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WO/2023/250394A1 |
A digital neutron and photon track dosimeter based on three-dimensional Not-And (3D NAND) flash memory may be provided. A plurality of logical addresses respectively associated with a plurality of cells in a 3D NAND flash memory that hav...
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WO/2023/245785A1 |
Embodiments of the present disclosure provide a semiconductor device, and a data processing circuit and method. A chip select signal and a plurality of command signals are received by means of an input end of the data processing circuit,...
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WO/2023/249826A1 |
A data processor is for accessing a memory having a first pseudo channel and a second pseudo channel. The data processor includes at least one memory accessing agent, a memory controller, and a data fabric. The at least one memory access...
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WO/2023/244866A1 |
A method for capturing real-time motion data events from a remotely deployed far edge compute node on a remote asset, such as a racing vehicle, allows for real-time motion simulation of a racing experience. In the method, incoming audio ...
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WO/2023/240513A1 |
Embodiments of this application provide a shift register, a shift register circuit, a display panel, and an electronic device. The shift register includes an input circuit, a bootstrapping circuit, and an output circuit, wherein the inpu...
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WO/2023/241433A1 |
A memory device includes a memory array and a peripheral circuit coupled to the memory array. The memory array includes a vertical transistor having a first terminal and a second terminal, a storage unit having a first end coupled to the...
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WO/2023/025035A9 |
Aspects of the present disclosure relate to a method for reducing repositioning time within tape systems. A request to reposition to a target file within a tape medium can be received. A determination can be made that a previous command ...
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WO/2023/245204A1 |
The present disclosure relates to resistive random-access memory (RRAM) devices. In some embodiments, an RRAM device includes: a first electrode; a second electrode comprising a first conductive material; and a switching oxide layer posi...
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WO/2023/245205A1 |
The present disclosure relates to resistive random-access memory (RRAM) devices. In some embodiments, an RRAM device includes: a first electrode including a metal nitride; a second electrode comprising a first conductive material; and a ...
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WO/2023/240676A1 |
Provided in the embodiments of the present disclosure are a data processing circuit and method, and a semiconductor memory. The data processing circuit comprises a receiving module, a first power supply module and a processing module, wh...
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WO/2023/240767A1 |
Provided in the present disclosure are a memory chip evaluation method and apparatus, a memory chip access method and apparatus, and a storage medium. The evaluation method comprises: testing a preset number of memory chips under test; c...
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WO/2023/241295A1 |
Disclosed in the embodiments of the present application are a ferroelectric memory and a manufacturing method for a ferroelectric memory. The ferroelectric memory comprises a storage array, the storage array comprises X rows * Y columns ...
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WO/2023/240728A1 |
The present invention relates to the technical field of storage. Provided are a programmable memory and a driving method therefor. The programmable memory comprises: a plurality of anti-fuse units, a plurality of word lines and a control...
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WO/2023/244335A1 |
A storage system has an inference engine that can infer a read threshold based on a plurality of parameters of the memory. The read threshold can be used in reading a wordline in the memory during a regular read operation or as part of a...
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WO/2023/242665A1 |
Provided is a semiconductor device having a novel configuration. This semiconductor device comprises a first element layer, and a plurality of second element layers on each of which a temperature detection circuit, a voltage generation c...
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WO/2023/241161A1 |
Provided in the present invention are an antiferromagnetic magnetic random access memory device and a manufacturing method therefor. The device comprises a ferromagnetic thin-film structural body, an antiferromagnetic thin-film structura...
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WO/2023/244907A1 |
The disclosed computer-implemented method may include systems and methods for automatically generating sound event subtitles for digital videos. For example, the systems and methods described herein can automatically generate subtitles f...
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WO/2023/242956A1 |
This memory device includes a page composed of a plurality of memory cells arranged on a substrate in a columnar configuration as seen in a plan view, and hole groups generated by the impact ionization phenomenon are retained inside a ch...
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WO/2023/244915A1 |
A memory includes a local control circuitry that manages refresh transactions using a set of sense amplifiers separate from those used for access (read and write) transactions. The local control circuitry interrupts refresh transactions ...
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WO/2023/244986A1 |
A method for providing a shareable media hosting platform includes recording, by a user device, multiple video segments corresponding to a narrative of a user. The method further includes storing, in a memory, the multiple video segments...
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WO/2023/240952A1 |
A data information storage method based on recombinant plasmid DNA molecules. A recombinant plasmid library is composed of universal information storage DNA recombinant plasmids, and the plasmids in the plasmid library record, by using c...
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WO/2023/244272A1 |
A method includes obtaining a video having image frames, and determining, for each respective image frame, a corresponding frame content score based on a visual content thereof. The method also includes selecting, from the image frames, ...
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WO/2023/244583A1 |
A selector for a memory cell in a memory array may operate by opening different conductive paths to high and low voltages during set and reset operations. A first transistor may open a conductive path between a high voltage and a termina...
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WO/2023/242668A1 |
Provided is a novel semiconductor device. In the present invention, a first circuit is electrically connected to a second circuit via a first wire, the first circuit is electrically connected to a fourth circuit via each of a third wire ...
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WO/2023/244361A1 |
A method and system for uploading a media file container from a first device to a second device are described herein, including receiving an instruction to upload the media file container and in response, reading a metadata box of the me...
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WO/2023/244473A1 |
A controller iteratively activates a control signal for one-half a clock cycle while sweeping its phase relationship to the rising edge of the clock. Phase relationships that result in the rising edge of the clock occurring while the con...
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WO/2023/236245A1 |
The present disclosure provides a logic analysis decoding method, comprising the following steps: acquiring a sampling file of a memory circuit block, and generating an instruction sequence file of the memory circuit block, the sampling ...
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WO/2023/239486A1 |
A memory is provided with a plurality of column groups and two redundant column groups. If there are two defective columns in the plurality of column groups, the plurality of column groups may be divided into a no-shift region, a one-shi...
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WO/2023/239556A1 |
In an embodiment, a method includes: receiving a first program bit address associated with a plurality of redundant bit addresses and a first transistor-based memory cell, where the plurality of redundant bit addresses are each associate...
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WO/2023/236268A1 |
A bit breakdown condition determining method and device. The method comprises: determining a plurality of first breakdown conditions (S101); breaking down, according to each first breakdown condition, a corresponding first bit respective...
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WO/2023/236269A1 |
Provided in the embodiments of the present disclosure are a phase adjustment circuit, a delay-locked circuit and a memory. The phase adjustment circuit comprises a measurement module, a comparison module, a counting module and an adjustm...
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WO/2023/236528A1 |
The present application discloses a hard disk head and a preparation method therefor, and a hard disk. The top end of a super-lubricity gasket of the hard disk head is fixedly connected to the bottom of a head slider by means of an adhes...
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WO/2023/236258A1 |
The embodiments of the present disclosure relate to the field of semiconductors. Provided is a memory system. The memory system comprises: a basic chip and a plurality of stacked memory chips, wherein each memory chip comprises a plurali...
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