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Patent Searching and Data


Matches 401 - 450 out of 661,464

Document Document Title
WO/2022/020140A1
Apparatuses and methods can be related to implementing edge compute components in a memory array. Compute components can be implemented under a memory array. Implementing compute components under a memory array can limit control access t...  
WO/2022/020235A1
The disclosed computer-implemented method may include (1) accessing a first media data object and a different, second media data object that, when played hack, each render temporally sequenced content, (2) comparing first temporally sequ...  
WO/2022/018914A1
A magnetic tape device comprising: a magnetic head including a magnetic element which approaches and acts on a magnetic layer formed on a surface of a magnetic tape; and a supporting member which is arranged at a position opposed to the ...  
WO/2022/020131A1
A method for performing stutter of dynamic random access memory (DRAM) where a system on a chip (SOC) initiates bursts of requests to the DRAM to fill buffers to allow the DRAM to self-refresh is disclosed. The method includes issuing, b...  
WO/2022/016476A1
A bit line read circuit and a memory. When the bit line read circuit reads a level from a memory cell, two sense amplifiers operate synchronously; after the sense amplifiers performs differential amplification on voltages on a bit line a...  
WO/2022/018915A1
A magnetic tape unit equipped with: a magnetic head which has a magnetic device which acts on a magnetic layer formed on a surface of the magnetic tape; a position adjustment actuator which, by moving the magnetic head, adjusts the posit...  
WO/2022/018913A1
The present invention provides a magnetic tape device comprising a magnetic head having a magnetic element that acts on a magnetic layer formed on an obverse surface of a magnetic tape, and a guide member that is arranged in a position f...  
WO/2022/020119A1
Semiconductor die stacks, and associated methods and systems are disclosed. The semiconductor die stack may include a first die with a memory array and a second die with CMOS circuitry configured to access the memory array. The first die...  
WO/2022/020494A1
A process for manufacturing a 3-D NOR memory array provides thin-film storage transistors of each NOR memory string in either shafts or portions of a trench between adjacent shafts.  
WO/2022/016233A1
An apparatus for electromagnetic characterisation of internal features of an object, including a lens for placement between a source of electromagnetic energy and the object, the lens being composed of a first material having a first per...  
WO/2022/017324A1
A tamper-resistant memory is formed by placing a solid-state memory array between metal wiring layers in the upper portion of an integrated circuit (back-end of the line). The metal layers form a mesh that surrounds the memory array to p...  
WO/2022/016341A1
Embodiments of the present application relate to the technical field of laser detection, and provide a signal processing method and apparatus, which can be applied to autonomous driving or assisted driving. The embodiments of the present...  
WO/2022/020118A1
A semiconductor memory stack connected to a processing unit, and associated methods and systems are disclosed. In some embodiments, the semiconductor memory stack may include one or more memory dies attached to and carried by a memory co...  
WO/2022/018882A1
The purpose of the present invention is to provide a magnetic recording medium capable of suppressing dimensional changes in a width direction by making the water vapor transmission rate lie within a specific range. The present technolog...  
WO/2022/020013A1
A bonded assembly includes a first three-dimensional memory die containing a first alternating stack of first insulating layers and first electrically conductive layers and first memory structures located in the first alternating stack, ...  
WO/2022/018950A1
The memory system according to an aspect of the present disclosure is provided with a soft error generation unit that generates write data or readout data in which a probabilistic defect is considered by using a random number.  
WO/2022/016313A1
A cache device and a manufacturing method therefor, applied to the technical field of caches. The cache device comprises a first field-effect transistor (10), a magnetic tunnel junction, an electrode (17), and a second field-effect trans...  
WO/2022/020139A1
Methods, systems, and devices for read operations based on a dynamic reference are described. A memory device may include a set of memory cells each associated with a capacitive circuit including a first and second capacitor. After recei...  
WO/2022/018904A1
The purpose of the present invention is to provide a magnetic recording medium with which it is possible to minimize a dimensional change in the width direction by having water vapor transmission be within a specific range. The present t...  
WO/2022/019522A1
The present invention relates to a three-dimension flash memory to which an efficient word line connection structure is applied, and a method for manufacturing same, wherein a plurality of word lines are connected to a low decoder respec...  
WO/2022/020502A1
A process for building a 3-Dimensional NOR memory array avoids the challenge of etching a conductor material that is aimed at providing local word lines at a fine pitch. The process defines the local word lines between isolation shafts t...  
WO/2022/013590A1
Methods, systems, and devices for memory array with multiplexed select lines are described. In some cases, a memory cell of the memory device may include a storage component, a first transistor coupled with a word line, and a second tran...  
WO/2022/013168A2
Disclosed is a method and system of authoring an audio signal to produce an immersive haptic experience. The method and system preprocesses the audio signal in a preprocessor, which is passed to an audio analysis module. The audio analys...  
WO/2022/012255A1
The present invention relates to a test method, test system and test device for a semiconductor chip. The method comprises: acquiring a target chip; respectively carrying out read-write function test on a preset number of storage units i...  
WO/2022/012202A1
An antifuse storage unit state detection circuit (200) and a memory using same. The circuit (200) comprises: a current supply module (21), connected to a first node (N1), and used for supplying a constant current; an antifuse storage uni...  
WO/2022/013589A1
The present disclosure relates a method for an improved accessing operation of memory cells, the method comprising storing a set of user data and additional data information in a plurality of memory cells of a memory array, the additiona...  
WO/2022/011954A1
Provided is a semiconductor apparatus. The semiconductor apparatus comprises a memory chip and a temperature detection module, wherein the temperature detection module is used for detecting the temperature of the memory chip. The tempera...  
WO/2022/014529A1
Provided are a layer structure for a magnetic memory element, the layer structure having improved controllability of a drive current required for domain wall displacement and that of domain wall displacement, and a magnetic memory elemen...  
WO/2022/015963A1
This invention provides a quaternary field effect transistor with two gate electrodes for individually controlling a conductivity type of a channel region between a source and a drain, such that the quaternary field effect transistor is ...  
WO/2022/015741A1
Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a buffer to translate high speed data interactions on a host interface side into slower, wider data interactio...  
WO/2022/011956A1
A semiconductor device, comprising a plurality of memory chips (100); and a temperature detection module (110), the temperature detection module (110) comprising: a plurality of temperature sensitive units (111) provided on the memory ch...  
WO/2022/014154A1
A semiconductor device according to one embodiment of the present disclosure is provided with: a memory cell array including a plurality of first selection lines extending in a first direction, a plurality of second selection lines exten...  
WO/2022/011955A1
A semiconductor device comprises multiple memory chips (100) and a temperature detection module (110). The temperature detection module (110) comprises: multiple temperature detection units (111) disposed on at least a portion of the mem...  
WO/2022/015537A1
Methods, systems, and devices for data-based polarity write operations are described. A write command may cause a set of data to be written to a set of memory cells. To write the set of data, a write operation that applies voltages acros...  
WO/2022/015967A1
An array of high endurance memory (HEM) cells are configured in a crossbar arrangement, each HEM cell of the array being configured to perform a computation-in-memory operation. Each HEM cell of the array includes an HEM latch, a vector ...  
WO/2022/012203A1
An antifuse storage unit state detection circuit and a memory. The circuit comprises: a first current module (21), having a first end connected to an antifuse storage unit array (22) via a first node (N1), and a second end connected to a...  
WO/2022/016145A1
In at least one embodiment, a system for controlling aspects of a virtual concert is provided. The apparatus includes one or more controllers and at least one computing device. The one or more controllers are positioned in a venue and ar...  
WO/2022/013677A1
Provided is a semiconductor device having a novel configuration. A first memory circuit part has a first memory circuit that holds a plurality of pieces of first weight data. A second memory circuit part has a second memory circuit that ...  
WO/2022/012920A1
Provided are embodiments for a computer-implemented method, a system, and a computer program product for updating analog crossbar arrays. The embodiments include receiving a number used in matrix multiplication to represent using pulse g...  
WO/2022/012790A1
The present invention relates to a magnetoelectric device (D), comprising: - a magnetoelectric element (Me); and - an electric voltage source (PS) configured and arranged to induce on the magnetoelectric element (Me), at least at room te...  
WO/2022/011502A1
A storage device, an information processing method and a storage system. The storage device comprises: a storage medium for storing information; and a display module, the display module continuously displaying, in response to display inf...  
WO/2022/012269A1
An antifuse memory cell state detection circuit and a memory using same are provided. The antifuse memory cell state detection circuit comprises: a first switch element, having a first end connected to a power supply, a second end connec...  
WO/2022/012200A1
An antifuse storage unit state detection circuit (200) and a memory. The circuit comprises: an amplifier (21), having a first input end connected to a first reference voltage, a second input end connected to a first node, and an output e...  
WO/2022/016113A1
A page buffer circuit in a memory device includes a logic element configured to perform a series of calculations pertaining to one or more memory access operations and generate a plurality of calculation results associated with the serie...  
WO/2022/015463A1
Methods and systems are provided for generating a video stream for followers of an influencer during a session. The method includes capturing video images of an environment of the influencer, wherein the environment includes the influenc...  
WO/2022/014644A1
Provided is a magnetic recording medium in which it is possible to suppress reduction of travel stability even after repeated recording or replaying. The present invention is a tape-like magnetic recording medium provided with: a base ...  
WO/2022/015431A1
The present disclosure provides bit cells with data redundancy according to various aspects. In certain aspects, a bit cell includes a first memory element coupled to a write bit line, and a first write-access switch coupled between the ...  
WO/2022/015540A1
A content-creation tool includes a processor and a memory. The processor is configured to receive a first video clip and a second video clip, a respective first and second metadata-item thereof being set to a respective first and second ...  
WO/2022/010689A1
The present invention relates to the field of tape drives, tape transport, tape heads and tape head suspension. More particularly, the present invention is related to magnetic tape data storage and tape recorders that include components ...  
WO/2022/010765A1
Memory devices, systems, and associated methods with per die temperature-compensated refresh control, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory cells and a sensor conf...  

Matches 401 - 450 out of 661,464