| Document |
Document Title |
|
WO/2023/238906A1 |
A fluorine-containing ether compound represented by R1-[B]-[A]-CH2-R2[-CH2-R3-CH2-R2]z-CH2-[C]-[D]-R4 ([A] is formula (2-1). [B] is formula (2-2). [C] is formula (3-1). [D] is formula (3-2). R4 is formula (4). R1 is a terminal group that...
|
|
WO/2023/236996A1 |
The present application relates to the technical field of computers. Disclosed are a memory module and an electronic device. In the memory module, the number of DRAM particles in a rank is increased so as to reduce the number of bits of ...
|
|
WO/2023/236748A1 |
Provided in the embodiments of the present application are a power switch circuit, an electrically programmable fuse memory and an electronic device, which are applied to the technical field of data storage. The electrically programmable...
|
|
WO/2023/236831A1 |
The present invention relates to the technical field of display, and provides a display substrate and a display device. The display substrate comprises a shift register disposed on a base substrate, the shift register comprises a multi-s...
|
|
WO/2023/239301A1 |
The present disclosure describes techniques for voice-controlled content creation. The techniques comprise monitoring voice commands spoken by a creator. Recording of a content may be initiated in response to recognizing a first voice co...
|
|
WO/2023/238698A1 |
A semiconductor device according to an embodiment of the present disclosure comprises: a plurality of fuse elements; and a selection element that is provided in common in the plurality of fuse elements, and switches the plurality of fuse...
|
|
WO/2023/239471A1 |
Memory arrays employing flying bit lines to increase effective bit line length for supporting higher performance, increased memory density, and related methods. To increase memory density, the memory array has a first memory sub-bank and...
|
|
WO/2023/236304A1 |
Disclosed in the present invention are a high-speed large-current adjustable pulse circuit, and an operation circuit and operation method for a phase change memory. The high-speed large-current adjustable pulse circuit is provided with a...
|
|
WO/2023/238487A1 |
A recording medium 100 according to one aspect of the present disclosure comprises a first dielectric layer 20A, a second dielectric layer 20B, and a recording layer 10. The recording layer 10 has a recording region for recording informa...
|
|
WO/2023/231164A1 |
A semiconductor device and a memory. The semiconductor device comprises a pull-up circuit integration area (61), a pull-down circuit integration area (62), and a compensation circuit integration area (63) that do not overlap each other; ...
|
|
WO/2023/232697A1 |
According to an aspect of the present inventive concept there is provided a molecular synthesis array comprising: a substrate; an insulating layer (202) arranged on the substrate; a plurality of column lines (102) extending in parallel a...
|
|
WO/2023/230886A1 |
Provided in the present disclosure are an audio control method and control apparatus, a driving circuit, and a readable storage medium. The audio control method according to some embodiments of the present disclosure is applicable to a d...
|
|
WO/2023/231756A1 |
The present application discloses a three-dimensional stacked chip and a data processing method therefor. The three-dimensional stacked chip comprises a storage die layer and a logic die layer stacked on the storage die layer. The storag...
|
|
WO/2023/232696A1 |
According to an aspect of the present inventive concept there is provided a molecular synthesis array (100, 100') comprising: a substrate (208, 208'); an insulating layer (202, 202') arranged on the substrate (208, 208'); a plurality of ...
|
|
WO/2023/233875A1 |
A cradle 100A which is a contact operation device comprises: an arm 111 having, at the distal end thereof, a contact operation part 114 that contacts a touch panel 205; and a support part 120 supporting the arm 111, said support part 120...
|
|
WO/2023/235216A1 |
A 3D memory device includes a plurality of mats that each include a memory array stacked over logic circuitry supporting operations of the memory array. The logic circuitry include a local column decoder under the memory array for select...
|
|
WO/2023/231166A1 |
Embodiments of the present disclosure provide a fuse circuit, comprising: a fuse unit array, the fuse unit array being operated according to a received first enable signal; and an address signal generation module coupled to the fuse unit...
|
|
WO/2023/235202A1 |
A shared data strobe signal is applied to time data reception simultaneously in two or more transactionally-independent memory channels, lowering strobe signaling overhead by at least half relative to conventional strobe-per-channel solu...
|
|
WO/2023/231263A1 |
Disclosed in the embodiments of the present disclosure is a refresh address generation circuit, comprising: a refresh control circuit, a repetitive command processing circuit and an address generator. The refresh control circuit is used ...
|
|
WO/2023/231295A1 |
A refresh address generation circuit and method, and a memory and an electronic device. The refresh address generation circuit comprises a refresh control circuit (100) and an address generator (200), wherein the refresh control circuit ...
|
|
WO/2023/235115A1 |
In order to achieve tight and uniform erased threshold voltage distributions in a non-volatile memory system that includes non-volatile memory cells arranged in blocks that have multiple sub-blocks and has an erase process using gate ind...
|
|
WO/2023/235339A1 |
Systems, devices, and methods for a laser diode assembly (102) including: a laser diode (120) configured to emit a laser beam (200); and a housing (124) configured to receive at least a portion of the laser diode (120), where the housing...
|
|
WO/2023/231177A1 |
The present disclosure provides a receiving circuit and a memory. The receiving circuit comprises: an input buffer, configured to receive a first input signal and a second input signal and compare the first input signal with the second i...
|
|
WO/2023/232749A1 |
A system for the electrochemical synthesis of polymers, comprising: a. one or more reaction chambers comprising an inlet, an outlet, and a plurality of reaction sites comprising one or more individually addressable electrodes, b. a plura...
|
|
WO/2023/231090A1 |
A termination impedance parameter generation method and test system. The method comprises: when a first operation instruction is received, writing a plurality of preset control words into a first data queue in a data buffer (S201), where...
|
|
WO/2023/235157A1 |
A regeneration circuit includes a first inverting circuit and a second inverting circuit. The regeneration circuit also includes a first transistor coupled to an input of the second inverting circuit, and a second transistor coupled to a...
|
|
WO/2023/231273A1 |
Provided in the present disclosure are a test method, test equipment and a computer storage medium. The method comprises: determining an initial clock signal; generating a target clock signal on the basis of the initial clock signal; acq...
|
|
WO/2023/231223A1 |
Disclosed in the embodiments of the present disclosure is a refresh address generation circuit, comprising a refresh control circuit and an address generator. The refresh control circuit sequentially receives a plurality of first refresh...
|
|
WO/2023/235037A1 |
The present disclosure relates to systems and methods implemented on a memory controller for detecting and mitigating memory attacks (e.g., row hammer attacks). For example, a memory controller may track activations of row addresses with...
|
|
WO/2023/231276A1 |
The present invention relates to the field of very-large-scale integrated circuit testability design. Disclosed is a chiplet test circuit based on flexible configurable modules (FCMs). A circuit core structure is located in an intermedia...
|
|
WO/2023/230835A1 |
A scan circuit having a plurality of stages is provided. A respective stage includes a respective scan unit configured to provide a control signal to at least a row of subpixels. The respective scan unit includes an input subcircuit (Isc...
|
|
WO/2023/235055A1 |
Computer memory systems employing localized generation of a global bit line (GBL) clock signal to reduce clock signal read path divergence for improved signal tracking, and related methods. The memory system includes one or more memory b...
|
|
WO/2023/226112A1 |
Provided in the embodiments of the present disclosure are a refresh control circuit, a memory, and a refresh control method. The refresh control circuit comprises: a processing module which is configured to receive a refresh command sign...
|
|
WO/2023/226066A1 |
A GOA (Gate Driver On Array) circuit and a display panel. The present invention employs a first GOA unit (sGOA) of each stage of GOA module to realize upward and downward signal transmission, so as to reduce the number of thin film trans...
|
|
WO/2023/229816A1 |
A method for programming a memory array of a non-volatile memory structure, wherein the memory array comprises a population of MLC NAND-type memory cells, and the method comprises: (1) in a first program pulse, programming selected memor...
|
|
WO/2023/226417A1 |
A memory device, a memory system, and a program operation method are disclosed. In one example, at an ith programming loop, in response to determining that index i is greater than or equal to a first preset value and less than an initial...
|
|
WO/2023/225847A1 |
A shift register unit, comprising: a sensing control circuit (1), connected to a sensing signal input end (INPUT2), a random signal input end (OE), and a sensing control node (H), and configured to write a signal provided by the sensing ...
|
|
WO/2023/229815A1 |
Technology is disclosed herein for refreshing threshold switching selectors in programmable resistance memory cells in cross-point memory arrays. The Vt of the threshold switching selector may drift over time. The memory system resets th...
|
|
WO/2023/229807A1 |
A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to word lines and disposed in strings and configured to retain a threshold voltage. The memory apparatus also includes a charge p...
|
|
WO/2023/229369A1 |
A video storage apparatus according to an embodiment of the present invention comprises: a spare power source that supplies auxiliary power; a main board that selects, from videos transmitted over a network, a video to store; a video sto...
|
|
WO/2023/229009A1 |
An aspect of the present disclosure provides a grinding liquid composition that can reduce residue of silica on a substrate surface after grinding is performed, while maintaining a grinding rate.　One aspect of the present disclosure pe...
|
|
WO/2023/225704A1 |
The present invention relates generally to the field of digital content, and more particularly to an improved system and methods for producing, mixing, and recording content. In particular, the system may include a plurality of input cha...
|
|
WO/2023/226060A1 |
Provided in the present application is a counter circuit, comprising an addition module, a subtraction module and a plurality of control modules. The addition module comprises a plurality of stages of counting modules for corresponding b...
|
|
WO/2023/229840A1 |
A double data rate (DDR) physical (PHY) provides an interface between a memory controller and a dynamic random-access memory (DRAM). The DDR PHY includes a first set of core logic configured to convert data between a single data rate and...
|
|
WO/2023/229683A1 |
Techniques are described for managing video editing projects using single bundled video files. A single bundled video file is a new type of file that is in a video container format and that can be used to store and re-create a video edit...
|
|
WO/2023/227027A1 |
The present disclosure relates to the technical field of display and provides a shift register and a drive circuit and method therefor, a display panel, and a device. The shift register comprises an input unit, a first control unit, an o...
|
|
WO/2023/229524A1 |
A computing system is provided which includes a client computing device including a processor. The processor is configured to execute a client program to display a first video published by a first user on a video server platform, to a se...
|
|
WO/2023/225946A1 |
Provided in the embodiments of the present disclosure are a shift register unit, a driving control circuit, a display apparatus and a driving method. The shift register unit comprises: an input circuit, which is configured to provide an ...
|
|
WO/2023/229808A1 |
A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines. The memory cells are disposed in strings and configured to retain a threshold voltage corres...
|
|
WO/2023/226540A1 |
Provided in the present invention are a magnetic random access memory device and a manufacturing method therefor. The device comprises magnetic thin film structure bodies, and an electrode capable of applying voltage to a magnetic thin f...
|
