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Patent Searching and Data


Matches 401 - 450 out of 863,225

Document Document Title
WO/2020/250334A1
A semiconductor integrated circuit has: an output buffer that outputs a memory control signal to an external terminal; a power source control unit that controls the supply of power source voltage to the output buffer; a pull-up control u...  
WO/2020/250545A1
This on-vehicle control system is provided with: an audiovisual information output unit (5) that outputs audiovisual information to an occupant of a vehicle (C); a reproduction signal generation device (3) that generates a reproduction s...  
WO/2020/248834A1
The present invention provides a reading circuit for reading the resistance state of a storage unit, comprising: a power-on unit, a current mirror unit, and an output unit, wherein the first end of the power-on unit is connected to a rea...  
WO/2020/251708A1
Memory management and erasure decoding for a memory device are described. A memory device may identify charge leakage associated with one or more memory cells, and may determine whether to invert a logic state stored by one or more memor...  
WO/2020/248787A1
Disclosed are a data disaster recovery storage device and a carrier. The data disaster recovery storage device comprises: a housing; a fire-resistant shell; a liner; an internal data line; and a memory. The memory is connected to the int...  
WO/2020/251625A1
An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Each of the memory stack structures includes a memory film and a vert...  
WO/2020/247024A1
A methodology and structure for accounting for fabrication difference in memory holes is described. Increasing the distance of the memory holes from the sources of etchant or other fabrication material results in different characteristic...  
WO/2020/247509A2
A dual-mode memory is provided that includes a self-timed clock circuit for asserting a sense enable signal for a sense amplifier. In a low-bandwidth read mode, the self-timed clock circuit asserts the sense enable signal only once durin...  
WO/2020/246252A1
An information processing device comprising: a plate-shaped main body; and a storage unit which comprises a storage device and can be attached/detached to/from the main body. The main body comprises: a recessed housing part which is depr...  
WO/2020/247023A1
A methodology and structure for performing an erase verify in non-volatile memory is described. Both the odd wordlines and the even wordlines are driven to a high voltage level. This can be done simultaneously. The simultaneous charging ...  
WO/2020/245631A1
In various embodiments, a sound modification application selectively modifies one or more sounds included in one or more audio signals. In operation, the sound modification application determines classifications associated with multiple ...  
WO/2020/244489A1
The present disclosure provides a shift register, comprising: a pre-charging reset circuit and an output circuit, the pre-charging reset circuit being used for writing, into a pull-up node, an input signal provided by a signal input end ...  
WO/2020/247163A1
An apparatus may include a refresh control circuit with multiple timing circuits. The timing circuits may be used to control steal rates, e.g., the rate of refresh time slots dedicated to healing victim word lines of row hammers. The tim...  
WO/2020/246525A1
Provided is a card reader which is capable of generating a complex interference magnetic field by means of an interference magnetic field generation mechanism while being capable of increasing the range affected by the interference magne...  
WO/2020/247059A1
Systems, devices, and methods for generating a unique fingerprint are described herein. For example, an example integrated circuit (IC) chip includes a physically unclonable function (PUF) and an auxiliary circuit. The PUF is a hybrid Bo...  
WO/2020/247149A1
Methods, systems, and devices for scrub rate control for a memory device are described. For example, during a scrub operation, a memory device may perform an error correction operation on data read from a memory array of the memory devic...  
WO/2020/247639A1
Embodiments of the disclosure are drawn to apparatuses and methods for staggering the timing of skipped refresh operations on a memory. Memory cells of memories may need to periodically perform refresh operations. In some instances, auto...  
WO/2020/244420A1
Provided by the present disclosure are a method and apparatus for determining a movement trajectory, and an electronic device. The electronic device comprises: a body (1), a light-emitting assembly (2), a photosensitive assembly (3) and ...  
WO/2020/117348A3
Exemplary methods and apparatus are provided for implementing a deep learning accelerator (DLA) or other neural network components within the die of a non-volatile memory (NVM) apparatus using, for example, under- the- array circuit comp...  
WO/2020/247646A1
The disclosure provides a system and method for capturing and editing video from a plurality of cameras.  
WO/2020/247175A1
Provided are systems and methods for animating a single image of a human body and applying effects. An example method includes providing, by a computer device, a database of motions; receiving, by a computing device, an input image, the ...  
WO/2020/247404A1
A memory is provided with a plurality of cores that power up according to a power-up order from a first core to a final core. As the core power supply voltage for a current core powers up according to the power-up order, it triggers the ...  
WO/2020/247505A1
A memory is provided that is configured to practice both a conventional normal read operation and also a burst mode read operation. During the normal read operation, the memory pre-charges the bit lines in a group of multiplexed columns....  
WO/2020/245697A1
The present invention provides a semiconductor device with a novel structure. The semiconductor device has: a silicon substrate that has a first circuit; a first element layer that has a second circuit; and a second element layer that ha...  
WO/2020/246179A1
The present invention pertains to a light source module which projects a plurality of laser beams that have different wavelengths and are respectively emitted from a plurality of laser light sources such that the laser beams are gathered...  
WO/2020/246135A1
This optical recording medium comprises an optical recording medium main body having a first surface and a second surface, and a first uneven structural layer provided on the first surface. The first uneven structural layer includes a pl...  
WO/2020/247211A1
A request to read data from a location associated with a memory component is received. The request is assigned a first tag, the first tag having a first identifier of a first buffer to store data read from the location. The request to re...  
WO/2020/247025A1
Non-volatile, high performance memory devices balance speed and reliability, which can include channel boosting to reduce data error rates in the memory cells. Vertical NAND strings exhibit greater program disturb (errors) the higher the...  
WO/2020/245688A1
Provided is a semiconductor device with reduced power consumption. The present invention pertains to a semiconductor device including a power management unit, a CPU core, and a memory device, wherein the power management unit includes a ...  
WO/2020/244246A1
Disclosed in the present invention is a music playing device coupled to a lollipop, comprising a music playing element and a corresponding playing control device, and further comprising a disc-shaped edible sugar body and a stick inserte...  
WO/2020/247009A1
A memory cell having a structure of a modified flash memory cell, but configured to operate in a low voltage domain (e.g., using voltages of ?6V amplitude for program and/or erase operations) is provided. The disclosed memory cells may b...  
WO/2020/247077A1
Bit string accumulation in a memory array periphery is described. Control circuitry (e.g., a processing device) may be utilized to control performance of operations using bit strings within a memory device. Results of the operations may ...  
WO/2020/247277A1
The present disclosure generally relates to combinations of resistive change elements and resistive change element arrays thereof. The present disclosure also generally relates to combinational resistive change elements and combinational...  
WO/2020/246344A1
Transistors (N1, N5) that correspond to a drive transistor (PD1) are respectively formed at a cell upper part and a cell lower part. Transistors (N2, N6) that correspond to a drive transistor (PD2) are respectively formed at the cell upp...  
WO/2020/241000A1
Provided is an electronic circuit equipped with: a cell array comprising a plurality of memory cells, each of the memory cells being equipped with a bistable circuit equipped with a first inverter circuit and a second inverter circuit th...  
WO/2020/243300A1
A memory device includes a memory array arranged in rows and columns; memory cell layers at each row and column intersection, where each memory cell layer is configured to be set to a predetermined conductance state; a row control circui...  
WO/2020/242534A1
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive word line layers located over a substrate, and a plurality of vertical memory strings. Each vertical memory string includes ...  
WO/2020/240855A1
A display device (5) is provided with: a rotary body (51) that is mounted on a turntable (RP1) of a record player (RP) and that is rotated together with the turntable; and a display unit (52) that is provided on the rotary body along a c...  
WO/2020/239835A1
There are provided techniques for signal processing (e.g., for a mixed-signal beamforming and/or down-conversion receiver). The techniques may be implemented in devices (e.g., circuit arrangements), systems, methods, and/or storage units...  
WO/2020/237410A1
A reference voltage value and a chip select (CS) signal timing delay provided to memory devices can be determined based on samples of the CS signal received by the memory devices. The CS signal can be provided to the memory devices with ...  
WO/2020/240227A1
The present disclosure relates to a Flash memory portion architecture coupled to a System-on-Chip (SoC) including a matrix of memory cells with associated decoding and sensing circuitry and having a structurally independent structure lin...  
WO/2020/240186A1
There is provided a memory cell for storing one or more bits of information. The memory cell comprises a semiconductor substrate on which is provided a source terminal, a drain terminal and a channel extending between the source and drai...  
WO/2020/240241A1
The present disclosure relates to a memory device comprising: an array of memory cells; a plurality of boundary cells able to manage serial and parallel data; mixed pads connected to the memory cells through low speed paths, the mixed pa...  
WO/2020/240226A1
The present disclosure relates to method for checking the reading phase of a non-volatile memory device including at least an array of memory cells and with associated decoding and sensing circuitry and a memory controller, the method co...  
WO/2020/239806A1
The invention relates to data storage and retrieval. More particularly the invention provides means and method for storing files of digital of information in pools of individual nucleic acid molecules with a minimal DNA synthesis effort....  
WO/2020/240240A1
The present disclosure relates to an apparatus comprising: - a memory component having an independent structure and including at least an array of memory cells with associated decoding and sensing circuitry and a memory controller; - a h...  
WO/2020/238102A1
The present utility model relates to a tool-disassembly-free hard disk cartridge, comprising side baffles, a bottom plate, and a front baffle, wherein the side baffles are provided with protruding buckles and elastic pieces for providing...  
WO/2020/092406A8
A system includes a volatile storage device (106), a read-only memory (ROM, 104), a memory built-in self-test (BIST) controller (110) and a central processing unit (CPU, 102). The CPU (102), upon occurrence of a reset event, executes a f...  
WO/2020/240229A1
The present disclosure relates to an apparatus comprising a memory component having an independent structure and including at least an array of memory cells with associated decoding and sensing circuitry, a host device coupled to the mem...  
WO/2020/240233A1
A memory component comprises a memory unit including an array of memory cells, a controller of the memory unit, and a JTAG test interface including a plurality of contact pads adapted to connect the memory component with a host device an...  

Matches 401 - 450 out of 863,225