Login| Sign Up| Help| Contact|

Patent Searching and Data


Matches 1 - 50 out of 863,821

Document Document Title
WO/2021/118163A1
A memory device according to the present invention comprises: a memory cell array in which memory cells are connected to wordlines and bitlines in a matrix form; and a control circuit for programming the memory cells or controlling a rea...  
WO/2021/118634A1
This application discloses a memory built-in self-test system to prompt a memory device to sense values of stored data using a reference trim during memory read operations. The memory built-in self-test system can automatically set the r...  
WO/2021/118617A1
For a non-volatile memory die formed of multiple blocks of memory cells, the memory die has a multi-bit bad block flag for each block stored on the memory die, such as in a fuse ROM. For each block, the multi-bit flag indicates if the bl...  
WO/2021/119203A1
A processing device receives a request to perform an erase operation on a memory device. The processing device executes a portion of the erase operation during a first time period. The processing device further executes an erase suspend ...  
WO/2021/118711A1
Systems, apparatuses, and methods related to using memory device sensors are described. Some memory system or device types include sensors embedded in their circuitry. For instance, a device can be coupled to a memory device with an embe...  
WO/2021/117897A1
Provided is a glass which is for a magnetic recording medium substrate or for a glass spacer to be used in a magnetic recording/reproducing device and in which: the total content (Li2O+Na2O+K2O+B2O3+ZnO) of Li2O, Na2O, K2O, B2O3, and ZnO...  
WO/2021/117470A1
A recording layer for an optical information recording medium according to the present invention is capable of recording an information signal by a laser beam being irradiated thereon, and includes a metal oxide including an Sn oxide or ...  
WO/2021/117481A1
The present technology relates to a data processing device, a data processing method, and a program that make it possible to easily perform synchronized generation of a plurality of files in which file streams of different data formats a...  
WO/2021/118658A1
A memory device can sense stored data during memory read operations using a reference trim, and a memory built-in self-test system can perform a multiple step process to set the reference trim for the memory device. The memory built-in s...  
WO/2021/118618A1
An apparatus and method of skip coding user data is provided. According to skip coding, for each bit in which an upper page is 0, data is stored in a half page. For each bit in which the upper page is l, data is not stored in the half pa...  
WO/2021/119409A1
A processing system includes a content addressable memory (CAM) in an input/output path to selectively modify register writes on a per-pipeline basis. The CAM compares an address of a register write to an address field of each entry of t...  
WO/2021/116828A1
Provided is a semiconductor device having high reliability. The semiconductor device includes first to third transistors and a capacitor. In the first transistor, a first signal is applied to one of a source and a drain, the other one of...  
WO/2021/119003A1
A memory sub-system configured to improve performance using signal and noise characteristics of memory cells measured during the execution of a command in a memory component. For example, the memory component is enclosed in an integrated...  
WO/2021/118710A1
Systems and methods for adding virtual audio stickers to videos are disclosed. In general, one aspect disclosed features a method, comprising: editing a video to create an edited video, the editing comprising: playing a video in a video ...  
WO/2021/114011A1
A method of operating a memory device, the memory device includes a top select cell, a top dummy cell and a string of memory cells. The top select cell has a first terminal coupled to a bit line and a control terminal coupled to a top se...  
WO/2021/114013A1
A sense circuit of a memory cell includes a first switch, a sense node, a third switch, a connection node, a fourth switch, and a memory cell coupled in series. A boost driver is coupled to the sense node. A second switch and the connect...  
WO/2021/114571A1
A two-dimensional material-based gate, a memory unit, an array, and an operating method thereof, the gate comprising: a stack unit. The stack unit is a metal-two-dimensional semiconductor-metal structure, comprising a two-dimensional sem...  
WO/2021/119578A1
A power-on-reset (POR) circuit (800) includes an NFET branch (302) and a PFET branch (306). The NFET branch (302) includes: an n-channel field effect transistor (NFET) (310, 312) having a first threshold voltage (Vthn); and a first quies...  
WO/2021/114014A1
A memory includes an upper deck and a lower deck. The upper deck includes a first upper dummy word line. The lower deck includes a first lower dummy word line. A method for reducing program disturbance of the memory includes adjusting a ...  
WO/2021/118712A1
Systems, apparatuses, and methods related to using memory device sensors are described. Some memory system or device types include sensors embedded in their circuitry. For instance, another device can be coupled to a memory device with a...  
WO/2021/119194A1
A read command to read a target memory die of a memory sub-system is received from a host system via a host-side interface of an active input/output (I/O) expander. The active I/O expander identifies a page address corresponding to the t...  
WO/2021/119102A1
Some implementations involve determining a noise metric and/or a speech intelligibility metric and determining a compensation process corresponding to the noise metric and/or the speech intelligibility metric. The compensation process ma...  
WO/2021/119094A1
Some implementations involve determining a noise metric and/or a speech intelligibility metric and determining a compensation process corresponding to the noise metric and/or the speech intelligibility metric. The compensation process ma...  
WO/2021/112905A1
A method for memory block management includes identifying a first group of bit lines corresponding to memory blocks of a 3-dimensional memory array. The method also includes biasing the first group of bit lines to a first voltage using r...  
WO/2021/111155A1
The present disclosure relates to a memory device comprising a plurality of memory cells, each memory cell being programmable to a logic state corresponding to a threshold voltage exhibited by the memory cell in response to an applied vo...  
WO/2021/111444A1
A memory circuit which includes: A synchronous memory cell array, configured to receive a clock signal and having address lines and bit lines. A margin agent, determining a status of the synchronous memory cell array based on a time dura...  
WO/2021/109244A1
The present invention provides a storage structure and an erase method therefor, which can perform an erase operation on blocks B1... Bn, n being an integer greater than or equal to 2. The storage structure comprises a first bank, a seco...  
WO/2021/113072A1
Methods, systems, and devices for reset verification in a memory system are described. In some examples, a memory device may perform a reset operation and set a mode register to a first value based on performing the reset operation. The ...  
WO/2021/112956A1
Methods, systems, and devices for write operation techniques for memory systems are described. In some memory systems, write operations performed on target memory cells of the memory device may disturb logic states stored by one or more ...  
WO/2021/111159A1
The present disclosure provides a memory device. The memory device comprises: a first group of memory cells and a second group of memory cells, the memory cells of the second group being programmed to a predefined logic state of at least...  
WO/2021/112904A1
Apparatuses and techniques are described for periodically refreshing word line voltages in a memory device. A decision to perform a refresh operation is made based on the temperature and number of program-erase (P-E) cycles. In one appro...  
WO/2021/109243A1
A storage structure and an erasing method thereof, being capable of performing an erasing operation on storage blocks. The storage structure comprises: a first memory bank, a second memory bank, a third memory bank, and a controller. The...  
WO/2021/112955A1
Methods of operating a memory device are disclosed. A method may include receiving, at a first die of a number of dies, a first number of bits including one or more command bits, one or more identification bits, and a first number of add...  
WO/2021/110807A1
Method for resetting an array of Resistive Memory (RM) cells by applying a sequence of N reset operations, each reset operation comprising the application of a reset technique, said method comprising the following steps: - at the first r...  
WO/2021/111229A1
A within-chip magnetic field control device is formed in proximity to a Josephson Junction (JJ) structure. The within-chip magnetic field control device includes wiring structures that are located laterally adjacent to the JJ structure. ...  
WO/2021/111157A1
The present disclosure provides a method, a circuit, and a system for reading memory cells. The method comprises: applying a first voltage with a first polarity to a plurality of the memory cells; applying a second voltage with a second ...  
WO/2021/110666A1
Method for resetting an array of Resistive Random-Access Memory cells by applying a sequence of N reset operations, said method comprising the following steps: defining (DF) a first reset technique and performing (RF) the first reset ope...  
WO/2021/111158A1
The present disclosure relates to a method for reading memory cells, comprising the steps of: applying a first/second/third read voltage to a plurality of memory cells, wherein the third read voltage has the same polarity as the first an...  
WO/2021/112813A1
In accordance with some embodiments of the disclosed subject matter, mechanisms for seamless audio melding between audio items in a playlist are provided. In some embodiments, a method for transitioning between audio items in playlists i...  
WO/2021/111156A1
The present disclosure relates to a method for improving the reading and/or writing phase in storage devices including a plurality of non-volatile memory portions managed by a memory controller, comprising: providing at least a faster me...  
WO/2021/111608A1
The present invention sufficiently increases the writing efficiency in transferring a magnetic pattern onto a magnetic recording medium. A slave (10) to which uniform magnetization is imparted and a master (20) to which magnetization o...  
WO/2021/109834A1
A random number generating method and a random number generator. The random number generating method comprises: executing n write operations with respect to at least one analog resistive memory, each write operation among the n write ope...  
WO/2021/111250A1
Provided is a novel information processing device that has low signal transmission delay and low power consumption. A storage device according to the present invention comprises a first layer, a second layer, and a third layer. A circuit...  
WO/2021/113835A1
A test and measurement instrument includes an acquisition memory and a processor structured to store a stream of sampled incoming data samples in the acquisition memory. As the memory fills, the instrument automatically decimates either ...  
WO/2021/112247A1
The present invention provides a non-volatile storage element and a non-volatile storage device that use a ferroelectric material, can be embedded in advanced CMOS logic, and are excellent in low power consumption and high reliability, a...  
WO/2021/111243A1
Provided is a novel semiconductor device comprising a structure extending in a first direction, a first electrical conductor extending in a second direction, and a second electrical conductor extending in the second direction. The struct...  
WO/2021/033339A8
The purpose of the present invention is to provide a magnetic recording medium having excellent traveling stability and a thin overall thickness. The present technology provides a tape-like magnetic recording medium that includes a mag...  
WO/2021/113687A1
Techniques are provided by which the digital delivery of a viewer-requested video along with the best chosen advertisement for the viewer is improved. These techniques may be particularly suited for the short video industry. An innovativ...  
WO/2021/103874A1
The present invention provides an MTJ device manufacturing method. The method comprises: depositing a reference layer thin film, a barrier layer thin film, and a free layer thin film on a substrate; depositing a first metal oxide thin fi...  
WO/2021/103468A1
A read-write circuit of a one-time programmable memory, comprising: an anti-fuse array, comprising: n * n anti-fuse units which are coupled between a first node and a second node, a control end of a switch element in each of the anti-fus...  

Matches 1 - 50 out of 863,821