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Patent Searching and Data


Matches 1 - 50 out of 864,669

Document Document Title
WO/2021/184543A1
A GOA circuit (611) and a display panel (600). The GOA circuit (611) comprises multiple stages of cascaded GOA units, each GOA unit comprising a pull-up control module (301), a pull-down maintaining module (304), a pull-down module (305)...  
WO/2021/184260A1
A shift register unit, comprising: an input circuit (11), a first control circuit (12), a second control circuit (13) and an output circuit (14), wherein the input circuit (11) is configured to provide a signal of a signal input end (INP...  
WO/2021/188316A1
The dynamic memory array of a DRAM device is operated using at least two voltages. The first voltage, which is used to power the sense amplifiers during sense (i.e., read) operations and most other column operations (e.g., precharge, act...  
WO/2021/188720A1
A target value of programmed bits is established for each programming distribution of a set of programming distributions of a memory sub-system. A read voltage level is applied to determine a measured value of programmed bits in one or m...  
WO/2021/188263A1
Separate inter-die connectors for data and error correction information and related systems, methods, and devices are disclosed. An apparatus includes a master die, a target die including data storage elements, inter-die data connectors,...  
WO/2021/188253A1
A method for managing power amongst a set of memory devices that are provided a peak power that is quantized into a set number of power tokens. The method includes determining that the first memory die is to change from a lower power sta...  
WO/2021/188237A1
As described, an apparatus may include a memory cell corresponding to a memory address and an access line forming at least a portion of the memory cell. The apparatus may include a first decoder associated with a first delivery driver co...  
WO/2021/186367A1
A circuit for reducing read disturbance error in a tag array. The circuit includes a decoder, a plurality of m-bit comparators, and a plurality of n-bit comparators. The decoder is configured to enable access to a respective set of the t...  
WO/2021/187429A1
This information processing device is provided with at least one processor. When a predetermined value is reached by the size on a magnetic tape (30) of data recorded in a data partition (DP) of the magnetic tape (30), which has the data...  
WO/2021/188718A1
A workload level in an incoming request queue is determined based on one or more operations requested by a host system for execution by a memory sub-system. Based on the workload level in the incoming request queue, a set of memory dies ...  
WO/2021/184899A1
A shift register unit, a driving method, a gate driving circuit, and a display device. The shift register unit comprises a pull-down node control circuit (10); the pull-down node control circuit (10) is electrically connected to an input...  
WO/2021/186774A1
This information processing device provides control so that, among a plurality of items of data to be recorded in a plurality of magnetic tapes, a data group of which a value corresponding to the size of the data group is greater than or...  
WO/2021/184205A1
The present application relates to the technical field of memories, and provides a planar memory, a three-dimensional memory, and an electronic device, used for reducing the number of electrodes of a memory cell in the planar memory and ...  
WO/2021/180180A1
Disclosed in the present application are data writing and reading methods and devices, and a system. The methods improve the data storage density. The methods are applied to a data storage system, and the storage system comprises a proce...  
WO/2021/183255A1
Signals sent to a memory component are received by circuitry included in the memory component. The circuitry comprises a comparator circuit to process the received signals. The circuitry further comprises a resistor-capacitor (RC) circui...  
WO/2021/179213A1
The present application provides a method and a device for repairing a memory chip, relating to the field of computers. Said method comprises: acquiring self-detection parameters of a chip, and performing a repair operation on the chip a...  
WO/2021/179559A1
The embodiments of the present disclosure relate to the technical field of semiconductor device testing, and provided are a method and apparatus for testing a memory, electronic equipment, and a computer-readable storage medium. The meth...  
WO/2021/030750A8
Memories, memory controllers, and computing systems and their methods of operation are disclosed. In some embodiments, a method of accessing a memory includes accessing a first bit line corresponding to a sense amplifier and accessing a ...  
WO/2021/183794A1
A processing device in a memory sub-system sends a program command to the memory device to cause the memory device to initiate a program operation on a corresponding wordline and sub-block of a memory array of the memory device. The proc...  
WO/2021/181354A1
The present invention relates to a computer implemented system (100) and method for generating multiple media creations. The system (100) is able to 5 generate and display multiple variations of media content and display to the user. The...  
WO/2021/181739A1
When performing recording on magnetic tape by grouping together and transmitting a plurality of pieces of data to a tape drive, this information processing device selects one of a first method in which a data group of a plurality of piec...  
WO/2021/179603A1
A method and apparatus for testing a control chip, and an electronic device and a computer-readable storage medium. The method comprises: reading a first test vector stored in a first target memory chip (S210); sending the first test vec...  
WO/2021/179600A1
Disclosed are a memory testing method and apparatus, an electronic device, and a computer-readable storage medium, relating to the technical field of semiconductor device testing. The method comprises: testing a first memory and acquirin...  
WO/2021/179601A1
A method and apparatus for testing a control chip, and an electronic device and a computer-readable storage medium, relating to the technical field of semiconductor device testing. The control chip comprises a built-in self-test circuit,...  
WO/2021/179439A1
A shift register unit (100), a gate electrode drive circuit, and a display panel. The shift register unit (100) comprises: a pull-up control module (10) connected respectively to an (n-1)th stage scanning signal output end (STU), a first...  
WO/2021/181172A1
A method of manufacturing a double magnetic tunnel junction device is provided. The method includes forming a first magnetic tunnel junction stack (204), forming a spin conducting layer (206) on the first magnetic tunnel junction stack (...  
WO/2021/180647A1
The invention relates to a resistance network and to an integrated circuit having said resistance network, the resistance network comprising at least two memory cells (200a, 200d) for storing one resistance characteristic value each, eac...  
WO/2021/181838A1
In a sensor device in which adjustment information of the sensor device can be written from the outside, there is a possibility that unauthorized writing of the adjustment information may occur. A sensor device 1 according to the prese...  
WO/2021/183384A1
A method for performing an appearance search using a map involves receiving search commencement input requesting that an appearance search for one or more objects-of-interest commence be performed. In response to the search commencement ...  
WO/2021/181738A1
This information processing device executes control in which the identification information of at least some magnetic tapes of a plurality of magnetic tapes belonging to a magnetic tape pool is recorded to a recording medium other than a...  
WO/2021/179329A1
A shift register, a driving method, a gate drive circuit and a display device. The shift register comprises: an input circuit (10), a first transistor (M1), a cascade output circuit (20) and a drive output circuit (30). The first transis...  
WO/2021/179869A1
Disclosed are an audio playing method and apparatus, and a storage medium and a terminal. The method comprises: receiving a recommended audio acquisition instruction input for an audio playing interface, and acquiring a recommended piece...  
WO/2021/183663A1
A baseplate for a disk drive suspension is provided. The baseplate includes a receiving space at a distal end configured to mate with a spring of a load beam. The receiving space partially extends a length of the baseplate. The baseplate...  
WO/2021/179602A1
A memory test method and apparatus, an electronic device and a computer readable storage medium, relating to the technical field of semiconductor device test. Said method is executed by a built-in self-test circuit, and comprises: testin...  
WO/2021/182778A1
Disclosed is a logic element using spin-orbit torque. Two magnetic tunnel junctions have mutually opposite stator magnetizations. The direction of current flowing through a nonmagnetic metal layer acts as an input, and the resistance sta...  
WO/2021/179384A1
A shift register unit, a gate electrode driving circuit, and a display panel. The shift register unit (100) comprises: a compensation module (50), connected respectively to a second node (QB), a present-level cascading signal output end,...  
WO/2021/182621A1
The present invention provides a glass composition having a low density and a specific elastic modulus that is high enough to suppress deflection. This glass composition contains, in terms of mol%, 60-75% of SiO2, 5-15% of Al2O3, 0.5-5% ...  
WO/2021/158683A3
A method of manufacturing a tri-stage assembly is provided. The method includes attaching a first microactuator and a second microactuator to a trace gimbal to a flexure during a PZT on flexure process (POF). The first microactuator is l...  
WO/2021/181455A1
In order to suppress an increase in production burden of a memory cell array, a semiconductor storage device according to an embodiment is provided with a bit line, a capacitor, and a first memory cell transistor and a second memory cell...  
WO/2021/177246A1
An information processing device (10) is provided with at least one processor. The processor performs control for dividing data of a predetermined size or more that has been specified on the basis of a read history into a plurality of pa...  
WO/2021/176245A1
The present disclosure relates to a memory device comprising an array of memory cells arranged in a multideck configuration comprising a plurality of superimposed decks, a plurality of access lines comprising at least a first plurality o...  
WO/2021/178113A1
Disclosed embodiments relate, generally, to interfacing serial communication interfaces of a first device with a parallel communication interface of a second device. A first group of two or more serial communication interfaces and an int...  
WO/2021/178003A1
Numerous embodiments of analog neural memory arrays are disclosed. In one embodiment, an analog neural memory system comprises an array of non-volatile memory cells, wherein the cells are arranged in rows and columns, the columns arrange...  
WO/2021/178002A1
Numerous embodiments of analog neural memory arrays are disclosed. In certain embodiments, each memory cell in the array has an approximately constant source impedance when that cell is being operated. In certain embodiments, power consu...  
WO/2021/177300A1
This information processing device is provided with at least one processor. When an address relative value between a first address value, which indicates the tape-traveling-direction end position of recorded data, that is, data recorded ...  
WO/2021/178179A1
Embodiments of the disclosure are drawn to apparatuses, systems, methods, and memories that are capable of performing pattern matching operations within a memory device. The pattern matching operations may be performed on data stored wit...  
WO/2021/177517A1
Disclosed is a non-volatile flip-flop operation method in a data restoration mode. The present invention can maximize an offset removal effect by causing a first magnetic tunnel junction (MTJ) and a second MTJ to be disconnected from eac...  
WO/2021/175099A1
The present invention provides an effective random fault injection method for a memory circuit. The method comprises the following steps: step 1, extracting all possible fault nodes with a Perl language, modifying the names of all fault ...  
WO/2021/175735A1
An electronic device having circuitry, which is configured to estimate a distraction level of an audio object stream, and to modify the audio object stream based on the estimated distraction level to obtain a modified audio object stream.  
WO/2021/177301A1
This recording medium is provided with: a recording layer configured to be capable of changing a coloring state with an external stimulus; and a plurality of transparent convex parts provided on the recording layer. The convex parts have...  

Matches 1 - 50 out of 864,669