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Patent Searching and Data


Matches 1 - 50 out of 661,939

Document Document Title
WO/2022/164507A1
Systems, apparatuses, and methods related to memory device protection are described. A quantity of errors within a memory device can be determined and the determined quantity can be used to further determine whether to utilize single or ...  
WO/2022/164490A1
A first set of physical units of a storage device of a storage system is selected for performance of low latency access operations, wherein other access operations are performed by remaining physical units of the storage device. A determ...  
WO/2022/160888A1
A shift register, a gate drive circuit and a display panel. The shift register comprises: a first input module (10), a second input module (20), a first output module (30), a second output module (40), a first output control module (50) ...  
WO/2022/160847A1
Provided is a method for optimizing a polar-RNNA quantizer of an MLC-type NAND flash memory on the basis of deep learning. The method comprises the following steps: step S1, converting an MLC flash memory detection problem into a deep le...  
WO/2022/163509A1
This invention provides a magnetic tape having a non-magnetic support and a magnetic layer containing ferromagnetic powder. The amount of fluid lubricant extracted from the surface of the magnetic layer after sliding against a magnetic h...  
WO/2022/160802A1
A shift register (100), comprising an input circuit (110), an intermediate circuit (120) and an output circuit (130). The input circuit (110) is used for outputting an intermediate input signal to the intermediate circuit (120), the inte...  
WO/2022/164445A1
A testing circuit configured to test and diagnose a read-only memory comprises two multiple-input signature registers configured to generate two sets of signatures for multiple iterations of reading some or all of words stored in the rea...  
WO/2022/162870A1
The present invention is a memory device that uses rod-shaped semiconductor elements and in which there is a block in which memory cells CL00-CL13 are arranged in a matrix and that carries out: a data holding operation in which voltage a...  
WO/2022/160091A1
A request to perform a write operation at a memory device is received. Current wordline start voltage (WLSV) information associated with a particular memory segment of the plurality of memory segments is retrieved. The write operation is...  
WO/2022/164559A1
A package comprising a substrate, a first integrated device and a second integrated device. The substrate includes at least one dielectric layer, a plurality of interconnects, a solder resist layer, and a plurality of periphery interconn...  
WO/2022/160889A1
Disclosed are a shift register, a gate driving circuit and a display panel. The shift register comprises a first input module, a second input module, a first output module, a second output module, a first output control module and a seco...  
WO/2022/161940A1
The invention relates to a computer implemented method for adjusting a delivery of audio and/or audiovisual content (10) using a graphical user interface (12) on an electronic device (1) having a touch-sensitive display device (2), compr...  
WO/2022/164604A1
An input receiver circuit for a signal line may receive inputs from other signal lines to mitigate crosstalk noise present on the signal line. In some examples, the input receiver circuit may include a transistor with a programmable widt...  
WO/2022/164887A1
A system can perform image capture during a medical procedure. The system can record video from one or more video sources. The system can store the recorded video in a cached memory as stored video. The system can receive a triggering ev...  
WO/2022/160114A1
A flash memory device includes a plurality of memory planes each contains arrays of memory cells; a host interface for accessing the plurality of memory planes by an external host; and a controller connected to the plurality of memory pl...  
WO/2022/160574A1
A failure analysis method, a computer device and a storage medium. The failure analysis method comprises: acquiring failure data of IO channels in a target chip, wherein the target chip comprises m physical modules, each physical module ...  
WO/2022/163078A1
When performing control to store an object into divided multiple partial areas of a magnetic tape, this information processing device receives an object transmitted from a user terminal after a storage destination bucket for the object h...  
WO/2022/164513A1
Various embodiments include a computing device memory system having a memory device, a memory physical layer communicatively connected to the memory device, a first input/output (IO) voltage supply electrically connected to the memory de...  
WO/2022/164478A1
A crossflow air deflector part for directing airflow includes a front central spine, a first arcuate wall extending from the spine to a first back lateral edge of the airflow deflector, and a second arcuate wall extending from the spine ...  
WO/2022/165364A1
Cavity resonators are promising resources for quantum technology, while native nonlinear interactions for cavities are typically too weak to provide the level of quan¬ tum control required to deliver complex targeted operations. Here we...  
WO/2022/164633A1
A latch array including a row of master latches coupled to columns of slave latches. Each master latch includes an OR-AND-Inverter (OAI) gate cross-coupled with a NAND gate to receive and latch an input data, and each slave latch include...  
WO/2022/161822A1
A method and an apparatus for editing at least two sequences of pictures are provided. Editing the sequences comprises modifying at least one picture of one of the at least two sequences, based on a user input, and updating at least one ...  
WO/2022/165514A1
Methods and systems for forming holographic gratings are described herein. The methods and systems may decrease the amount of haze produced during exposure of a holographic recording medium. In some embodiments, the methods and systems i...  
WO/2022/163841A1
This method for manufacturing a glass plate involves processing in which laser light is radiated along the inner peripheral end face along an inner pore of a glass plate having an annular shape. In irradiating the inner peripheral end fa...  
WO/2022/161832A1
A memory structure (100) comprises a ReRAM module (110) embedded in a substrate. An insulative layer (106) is formed on the substrate. A first electrode is located on the insulative layer. The first electrode is proximately connected to ...  
WO/2022/160226A1
A storage array, a memory, a manufacturing method, and a writing method, relating to a magnetoresistive random access memory (MRAM) storage array and a manufacturing method therefor. The storage array comprises a plurality of storage cel...  
WO/2022/160317A1
A data processing method, apparatus and system, which are used to optimize the particle arrangement means for a QLC flash memory array. The method comprises: a storage controller measures the popularity of historical data of a QLC flash ...  
WO/2022/162342A1
According to one implementation of the present disclosure, an integrated circuit comprises a memory macro unit that includes an input/output (I/O) circuit block, where read/write circuitry of the I/O circuit block is apportioned on at le...  
WO/2022/160613A1
A refresh circuit and a memory. The refresh circuit comprises: a refresh control module (200), which is used to receive and execute a refresh command so as to output a row address refresh signal and which is further used to receive a pro...  
WO/2022/163708A1
Provided is a fluorine-containing ether compound represented by the following formula. R1-R2-CH2-R3-CH2-R4 (wherein R1 is a terminal group that includes an oxime group and is represented by formula (2), R2 is a divalent linking...  
WO/2022/163883A1
An object of the present invention is to provide a neuromorphic system including a synaptic unit capable of causing a gradual change in resistance for analog information processing, and an operating method therefor. In order to achieve t...  
WO/2022/160631A1
Embodiments of the present application provide a refresh circuit and a memory, the refresh circuit comprising: a refresh control module, which is used for receiving a refresh command so as to output row address refresh signals, wherein e...  
WO/2022/164659A1
A semiconductor memory device is implemented as strings of storage transistors, where the storage transistors in each string have drain terminals connected to a bit line and gate terminals connected to respective word lines. In some embo...  
WO/2022/160292A1
Provided are a ferroelectric memory and a storage device, which are used for reducing an operating voltage, reducing interface defects in a ferroelectric memory, and improving the durability of the ferroelectric memory. The ferroelectric...  
WO/2022/165271A1
Present implementations are directed to nonvolatile memory devices with charge trap transistor structures. Example implementations can include a method of memory storage, by programming a first data node operatively coupled to a first ch...  
WO/2022/156156A1
The present application provides a protection circuit and a memory. The circuit is applied to a chip. The circuit comprises a first protection unit and a first protected element; the first protection unit receives a first input signal an...  
WO/2022/158501A1
Provided are a perfluoropolyether compound that has high heat resistance and makes it possible to maintain a surface protection layer even under high temperatures, and a lubricant and a magnetic disc containing the perfluoropolyether com...  
WO/2022/157998A1
If a consumption current class supported by this removable memory device is another consumption current class that differs from a first consumption current class for which a consumption current value is largest among a plurality of varie...  
WO/2022/155828A1
The present disclosure provides a three-state spintronic device, a memory cell, an array, and a read-write circuit. The three-state spintronic device comprises, from bottom to top, bottom electrodes, a magnetic tunnel junction, and a top...  
WO/2022/159406A1
A non-volatile memory device includes: an insulation layer; a PN diode, which is formed in a monocrystalline silicon layer, a monocrystalline germanium layer or a monocrystalline gallium arsenide layer on the insulation layer; a writing ...  
WO/2022/158237A1
The present technology relates to a recording medium, a recording device, a recording method, a reproduction device, and a reproduction method that make it possible to correctly reproduce multi-level code that has been recorded at high d...  
WO/2022/159031A1
Embedded memory structures and methods of fabricating an embedded memory structure. In one embodiment, the method comprises providing an array of bitcells interconnected by a plurality of bitlines and a plurality of wordlines, each bitce...  
WO/2022/158349A1
A semiconductor storage device (100a) according to this disclosure comprises: a memory cell array (110) including a plurality of memory cells; a read data output unit which outputs data read from the memory cell array to the outside with...  
WO/2022/155948A1
The present disclosure discloses a video storage method for a vehicle-mounted device, and a vehicle-mounted device. Said method comprises: monitoring the state of a vehicle; and if an anomalous state of the vehicle is detected, writing b...  
WO/2022/158626A1
The present invention relates to a Bluetooth microphone supporting a speech to text (STT) function. The Bluetooth microphone supporting an STT function, according to the present invention, comprises: a microphone head formed on the top o...  
WO/2022/158118A1
This wiring circuit board (X1) comprises a metal support substrate (10), an insulating layer (20), and a conductor layer (30) in this order in the thickness direction (T). The conductor layer (30) includes at least one terminal section (...  
WO/2022/158545A1
A photonic spin register (100) comprises: a shift register unit (104) having a magnetic material layer (124) of a shape extending in one direction; a light receiver (114) for receiving a serially input, pulse amplitude-modulated optical ...  
WO/2022/155798A1
The systems and methods are configured to efficiently and effectively prime and initialize a memory. A memory controller (130) includes a normal data path (131) and a priming path (132). The normal data path (131) directs storage operati...  
WO/2022/157954A1
According to the present invention, a columnar semiconductor memory device is configured to perform: data holding operation for controlling voltage applied to a first gate conductor layer, a second gate conductor layer, a first impurity ...  
WO/2022/156204A1
A method for detecting etching defects of an etching machine, which belongs to the technical field of semiconductor production and fabrication. The method for detecting the etching defects of the etching machine comprises: providing a te...  

Matches 1 - 50 out of 661,939