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Matches 1 - 50 out of 666,025

Document Document Title
WO/2024/146049A1
The present disclosure relates to the field of semiconductor circuit design, and in particular, to a random pulse generation circuit, a monitoring circuit, and a memory. The random pulse generation circuit comprises: an oscillation gener...  
WO/2024/146129A1
Disclosed are an address comparison circuit and a storage system. The circuit comprises: a reset circuit, which has a feedback node, and is configured to receive a control command and adjust, in response to the valid control command, the...  
WO/2024/146330A1
The present application relates to the field of video processing, and discloses a video storage method and a video playback method. The video storage method comprises: acquiring at least one video stream; controlling a processing thread ...  
WO/2024/147041A1
A method for video processing includes receiving a sequence of video frames containing video images having respective timestamps with a first temporal granularity superimposed on the video images (100). The video frames are processed to ...  
WO/2024/147848A1
A highly fluorinated lubricant configured to be adsorbed by an overcoat of a magnetic recording medium. The lubricant may have a structure: R1-Rf-R1 where Rf is -CF2O(CF2CF2O)nCF2- where n is from 1 to about 100, or Rf is – CF2CF2O(CF2...  
WO/2024/146050A1
The present disclosure provides a data reading circuit and a storage device thereof. The data reading circuit comprises: a first data transmission path for transmitting first data; a second data transmission path for transmitting second ...  
WO/2024/146031A1
Embodiments of the present disclosure provide a control circuit, a control method and a memory. The control circuit comprises: an input control module used for generating a first driving control signal and a second driving control signal...  
WO/2024/146004A1
Provided in the present disclosure are a control circuit, a control method and a memory. The circuit comprises: a clock processing module, which is configured to perform sampling and shift processing on a clock enable signal according to...  
WO/2024/145978A1
The present application provides a memory, comprising a plurality of cluster areas, a command decoding circuit, and a control circuit. Each cluster area comprises a plurality of storage clusters, and each storage cluster corresponds to o...  
WO/2024/146128A1
The present invention relates to the field of semiconductor circuit design, and in particular to a memory and a write test method. A memory (10) comprises: a signal receiving circuit (101) used for: when a chip select signal is valid, in...  
WO/2024/146058A1
Disclosed are a memory and a testing method therefor. The memory comprises: a plurality of first pins used for receiving data; a second pin used for receiving mask data when the memory performs a mask write operation or receiving check c...  
WO/2024/146009A1
Disclosed in the present invention is a high-efficiency memory used for cryogenic computing, characterized by comprising a plurality of memory groups. Each memory group comprises a CSDB-GC macro module, a universal address decoder and a ...  
WO/2024/146023A1
Provided in the embodiments of the present disclosure are an anti-fuse structure and a memory. The anti-fuse structure comprises a first anti-fuse unit and a second anti-fuse unit, wherein the first anti-fuse unit comprises a first selec...  
WO/2024/146127A1
A memory and a write test method. The memory comprises: a signal receiving circuit, wherein in a test mode, within two clock cycles of a clock signal, when a chip selection signal is valid, a compression write command is obtained by perf...  
WO/2024/146030A1
Embodiments of the present disclosure provide a control circuit, a control method, and a memory. The control circuit comprises: an identification signal generation module used for generating a command/address reverse-identification signa...  
WO/2024/146274A1
Disclosed in embodiments of the present disclosure is a memory, comprising a plurality of column decoders and a plurality of local power supply units which are in one-to-one correspondence to the column decoders and are used for supplyin...  
WO/2024/146130A1
Provided in the embodiments of the present disclosure are a signal generation circuit, a storage apparatus, and an operating method. The circuit comprises: a first circuit, configured to receive a read selection signal, a write selection...  
WO/2024/146135A1
A power supply circuit of a semiconductor memory apparatus, and a semiconductor memory apparatus. The power supply circuit (10) comprises a first power branch (101) and a second power branch (102). The first power branch (101) receives a...  
WO/2024/145860A1
A memory controller coupled to a memory device including an array of memory cells, each memory cell being set to one of 2 N states corresponding to a piece of N-bits data, where N is an integer greater than 1, and the array of memory cel...  
WO/2024/123715A3
In some embodiments, an electronic device changes a value of a first visual characteristic with which lyrics are displayed in response to detecting a change in a performer of lyrics associated with a song or other type of content item. I...  
WO/2024/146018A1
Disclosed are a control circuit and a semiconductor memory. The control circuit comprises a data input and output module. After check of CRC data fails, the data input and output module generates a CRC warning signal; and when the number...  
WO/2024/146318A1
The present disclosure provides a storage circuit, a storage chip and a memory. The storage circuit comprises a row address gating unit, a row address decoder, a first storage array and a second storage array which are located on two opp...  
WO/2024/139915A1
Disclosed in the present invention are a programming method and apparatus capable of reducing space occupation in an NAND flash memory device, a memory, and a system. The programming method comprises the following steps: applying a first...  
WO/2024/144955A1
Systems and methods for operating a low-density parity-check (LDPC) bit-flipping decoder are disclosed herein. An LDPC codeword is received, and each bit in the LDPC codeword is classified as either a high-confidence bit or a low-confide...  
WO/2024/138879A1
In certain aspects, a memory device includes an array of memory cells, word lines respectively coupled to rows of the memory cells, and a peripheral circuit coupled to the array of memory cells through the word lines and configured to re...  
WO/2024/144868A1
Automated memory overclocking is described. In accordance with the described techniques, one or more sets of overclocked memory settings of a memory are automatically selected for performance testing and stability testing of the memory. ...  
WO/2024/138844A1
A three-dimensional (3D) memory includes a first semiconductor structure having a 3D memory array, wherein the 3D memory array includes a plurality of memory planes, and a second semiconductor structure having a plurality of page buffer ...  
WO/2024/141349A1
The present invention relates to a device and an automated method for deleting data stored in non-volatile memories (M) of electronic devices (A), for example portable devices such as smartphones or tablets, characterised in that the met...  
WO/2024/143860A1
An electronic device according to an embodiment may comprise a display, a communication module, and a processor. The processor according to an embodiment may: while playing back audio on the electronic device, if identifying selection fo...  
WO/2024/138492A1
A computer implemented method by a neural network for continual learning of a series of tasks is disclosed, wherein the neural network includes a plurality of sub-networks having the same architecture and respective parameter spaces. The...  
WO/2024/143499A1
This fluorine-containing ether compound is represented by formula (1). In formula (1), X represents one of formulae (2-1) to (2-5), A represents formula (3-1) or (3-2), B represents a perfluoropolyether chain, D comprises 2 to 4 polar gr...  
WO/2024/140504A1
Embodiments of the present application relate to the technical field of semiconductors, and provide a memory array and a preparation method, a storage circuit and a read-write method, and an electronic device, which are used for improvin...  
WO/2024/138912A1
In certain aspects, a memory device includes an array of memory cells and a peripheral circuit coupled to the array of memory cells. At least one of the memory cells is set to one of 2N levels corresponding to a piece of N-bits data, whe...  
WO/2024/144908A1
A memory system is described having an x-direction (bit line direction) divided sub-block mode. Each block is divided in a y-direction and in the x-direction into a number of groups of contiguous NAND strings that are referred to as XY s...  
WO/2024/144849A1
A DRAM fabrication process for producing a semiconductor die adapted for having the ability to be both a hybrid memory and power supply capacitance. DRAM arrays on a semiconductor die may be individually selected to function as either a ...  
WO/2024/139206A1
A memory device includes a memory array structure and a peripheral structure. The memory array structure includes at least one memory bank, and each memory bank includes a plurality of memory blocks. The peripheral structure includes a w...  
WO/2024/138819A1
A memristor-based charge-type in-memory computation implementation method and a unit structure therefor. The unit structure comprising a memristor, a transistor and a capacitor converts the resistance state of the memristor into a charge...  
WO/2024/140102A1
A magnetic tunnel junction structure, comprising a reference layer, a barrier layer and a free layer, which are arranged in a stacked manner, wherein the free layer comprises: a first free layer, which is arranged on the side of the barr...  
WO/2024/142389A1
The present invention comprises: a RAM cell including columnar P layers 3, 3A, 3B standing on P layer substrates 1, 1a, 1b, a first gate insulating layer 5 and a first gate conductor layer 6 surrounding a P layer 3a, a second gate insula...  
WO/2024/144915A1
A process of assembling a voice coil motor (VCM), such as for a hard disk drive, includes creating an opening in a yoke, attaching a primary magnet to an inside surface of the yoke, installing through the opening in the yoke a cross-flux...  
WO/2024/144172A1
According to embodiments disclosed herein, a memory device, which comprises a ternary memory cell and performs a ternary operation, comprises: the ternary memory cell in which a storage value, which is ternary data, is stored by applying...  
WO/2024/138986A1
In certain aspects, a memory device includes an array of memory cells in columns and rows, word lines respectively coupled to rows of the memory cells, and a peripheral circuit coupled to the rows of memory cells through the word lines. ...  
WO/2024/144910A1
A non-volatile memory system reduces the number of bits of data per non-volatile memory cell for a block (or other grouping of non-volatile memory cells) in response to a failed memory operation, the block being subjected to more than a ...  
WO/2024/138900A1
A technical solution of the present invention provides an ultra-low voltage SRAM unit capable of eliminating half-select disturbance in a bit-interleaved structure, characterized by comprising a read path composed of a set of inverter ri...  
WO/2024/138905A1
Disclosed in the present invention is a cryogenic high-energy-efficiency computing-in-memory accelerator. The innovations of the present invention lie in: the design of a long-retention-time cryogenic 3T storage unit: provided in the pre...  
WO/2024/142984A1
An alkali-free glass plate according to the present invention is characterized in that: the glass composition thereof contains, in terms of mol%, 65-72% of SiO2, 11-15% of Al2O3, 2-5% of B2O3, 0-0.5% of Li2O+Na2O+K2O, 2-8% of MgO, 4-10% ...  
WO/2024/137794A1
Described in this specification are technologies including a vector data structure for representing data objects with identifiers, with applications in searching for data objects that are similar or identical to a given query data object...  
WO/2024/130672A1
Provided in the present disclosure are a display substrate, a manufacturing method and a display apparatus. The display substrate comprises a driving circuit arranged on a base substrate, the driving circuit comprising a first node contr...  
WO/2024/137892A2
Devices and methods for backing up digital data on storage devices which are automatically selected on an individual basis for digital connection, data exchange and data storage on a scheduled basis and each kept digitally disconnected w...  
WO/2024/133958A1
The invention relates to a magnetic card (2) reader (1), which comprises: - an electronic card (5) which is intended to receive and process data from a magnetic card; - a magnetic reading head (6) which is intended to read data contained...  

Matches 1 - 50 out of 666,025