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Patent Searching and Data


Matches 401 - 450 out of 816,376

Document Document Title
WO/2024/048419A1
A plasma treatment method for using a plasma treatment device is used, the method comprising: a step for acquiring parameters including a first initial electric-power value, an initial electric-power application time, and an output inhib...  
WO/2024/049642A1
The present disclosure is directed towards polishing modules for performing chemical mechanical polishing of a substrate. The substrate may be a semiconductor substrate. The polishing modules described have a plurality of pads, such as p...  
WO/2024/048605A1
Provided are: a photosensitive resin composition comprising a polyimide precursor having a radical-polymerizable group, a photopolymerization initiator, and a compound having a coumarin skeleton; a cured product; a layered body; a method...  
WO/2024/048631A1
The present invention addresses the problem of providing a novel compound which enables the production of a cured article having a high refraction index and which has excellent moldability and curability. The present invention relates ...  
WO/2024/045270A1
A laminated structure and a preparation method therefor, a pattern transfer method, and a reworking method. A stripping layer (100) capable of being etched and removed by means of a wetting method is arranged below a bottom anti-reflecti...  
WO/2024/049863A1
Methods of separating semiconductor dies are described. The method can separate individual semiconductor dies (115) from a semiconductor wafer (110) without using a blade. The methods include a plasma etch process (155) utilizing metal s...  
WO/2024/047479A1
An electronic device (11) includes a substrate (55), first and second semiconductor devices (22, 33), and a power supply structure (88b). The first semiconductor device (22) includes a first plurality of gate all-around (GAA) field effec...  
WO/2024/048083A1
The present invention increases the degree of integration of a semiconductor device. This semiconductor device comprises: a three-dimensional material layer; a first transistor including the three-dimensional material layer; a two-dimens...  
WO/2024/047916A1
Provided are a resin sealing device and method with which it is possible to remove a gate part with high precision and to miniaturize and increase the mounting density of molded articles. This resin sealing method comprises: a resin seal...  
WO/2024/045597A1
The present application provides a solar cell and a preparation method therefor. The preparation method for the solar cell comprises: providing a solar cell substrate having transparent conductive films; sequentially forming a plurality ...  
WO/2024/045211A1
Embodiments of the present disclosure relate to a semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises: a substrate, a plurality of capacitive contact structures arranged at intervals being f...  
WO/2024/047995A1
This semiconductor device comprises: an amorphous substrate having an insulating surface; an orientation pattern located on the amorphous substrate; and a semiconductor pattern including gallium nitride and located on the upper surface o...  
WO/2024/048271A1
Provided are: a composition for chemical mechanical polishing; and a polishing method using the same. The composition allows rapid polishing of a polishing surface that contains a silver material for wiring, and makes it possible to obta...  
WO/2024/047835A1
A data collection and analysis system (1) is applied to, for example, an etching device in semiconductor manufacturing. The data collection and analysis system (1) comprises: a measurement data collection unit (100) that is disposed in a...  
WO/2024/047487A1
Provided is a storage device which can be micro-fabricated or highly integrated. The storage device includes a memory cell, a first insulator, and a second insulator. The memory cell includes a capacitor element and a transistor on the c...  
WO/2024/049699A1
Provided are nitride atomic layer etch including in situ generating a phosphoric acid on the surface of silicon nitride layer by reacting a phosphorus containing reactant with one or more oxidants. Phosphoric acid selectively etches sili...  
WO/2024/045818A1
A substrate heat treatment apparatus, comprising a fixing frame; a movable base for loading a heat treatment module; a limited plate-like motion guide rail, the movable base being movably mounted in the fixing frame by means of the limit...  
WO/2024/045296A1
Provided in the present disclosure are a semiconductor structure and a preparation method therefor. The preparation method comprises: providing a substrate, wherein the substrate comprises a shallow trench isolation structure and an acti...  
WO/2024/045732A1
The present invention provides a preparation method for a polyimide via, and a wafer-level semiconductor packaging structure. The preparation method for the polyimide via comprises: S1: providing a substrate having a metal pad attached t...  
WO/2024/047423A1
A semiconductor structure includes a first field-effect transistor having a first back side source/drain contact, a second back side source/drain contact, and a first power line and a first signal line each connected to the first back si...  
WO/2024/045242A1
The application relates to a positioning device and a wafer clamping system. The positioning device is used in the wafer clamping system, and comprises a supporting mechanism and a positioning mechanism, wherein the positioning mechanism...  
WO/2024/047488A1
Provided is a semiconductor device that occupies a small area. The semiconductor device includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a first conductive layer, a second conductive layer,...  
WO/2024/046738A1
A semiconductor structure including a fin of a vertical transistor structure, a top source drain region on a top side of the fin, a bottom source drain region on a bottom side of the fin, and a backside contact below and contacting the b...  
WO/2024/047471A1
Methods for creating a conductive pillar on a receiver substrate may include forming a dried metal paste pillar by printing metal paste over an area of a receiver substrate, drying the metal paste, and repeating the printing and drying s...  
WO/2024/045731A1
A three-dimensional packaging structure (10) and a manufacturing method therefor. The three-dimensional packaging structure (10) comprises: a packaging substrate (500), a rewiring layer (100), a plurality of TSV bridging substrates (200)...  
WO/2024/046093A1
Embodiments of the present application relate to the technical field of semiconductors, and provide a semiconductor structure and a preparation method, a radio frequency front-end module, a power conversion module and an electronic devic...  
WO/2024/048764A1
[Problem] To provide: a crystal having excellent crystallinity; a layered structure; and an element, an electronic device, an electronic apparatus, and a system that use the crystal and the layered structure. [Solution] This layered stru...  
WO/2024/046398A1
A composition. The composition comprises a metal ion source and a leveling agent as represented by formula (I), i.e., R1-S-(R3-O)m-(R2-O)n-R2-(O-R3)m-S-R1 , wherein each R1 group is independently selected from a substituted or unsubstitu...  
WO/2024/046983A1
The invention relates to a method for separating a semiconductor component (21) from a carrier (22), wherein the semiconductor component (21) is integrally bondedly held in a bonding plane (24) on a carrier (22) by means of a metal-conta...  
WO/2024/047746A1
In order to provide a plasma processing device with increased processing yield, an internal member thereof, or a method for manufacturing those, the present invention comprises a processing chamber which is disposed inside a vacuum chamb...  
WO/2024/047486A1
Provided is a storage device which allows for miniaturization and high integration. The present invention comprises: a first insulator on a substrate; an oxide semiconductor covering the first insulator; a first conductor and a second co...  
WO/2024/048273A1
In the present invention, a base is arranged inside a plasma treatment chamber. An electrostatic chuck is arranged on the upper part of the base. A first heater electrode layer is arranged inside the electrostatic chuck. A second heater ...  
WO/2024/045252A1
The present application relates to a carrying device and a wafer cooling system. The carrying device is used in the wafer cooling system which comprises a base for supporting and cooling a wafer. The carrying device comprises a body comp...  
WO/2024/048316A1
A substrate treatment device according to an embodiment of the present disclosure has: a treatment container; a substrate holding unit that is disposed inside of the treatment container and that holds a substrate; a gas nozzle that spray...  
WO/2024/049769A2
Patterned assemblies with a patterned release layer, methods of making, and methods of using are described herein. The assemblies with a patterned release layer may include donor plates, wafers, components (e.g. microelectronic component...  
WO/2024/048498A1
[Problem] To provide a silicon-etching liquid capable of wet-etching silicon at a high rate without etching an insulation film made of silicon dioxide, silicon nitride, or the like, when producing a semiconductor device or the like. [Sol...  
WO/2024/045758A1
A three-dimensional stacked fan-out package structure and a preparation method therefor. The fan-out package structure sequentially comprises chip stacks, a silicon interposer (101), transmission chips (122), a coating layer (102) and a ...  
WO/2024/045860A1
The present application provides a thin film transistor and an electronic device using same. An active layer in the thin film transistor comprises a first active layer, a channel layer and a second active layer which are stacked; the fir...  
WO/2024/046726A1
A semiconductor interconnect structure comprises a substrate, a plurality of metal lines disposed relative to the substrate and a plurality of first and second caps disposed on the metal lines wherein the first caps comprise a first diel...  
WO/2024/050158A1
A transistor and method of fabricating the same comprising a channel layer; an epitaxial barrier layer on the channel layer; an epitaxial cap layer on the epitaxial barrier layer; a dielectric layer on the epitaxial cap layer having an o...  
WO/2024/016380A9
The present disclosure relates to the technical field of semiconductors, and relates to a processing method, processing apparatus and processing system for a semiconductor structure. The processing method of the present disclosure compri...  
WO/2024/050167A1
Aspects disclosed herein include integrated circuit (IC) packages employing a capacitor interposer substrate with aligned external interconnects, and related fabrication methods. The IC package includes one or more semiconductor dies ("d...  
WO/2024/048766A1
[Problem] To provide a crystal having excellent crystallinity, a multilayer structure, and an element, an electronic device, an electronic appliance, and a system which are obtained using these. [Solution] An electroconductive crystal wh...  
WO/2024/049183A1
The present invention relates to a method for producing a ceramic substrate. The ceramic substrate can be used in high-output power modules due to the 0.3-0.8mm thickness of the upper and lower metal layers that adhere to the upper and l...  
WO/2024/049754A1
A method for forming alignment marks leverages pad density and critical dimensions (CDs). In some embodiments, the method includes forming first and second alignment marks on a first substrate and a second substrate where the alignment m...  
WO/2024/048604A1
A resin composition containing a polyimide precursor that includes a repeating unit represented by formula (1-1) and that has a polymerizable group content of 2 mmol/g or more and an amide bond content of 1.5 mmol/ g or less, a polymeriz...  
WO/2024/047959A1
The purpose of the present invention is to provide a semiconductor device having low electrical resistance while preventing defects in semiconductor elements caused by thermal expansion differences by laminating an Fe-Ni alloy metal laye...  
WO/2024/048121A1
In this invention, an outer flow adjustment member adjusts flow of a gas passing between an upper sealing member and a lower sealing member and causes the gas to flow downward along an outer surface of the lower sealing member. Thus, a s...  
WO/2024/045019A1
A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a first conductive layer, a second conductive layer, and a gate electrode. The second nitride-based semi...  
WO/2024/048122A1
This invention pertains to a substrate treatment technology for performing a prescribed substrate treatment on a substrate by supplying a treatment liquid to the substrate held by a rotating substrate holding unit, and collecting droplet...  

Matches 401 - 450 out of 816,376