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WO/2023/203428A1 |
The present invention provides a semiconductor device which has a high degree of integration. The semiconductor device has first and second transistors which are electrically connected to each other and a first insulating layer. The firs...
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WO/2023/203429A1 |
Provided is a high-definition display device. This display device has a transistor, wherein a semiconductor layer of the transistor is provided inside an opening formed in an interlayer insulation layer on a substrate. A floating-state c...
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WO/2023/202275A1 |
The present application relates to a silicon-on-insulator transverse device and a manufacturing method therefor. The device comprises: a substrate; a buried dielectric layer provided on the substrate; a drift region provided on the burie...
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WO/2023/201798A1 |
The present invention relates to a semiconductor structure and a preparation method therefor. The preparation method for the semiconductor structure comprises: providing a substrate; forming in the substrate a plurality of first trenches...
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WO/2023/204072A1 |
A semiconductor device according to the present invention comprises: a semiconductor layer that is of a first conductivity type and has a surface; a body region that is of a second conductivity type and is formed on the surface of the se...
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WO/2023/203425A1 |
The present invention provides a semiconductor device having a transistor of a very small size. In the semiconductor device, a second conductive layer is provided above the first conductive layer, the second conductive layer has a first ...
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WO/2023/201887A1 |
Provided in the present invention is a method for preparing a shield-gate trench field-effect transistor, comprising: forming a barrier stack on a substrate, comprising a first barrier layer, a second barrier layer, and a third barrier l...
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WO/2023/203846A1 |
[Problem] To provide a semiconductor material and a laminated semiconductor material, each of which is earth-conscious and is less harmful to living organisms. [Solution] The present invention comprises fibers each containing, as a main ...
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WO/2023/205169A1 |
In certain examples, methods and semiconductor structures are directed to devices and methods involving a semiconductor device with a current-blocking layer (CBL) and a first material layer having n-type dopant material that is activated...
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WO/2023/201448A1 |
A semiconductor element (100), comprising a semiconductor stack (104), an insulation structure (114), an electrode structure (130) and a protective layer (120), wherein the insulation structure (114) is arranged on the semiconductor stac...
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WO/2023/203417A1 |
Provided is a semiconductor device (10) having a transistor of a very small size. This semiconductor device has a first transistor (100) and a second transistor (200). The first transistor has a first conductive layer (112a), a first ins...
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WO/2023/203894A1 |
A semiconductor device according to the present invention is provided with a gate trench that is formed in a semiconductor layer, and a gate electrode that is embedded in the gate trench, with an insulating layer interposed therebetween....
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WO/2023/197368A1 |
Provided in the present invention are an array substrate and a manufacturing method therefor, and a display panel. The array substrate comprises an oxide semiconductor layer, a gate insulation layer, a gate electrode, an interlayer insul...
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WO/2023/197213A1 |
Embodiments of the present application relate to the technical field of semiconductors, provide a semiconductor device and a working method therefor, and an electronic device, for use in improving the performance of the semiconductor dev...
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WO/2023/197769A1 |
The present application provides a CMOS inverter, a storage chip, a memory and an electronic device. In the CMOS inverter, a support portion is located on the surface of a substrate and is provided with a first vertical sidewall and a se...
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WO/2023/199160A1 |
Provided is a semiconductor device (10) with a high degree of integration. This semiconductor device has a first and a second transistor that are electrically connected to each other, and a first insulation layer (110), wherein: the firs...
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WO/2023/199570A1 |
A semiconductor device 10 according to the present invention comprises a plurality of p-type deep layers 36, a plurality of n-type deep layers 37, an n-type drift layer 38, and an n-type high-concentration layer 39. The n-type high-conce...
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WO/2023/197202A1 |
For GAA nanosheet devices, a semiconductor structure (100) and fabrication method is provided. The semiconductor structure (100) comprises a substrate (101), a gate stack on the substrate (101) with a plurality of gate regions (103) and ...
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WO/2023/199159A1 |
The present invention provides a semiconductor device having a small occupancy area. A semiconductor device having: a first electroconductive layer; a second electroconductive layer positioned on the first electroconductive layer; a firs...
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WO/2023/200169A1 |
A VCSEL-based optical device having a common anode and a plurality of insulated cathode structures, and an optical module are disclosed. According to one aspect of the present embodiment, provided are: a VCSEL having a common anode struc...
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WO/2023/199722A1 |
An objective of the present invention is to provide an oxide semiconductor film capable of enhancing carrier mobility in a thin film transistor and stability relative to ambient temperature. An oxide semiconductor film according to one a...
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WO/2023/197251A1 |
The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a first passivation layer, and an electrode structure. The second nitride-based semiconductor layer is...
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WO/2023/199153A1 |
Provided is a transistor that can be miniaturized. Provided is a transistor that occupies a small area. A semiconductor device for providing a transistor having a short channel length has a first insulating layer, a semiconductor layer, ...
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WO/2023/197828A1 |
The present application relates to the technical field of semiconductors, and provides a transistor and a preparation method therefor, and a semiconductor device and a preparation method therefor, for use in ameliorating the problem that...
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WO/2023/200790A1 |
Anomalously large charge storage, charge release and/or charge transport is provided in room temperature MIS (Metal- Insulator-Semiconductor ) capacitive structures. These parameters can be l Ox or more ( often orders of magnitude more )...
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WO/2023/199181A1 |
The present invention provides a semiconductor device which enables miniaturization and high integration. According to the present invention, an oxide semiconductor, a first conductor, a first insulator, a second insulator, an inorganic ...
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WO/2023/197256A1 |
Disclosed are a transistor device and a method for manufacturing same. The transistor device comprises a gate, a gate insulator, and a body area and a drift area stacked in a first direction. The gate comprises a top surface and a bottom...
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WO/2023/197706A1 |
Provided in the present application are a field-effect transistor, a memory and an electronic device. The field-effect transistor comprises a laminated structure, a channel layer, a gate oxide layer and a gate electrode, wherein the lami...
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WO/2023/197707A1 |
A ferroelectric memory cell, a memory, and an electronic device. An oxygen barrier layer (05) and an oxygen storage layer (04) are introduced on one side of a ferroelectric layer (03); the oxygen storage layer (04) is adjacent to the fer...
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WO/2023/199932A1 |
Provided is a semiconductor device which is equipped with: a semiconductor substrate which has a top surface and a bottom surface and is provided with a drift region of a first conductive type; a transistor section which has a collector ...
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WO/2023/197387A1 |
A display panel and a manufacturing method therefor, and a mobile terminal. The display panel comprises a substrate, a thin film transistor layer, an oxygen supplementation function layer, and an electrode layer; the thin film transistor...
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WO/2023/197363A1 |
Disclosed in the present application are an array substrate, a manufacturing method therefor, and a display panel. The array substrate comprises a substrate, a first active layer, a first gate, a second active layer and a second gate whi...
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WO/2023/197088A1 |
Disclosed are a semiconductor element and a manufacturing method therefor. The semiconductor element comprises a substrate, a semiconductor stack, an insulating structure, and an electrode. The semiconductor stack is disposed on the subs...
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WO/2023/199472A1 |
The present invention addresses a scheme for a plurality of protection circuits without changing the layout of a switching element. A semiconductor device according to the present invention comprises: a main switching element that is for...
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WO/2023/195047A1 |
This semiconductor memory device comprises: a p layer 1 that is a semiconductor matrix; an n+ layer 2 that extends to one side; a second impurity layer n+ layer 3 that is in contact with the p layer 1 on the opposite side to the n+ layer...
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WO/2023/194211A1 |
A method of manufacturing a high electron mobility transistor (1), said method comprising the steps of: - providing a target wafer (10) comprising a target substrate (100); - providing a donor wafer (20) comprising an epitaxial donor fil...
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WO/2023/196292A1 |
A method (1100) of forming an integrated circuit includes first forming (1108) a resistor body and a transistor gate from a semiconductor layer over a substrate. Second, sidewall spacers are formed (1112) adjacent the resistor body and t...
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WO/2023/194698A1 |
An integrated circuit chip having a layered structure that defines processing circuitry. The chip has first and second outer layers providing external electrical contacts, and multiple inner layers including a partitioned semiconductor l...
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WO/2023/193370A1 |
Provided in the the embodiments of the present application is an IGBT device, which comprises an n-type semiconductor layer, wherein the following are formed in the n-type semiconductor layer: a p-type collector region; an n-type field c...
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WO/2023/196213A1 |
Embodiments of the disclosure advantageously provide semiconductor devices CFET in particular and methods of manufacturing such devices having a fully strained superlattice structure with channel layers that are substantially free of def...
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WO/2023/194836A1 |
Systems, devices and/or methods provided herein relate to a device that can facilitate generation of a pulse to affect a qubit and to a method that can facilitate fabrication of a semiconductor device. The semiconductor device comprises ...
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WO/2023/193875A1 |
The present disclosure relates to an elementary cell for a trench-gate semiconductor device and a corresponding production method. The elementary cell comprises: a first active area; a second active area; an inactive area separating the ...
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WO/2023/193083A1 |
A semiconducting quantum-dot (QD) nanoscale particle has a QD core, an inner shell coated on the QD core, an intermediate shell coated on the inner shell, and an outer shell coated on the intermediate shell. Each of the QD core, the inne...
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WO/2023/194825A1 |
The method provided herein relates to fabricating a semiconductor device having a co-integrated RTD and HEMT. A semiconductor device comprises an RTD and an HEMT that are co-integrated along a substrate. The fabrication method comprises ...
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WO/2023/193339A1 |
A method for manufacturing an IGBT device. An n-type charge storage region (22) is formed after a first trench (31) is formed, and the depth of the n-type charge storage region (22) is controlled by controlling the depth of the first tre...
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WO/2023/193342A1 |
The present application discloses a semiconductor diode, comprising an n-type substrate; an n-type drift region located on the n-type substrate; a p-type anode region located on the n-type drift region; and a plurality of n-type doped re...
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WO/2023/193288A1 |
An integrated MOSFET-JFET device made from a Silicon-Carbide (SiC) wafer has N+ source, P body diode, and upper N regions that form vertical MOSFETs on the sidewalls of polysilicon gates. An N substrate under the upper N region forms a d...
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WO/2023/194087A1 |
Embodiments of present invention provide a static random-access-memory (SRAM) device. The SRAM device includes a first set of nanosheets used in an n-type transistor; and a second set of nanosheets with one or more nanosheets of the seco...
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WO/2023/195279A1 |
In this light-emitting device, a pixel comprising a light-emitting element and a plurality of transistors for operating the light-emitting element is disposed on a substrate, the plurality of transistors including a first transistor havi...
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WO/2023/195761A1 |
The present invention relates to an oxide sintered body including In element, Zn element, Ga element, and oxygen and a thin film transistor including same, wherein the atomic ratio of In element to Zn element is 1 - 2:1, the atomic ratio...
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