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Matches 151 - 200 out of 216,463

Document Document Title
WO/2024/042777A1
Provided is a group-III element nitride substrate that is capable of having an improved yield. A method for inspecting a group-III element nitride substrate according to an embodiment of the present invention comprises: preparing a group...  
WO/2024/040515A1
A method for manufacturing a nitride-based semiconductor device is provided. The method includes steps as follows. An epitaxy structure is formed on a silicon-based substrate. An oxide structure is formed on the epitaxy structure. A mask...  
WO/2024/040883A1
The embodiments of the present disclosure relate to the field of semiconductors. Provided are a semiconductor structure and a manufacturing method therefor. The structure comprises: a substrate, which comprises a first active area and a ...  
WO/2024/043234A1
A majority-decision logic device 1 comprises a non-magnetic semiconductor layer 10 made of a material that, when irradiated with light having at least two kinds of mutually different polarization states, generates electron spin waves hav...  
WO/2024/041122A1
Provided in the present disclosure are a high-electron-mobility transistor and a preparation method therefor. The high-electron-mobility transistor comprises a substrate, an epitaxial layer, a source electrode, a drain electrode, a gate ...  
WO/2024/040698A1
Embodiments of the present disclosure relate to the field of semiconductors, and provide a semiconductor structure manufacturing method and a semiconductor structure. The semiconductor structure manufacturing method comprises: providing ...  
WO/2024/042419A1
Provided is a storage device which can be micro-fabricated or highly integrated. This storage device comprises a memory cell and a first insulator. The memory cell comprises a capacitive element and a transistor disposed on the capacitiv...  
WO/2024/041431A1
Provided in the present application are an integrated device, an electronic device, and a method for manufacturing an integrated device. The integrated device comprises a substrate, the substrate comprising a first substrate and a second...  
WO/2024/041626A1
Disclosed in the present application are a gate structure, a semiconductor device, and a method for preparing a semiconductor device. The gate structure comprises a gate portion and a field plate portion, wherein the field plate portion ...  
WO/2024/042602A1
This quantum device includes: a first surface; a waveguide extending in a first direction parallel to the first surface; a plurality of nano-pillars connected to the first surface and arranged in the first direction; colour centres respe...  
WO/2024/040645A1
The embodiments of the present disclosure provide a semiconductor structure and a manufacturing method therefor, and a memory. The semiconductor structure comprises: a substrate; active pillars, which are located on a surface of the subs...  
WO/2024/040622A1
The embodiments of the present disclosure disclose a semiconductor structure. The semiconductor structure comprises: a substrate, and an isolation structure located in the substrate, wherein the isolation structure defines an active regi...  
WO/2024/042404A1
Provided is a novel semiconductor device. A vertical channel transistor is provided overlapping a capacitive element. A ferroelectric body is used as a dielectric layer of the capacitive element. It is preferable that the ferroelectric b...  
WO/2024/041860A1
Techniques for co-integrating gate-all-around nanosheet devices having bottom dielectric isolation with an ideal vertical P-N-P diode on a common substrate are provided. In one aspect, a semiconductor structure includes: a diode in a fir...  
WO/2024/040463A1
A semiconductor device includes a first and a second nitride-based semiconductor layers, a first passivation layer, a gate electrode, and a first field plate. The first passivation layer has a first portion with at least one thickness mo...  
WO/2024/042408A1
Provided is a semiconductor having a small occupied area. This semiconductor device has a first conductive layer, a second conductive layer on the first conductive layer, a first insulating layer on the second conductive layer, a semicon...  
WO/2024/042809A1
A chip-scale package semiconductor device (1) which can be mounted face-down comprises a semiconductor substrate (32), a semiconductor layer (40) formed on the semiconductor substrate (32), a vertical field effect transistor (10) formed ...  
WO/2024/040465A1
A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a doped nitride-based semiconductor layer, and a gate electrode. The doped nitride-based semiconductor l...  
WO/2024/042814A1
This field effect transistor suppresses the dielectric breakdown of a gate insulating film when a current diffusion n-layer is provided. The field effect transistor includes: a semiconductor substrate having a trench in the upper face th...  
WO/2024/041311A1
Provided are a display panel and display apparatus, which belong to the technical field of display. The display panel comprises a base substrate, a plurality of first pixels and a plurality of second pixels. The base substrate has a spec...  
WO/2024/040600A1
A semiconductor device includes a first and a second nitride-based semiconductor layers, a drain, a source electrodes, a gate electrode, a plurality of field plates, a conductive layer, and at least one contact via. The field plates are ...  
WO/2024/043001A1
A semiconductor device including a semiconductor substrate having a first surface on which a first electrode is disposed, a first semiconductor region, of a first conductivity type, disposed on a second surface of the semiconductor subst...  
WO/2024/040513A1
A semiconductor device includes a substrate, a plurality of epitaxy structures, a protection layer, and a dielectric layer. The substrate includes a plurality of first regions and a second region having at least one groove surrounding ea...  
WO/2024/041861A1
Backside and frontside contact structures wrapping around source/drain regions provide increased contact areas for electrical connections and allow increased silicide areas. Sidewall metallization of epitaxially grown source/drain region...  
WO/2024/040843A1
The present application provides a display panel (100) and a drivr substrate (1) thereof. The drive substrate (1) is used for driving an inorganic light-emitting diode to emit light. The drive substrate (1) comprises a substrate (11) as ...  
WO/2024/041001A1
The present invention provides a high-voltage power semiconductor device and a manufacturing method therefor. A plurality of second resistive field plate structures extending through an epitaxial layer to a substrate in a first direction...  
WO/2024/037873A1
Backside contacts wrapping around source/drain regions provide increased contact areas for electrical connections between field-effect transistors and metallization layers. Cavities formed within a device layer expose sidewalls of select...  
WO/2024/036826A1
Embodiments of the present application provide a vertical transistor, a storage unit and a manufacturing method therefor. In the vertical transistor provided by the embodiments of the present application, a semiconductor layer is configu...  
WO/2024/039417A1
Various 3D memory cells, array architectures, and processes are disclosed. In an embodiment, a memory cell structure is provided that is formed by a process of alternately depositing multiple semiconductor layers and sacrificial layers t...  
WO/2024/037259A1
A laterally diffused metal oxide semiconductor device and a preparation method therefor. The laterally diffused metal oxide semiconductor device (1) comprises: a substrate (10), which is provided with a trench (16); a drift region (30), ...  
WO/2024/036486A1
A semiconductor device includes a first III-V nitride-based layer, a second III-V nitride-based layer, a nitride-based transition layer, and a nitride-based transistor. The first III-V nitride-based layer is disposed over a substrate by ...  
WO/2024/039416A1
Various 3D memory cells, array architectures, and processes are disclosed. In an embodiment, a memory cell structure is provided that is formed by a process of alternately depositing multiple semiconductor layers and insulating layers to...  
WO/2024/037906A1
The invention relates to a semiconductor device comprising a semiconductor switching element, a semiconductor device package for encapsulating the semiconductor switching element, a first electrode for providing a first voltage to the se...  
WO/2024/038685A1
This semiconductor device comprises: a multi-gate transistor in which a plurality of field effect transistors each having a pair of main electrodes and gate electrode arranged between the pair of main electrodes are electrically connecte...  
WO/2024/036747A1
The present disclosure relates to a semiconductor structure and a method for forming same. The method for forming the semiconductor structure comprises the following steps: forming a substrate, and a plurality of active regions which are...  
WO/2024/036762A1
The present application provides a thin film transistor of a vertical structure and an electronic device. According to the thin film transistor of the vertical structure, a second doped portion is arranged in a via hole of an insulating ...  
WO/2024/037186A1
Provided in the present application is an electronic device, comprising a reverse conducting IGBT power device. Further provided in the present application is a preparation method for a reverse conducting IGBT power device. The reverse c...  
WO/2024/039853A1
In some embodiments, an integrated circuit includes multiple charge storage regions configured to receive charge carriers from a photodetection region in response to a single excitation of a sample. In some embodiments, an integrated cir...  
WO/2024/038504A1
This silicon carbide semiconductor device has, on the upper surface of a semiconductor layer (20), a trench (6) that passes through a source region (3) and a body region (5) and reaches a drift layer (2). On the bottom portion in the tre...  
WO/2024/036665A1
The present disclosure relates to the technical field of semiconductors, and relates to a semiconductor structure and a forming method therefor, and a memory. The semiconductor structure of the present disclosure comprises a substrate, a...  
WO/2024/039432A1
A semiconductor device having one or more bifacial semiconductor wafers. The bifacial semiconductor wafer includes a first array of semiconductor dies on a first planar surface and a second array of semiconductor dies on a second planar ...  
WO/2024/036895A1
A display panel (100) and an electronic terminal. The display panel comprises a substrate (10), an active layer (20) located on the substrate (10), a first electrically conductive layer (30) located on the side of the active layer (20) c...  
WO/2023/231745A9
A semiconductor structure and method for manufacturing thereof are provided. The semiconductor structure includes a vertical transistor. The vertical transistor includes a semiconductor body extending in a first direction. The semiconduc...  
WO/2024/037347A1
A semiconductor structure and a method for forming same, wherein the method for forming the semiconductor structure comprises: forming on a semiconductor substrate (200) linear semiconductor patterns (203) extending in a first direction ...  
WO/2024/036792A1
The present disclosure relates to the field of power semiconductors, and particularly discloses a super-junction semiconductor device and a manufacturing method therefor. The manufacturing method comprises: etching a first predetermined ...  
WO/2024/039647A1
Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide electronic devices which comprise a dipole region and meet reduced thickness and...  
WO/2024/039968A2
A high electron mobility transistor comprises a semiconductor layer structure that includes a channel layer and a barrier layer and source and drain contacts on the semiconductor layer structure. A gate contact and a multi-layer passivat...  
WO/2024/036518A1
The present disclosure belongs to the technical field of radio frequencies. Provided are a radio-frequency switch unit and a preparation method therefor, and an electronic device. The radio-frequency switch unit in the present disclosure...  
WO/2024/037525A1
A ferroelectric random-access memory (FeRAM) cell (10) is provided. The FeRAM cell (10) includes a vertical channel (310) between a bottom source/drain region and a top source/drain region (630); a gate oxide (320) surrounding the vertic...  
WO/2024/036676A1
The present disclosure provides a fin transistor structure and a manufacturing method therefor. The manufacturing method for a fin transistor structure comprises: providing a substrate, wherein a fin-shaped portion extends out of the top...  

Matches 151 - 200 out of 216,463