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Patent Searching and Data


Matches 1 - 50 out of 284,168

Document Document Title
WO/2021/037794A3
The invention relates to a trench transistor (100), comprising: a semiconductor region (2); a trench structure (1) formed in the semiconductor region (2); a gate isolation layer (3, 4) and an electrically conductive gate layer (5), in th...  
WO/2021/090110A1
Provided is an image capture apparatus of low power consumption. A first circuit and a second circuit are provided in a pixel. The first circuit can generate image capture data and can hold differential data relative to data acquired in ...  
WO/2021/090092A1
The present invention provides a storage device which has a small signal transmission delay and a low power consumption, wherein an NAND-type flash memory and a controller as well as a controller and a cash memory are respectively connec...  
WO/2021/090105A1
A display device includes a first pixel circuit including a light-receiving element and a first transistor, and a second pixel circuit including a light-emitting element and a second transistor. The light-receiving element includes an ac...  
WO/2021/088232A1
A cell structure of a silicon carbide MOSFET device, comprising a first conductivity type drift region (3) located above a first conductivity type substrate (2). A main trench is provided in the surface of the first conductivity type dri...  
WO/2021/090116A1
Provided is a method for manufacturing a semiconductor device with less variation in characteristics. This method includes: forming a second insulator, an oxide, a conductive layer, and an insulating layer on a first insulator; depositin...  
WO/2021/090115A1
The present invention provides a semiconductor device in which variation in properties is reduced. The present invention has a first circuit region and a second circuit region on a substrate. The first circuit region has a plurality of f...  
WO/2021/088824A1
An array substrate, a display apparatus and an electrostatic protection unit. The array substrate comprises: a first wire (1), a second wire (2) and a first electrostatic protection unit (E1). The first electrostatic protection unit (E1)...  
WO/2021/089488A1
The present invention provides method for forming a diode, the method comprises providing a first graphene layer structure on a first substrate; providing a second graphene layer structure on a second substrate; treating the first graphe...  
WO/2021/091995A1
Metal gate stacks and integrated methods of forming metal gate stacks are disclosed. Some embodiment comprise MoN as a PMOS work function material. Some embodiments comprise TiSiN as a high-κ capping layer. Some embodiments provide impr...  
WO/2021/092117A1
A lateral DMOS transistor structure includes a substrate of a first dopant polarity, a body region of the first dopant polarity, a source region, a drift region of a second dopant polarity, a drain region, a channel region, a gate struct...  
WO/2021/090944A1
Provided is a semiconductor device having a high breakdown-voltage characteristic and capable of preventing a breakdown due to a large transient current. The semiconductor device has a super-junction structure comprising a first conducti...  
WO/2021/088231A1
A cellular structure (200) of a silicon carbide MOSFET device, and a silicon carbide MOSFET device. The cellular structure (200) of the silicon carbide MOSFET device comprises: second conductive well regions (203) located on two sides of...  
WO/2021/090103A1
A method for making a metal-organic framework, MOF, as nanosheets (400), includes providing (2000) a MXene (120), wherein the MXene (120) has a general formula of Mn+1XnTx, with n = 1-3, M represents an early transition metal, X is C and...  
WO/2021/089808A1
Disclosed is an insulated gate bipolar transistor comprising at least following layers: a source layer of a first conductivity type, a base layer of a second conductivity type, wherein the source layer and the base layer electrically con...  
WO/2021/089947A1
The invention relates to a two-dimensional crystal wafer of group 13 or III element nitride which is delimited by a face of orientation N, an opposing face of orientation E depending on the group 13 or III element, E being selected prefe...  
WO/2021/089230A1
The invention relates to a vertical field-effect transistor (200, 300, 400, 500, 600) having: a drift region (204); a semiconductor fin (230) on or above the drift region (204); a connection region (212) on or above the semiconductor fin...  
WO/2021/088156A1
Disclosed is a split-gate trench power semiconductor device, comprising: an active region provided on a semiconductor substrate, wherein the active region comprises a first well region and a second well region, longitudinally stacked alo...  
WO/2021/091685A1
A silicon carbide MOSFET Includes first and second source regions respectively disposed in the first and second well regions. Each of the first and second source regions extends up to a top surface of the substrate. First and second chan...  
WO/2021/090657A1
This semiconductor device includes: a semiconductor material layer forming a channel layer; a pair of source/drain electrodes formed on the semiconductor material layer; and a gate electrode disposed between the pair of source/drain elec...  
WO/2021/090104A1
Provided is a semiconductor device having little variation in characteristics. The semiconductor device has a plurality of circuits having transistors, the transistors each have an oxide in a channel formation region, the density of tran...  
WO/2021/088912A1
A thin film transistor and a preparation method therefor, an array substrate and a preparation method therefor, and a display panel. The preparation method for the thin film transistor comprises: forming an active layer (2) comprising a ...  
WO/2021/088186A1
A silicon carbide Schottky clamped transistor, relating to the field of semiconductor devices. The silicon carbide Schottky clamped transistor comprises an N+-type substrate collector region (1); an N-type collector region (2) and a P-ty...  
WO/2021/088478A1
An insulated gate bipolar transistor, comprising an anode second conductivity-type region and an anode first conductivity-type region provided on a drift region (3); the anode first conductivity-type region comprises a first region (17) ...  
WO/2021/090106A1
Provided is a semiconductor device having little variation in transistor characteristics. The semiconductor device comprises an oxide semiconductor film, a source electrode and a drain electrode on the oxide semiconductor film, an interl...  
WO/2021/090442A1
The purpose of the present invention is to reduce defects in a fuel cell module and to reduce manufacturing costs by identifying and taking countermeasures against cells exhibiting short circuit defects, from among fuel cells manufacture...  
WO/2021/091020A1
The present embodiments provide: a non-volatile multi-level optical memory which can be operated at multiple levels by means of one gate, as a result of forming an interface trap between a channel and a gate insulator by means of a visco...  
WO/2021/086189A1
The present invention relates to a field-effect transistor, to a packaged field-effect transistor and to an electronic device comprising the same. More in particular, the present invention relates to a field-effect transistor having an i...  
WO/2021/082150A1
Disclosed are a thin film transistor structure, a GOA circuit, and a display device. The thin film transistor structure defines a plurality of thin film transistors by patterning an active layer. Therefore, when a defect occurs in a gate...  
WO/2021/086588A1
A vapor chamber that includes a housing including a first sheet and a second sheet opposing each other and joined together at outer edges of the first sheet and the second sheet and defining a hollow vapor flow pass therein; a working fl...  
WO/2021/086440A1
Methods for reducing manufacturing cost and improving the reliability of non-volatile memories using NAND strings with polysilicon channels and p-type doped source lines are described. A NAND string may include a polysilicon channel that...  
WO/2021/086872A1
Devices, methods and techniques are disclosed for providing a multi-layer diode without voids between layers. In one example aspect, a multi-stack diode includes at least two Drift Step Recovery Diodes (DSRDs). Each DSRD comprises a firs...  
WO/2021/084369A1
Provided is a semiconductor device with little variation in properties. The present invention has a first insulator, transistors on the first insulator, a second insulator on the transistors, a third insulator on the second insulator, a ...  
WO/2021/081992A1
The present disclosure is related to a thin film transistor. The thin film transistor may include an active layer; a gate insulating layer on the active layer; and a gate and a plurality of metal films on the gate insulating layer. The p...  
WO/2021/086788A1
Processing methods may be performed to produce semiconductor structures that may include a high-k dielectric material. The methods may include forming a silicon layer over a semiconductor substrate. The semiconductor substrate may includ...  
WO/2021/082159A1
A semiconductor power device terminal structure comprising: an n-type epitaxial layer (20) and, disposed in the n-type epitaxial layer (20): at least one trench (40) comprising two parts, a trench upper part (41) and a trench lower part ...  
WO/2021/084367A1
The present invention provides a display device capable of displaying high-resolution images. The display device is provided with a first layer and a second layer which are stacked together. The first layer is provided with an arithmetic...  
WO/2021/082337A1
A method for improving the tip discharge defect and a manufacturing method for a semiconductor device. The method for improving the tip discharge defect comprises: providing a wafer structure, the wafer structure having a device area (11...  
WO/2021/084368A1
The power consumption of a power storage device is reduced. A safe power storage device is provided. Furthermore, the safety of a battery monitored by a semiconductor device is improved. Moreover, power consumption, for example, power in...  
WO/2021/085558A1
A semiconductor device, having: an Si substrate (1); a first transistor (111) formed on the Si substrate (1), the first transistor (111) having a first source electrode (11), a first gate region (13), and a first drain electrode (14); an...  
WO/2021/085436A1
Provided is a semiconductor integrated circuit comprising: a P-type substrate; an embedded insulating film provided on the substrate; a P-type active layer provided on the embedded insulating film; a cathode region formed in the active l...  
WO/2021/085078A1
This silicon carbide semiconductor device has: a silicon carbide substrate; a first electrode; and a second electrode. The silicon carbide substrate has a first main surface, a second main surface, a first impurity region, a second impur...  
WO/2021/085158A1
The present invention addresses the problem of properly shortening a processing step for processing a substrate in which a silicon layer and a silicon germanium layer are alternatively stacked. The present invention provides a method f...  
WO/2021/084652A1
A bottom part of a contact Ta column 47a is connected to an N+ layer 3a and a P+ layer 4a, and a gate HfO2 layer 36 is connected to side surfaces of Si columns 6a, 6b and the contact Ta column 47a, and to the upper surface of an SiO2 lay...  
WO/2021/082066A1
Provided are a display panel and a method for manufacture thereof, said method comprising: fabricating a primary gate and a secondary gate on a glass substrate (11), at least part of the secondary gate having a light-transmitting region;...  
WO/2021/085437A1
Provided is a semiconductor integrated circuit comprising a substrate of a first conductivity type, a buried insulating film provided on the substrate, an active layer of a first conductivity type provided on the buried insulating film, ...  
WO/2021/085642A1
Provided are a tunnel junction laminated film having high thermal stability, and a magnetic memory element and a magnetic memory using a tunnel junction laminated film. A tunnel junction laminated film 1 includes a recording layer 14 hav...  
WO/2021/082094A1
A BCE IGZO TFT device and a manufacturing method therefor, characterized by the method comprising: providing a substrate; depositing a first metal layer on the substrate, and subjecting the first metal layer to a patterning process to fo...  
WO/2021/086646A1
Some embodiments include an integrated assembly having digit lines supported by a base and extending along a first direction. A shield-connection-line is supported by the base and extends along the first direction. Transistor active regi...  
WO/2021/084070A1
A semiconductor device, comprises a semiconductor body (100) comprising a first surface (101), a second surface (102) opposite to the first surface (101) in a vertical direction (y), an edge termination region (210), and an active region...  

Matches 1 - 50 out of 284,168