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WO/2021/211348A1 |
Methods and apparatus for passivating a target are provided herein. For example, a method includes a) supplying an oxidizing gas into an inner volume of the process chamber; b) igniting the oxidizing gas to form a plasma and oxidize at l...
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WO/2021/205941A1 |
This three-dimensional array device include a plurality of layers in a height direction, the device comprising a first two-dimensional array circuit that is positioned in a first layer, and a second two-dimensional array circuit that is ...
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WO/2021/207224A1 |
A semiconductor device is disclosed which comprises a plurality of two-terminal resistive switching devices (420), wherein an electrode (322) in contact with a resistive switching layer (324) has a root mean square surface roughness (425...
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WO/2021/206908A1 |
Methods are provided herein for improving oxygen content control in a Metal-Insulator-Metal (MIM) stack of an RERAM cell, while also maintaining throughput. More specifically, a single chamber solution is provided herein for etching and ...
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WO/2021/205138A1 |
Display devices for displaying a pattern are disclosed. In one arrangement, a pixel element having a layered structure is provided. The layered structure comprises at least one phase change material layer thermally switchable between at ...
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WO/2021/203736A1 |
A resistive random access memory unit, comprising: two coupled transistors (T1, T2) and n resistive units (R1, R2, …, Rn); the n resistive units (R1, R2, …, Rn) are sequentially connected to one another by means of the electrodes the...
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WO/2021/191734A1 |
Provided is a storage device having high storage capacity and low power consumption. The storage device comprises a first layer and a second layer which includes the first layer. The first layer includes a circuit, and the second layer i...
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WO/2021/186199A1 |
A method for manufacturing a 3D vertical array of memory cells is disclosed. The method comprises: forming on a substrate a stack of dielectric material layers comprising first and second dielectric material layers alternated to each oth...
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WO/2021/186266A1 |
A phase change material switch includes a phase change layer disposed on a metal liner. A gate dielectric layer is disposed on the phase change layer. A metal gate liner is disposed on the gate dielectric layer.
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WO/2021/181188A1 |
A method may include forming two vertical transport field effect transistors stacked one atop the other and separated by a resistive random access memory structure. The two vertical transport field effect transistors may include a source...
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WO/2021/181173A1 |
A phase change memory (PCM) structure configured for performing a gradual reset operation includes first and second electrodes and a phase change material layer disposed between the first and second electrodes. The PCM structure further ...
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WO/2021/171454A1 |
This arithmetic circuit comprises: a variable resistance element that has three terminals of a first terminal, a second terminal and a third terminal and that can change the resistance value thereof; a first electrode connected to the fi...
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WO/2021/171480A1 |
This arithmetic circuit comprises: a resistance change device having three terminals, which are a first terminal, a second terminal, and a third terminal, and being able to change a resistance value; an input line connected to the first ...
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WO/2021/172230A1 |
In the present invention, existing variable resistance elements can be used as is by connecting two analog variable resistance elements (101, 102) in series, each of the analog variable resistance elements comprising an upper electrode, ...
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WO/2021/161117A1 |
A method is presented for improved linearity of a phase change memory (PCM) cell structure. The method includes forming a bottom electrode (12) over a substrate (10), constructing a PCM stack (20) including a plurality of PCM layers each...
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WO/2021/158320A1 |
Methods, systems, and devices supporting configurable resistivities for lines in a memory device, such as access lines in a memory array are described. For example, metal lines at different levels of a memory device may be oxidized to di...
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WO/2021/152215A1 |
A memristor material is disclosed which has the chemical formula R1 -XAXB03, wherein R is one of Eu, Gd, Tb, Nd, A is one of Ca, Sr, Ba, B is one of Mn, Co, Ni, and x is larger than 0 but smaller than 1, a preferred example being Gd1-xCa...
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WO/2021/150391A1 |
An electronic device comprising a stack structure comprising one or more stacks of materials and one or more silicon carbide materials adjacent to the one or more stacks of materials. The materials of the one or more stacks comprise a si...
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WO/2021/142684A1 |
A phase-change memory (PCM) device includes a first electrode, a second electrode, a memory layer, and a heater. The memory layer includes a phase-change material and is electrically coupled between the first electrode and the second ele...
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WO/2021/135924A1 |
Disclosed are a resistive random access memory and a manufacturing method. A memory area of the resistive random access memory comprises a first metal interconnection line, a resistive random access memory unit and a second metal interco...
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WO/2021/138124A1 |
Techniques are described to form a liner to protect a material, such as a storage element material, from damage during subsequent operations or phases of a manufacturing process. The liner may be bonded to the material (e.g., a chalcogen...
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WO/2021/128994A1 |
The present invention provides a superlattice memristor functional layer material, and a memristor unit comprising the superlattice memristor functional layer and a preparation method therefor. The superlattice memristor functional layer...
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WO/2021/132602A1 |
[Problem] An objective of the present invention is to provide a ferroelectric thin film that is very highly ferroelectric and is stable enough to withstand actual use compared to conventional ferroelectric thin films formed from scandium...
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WO/2021/124072A1 |
A resistive random access memory (RRAM) structure includes top and bottom electrodes (110, 108) electrically coupled with first and second metal connection lines, respectively, the first and second metal connection lines providing electr...
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WO/2021/120621A1 |
A resistive random access memory unit structure, consisting of a first transistor and a second transistor that are connected in parallel, and a resistive switching unit that is connected to the first transistor and the second transistor,...
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WO/2021/120620A1 |
Disclosed is a phase change memory unit, comprising, from bottom to top: a bottom electrode, a heating electrode, a phase change unit and a top electrode, the phase change unit being a cylinder longitudinally provided, and comprising, fr...
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WO/2021/126602A1 |
Some embodiments include a memory cell having a non-ohmic device between a transistor source/drain region and a capacitor. Some embodiments include a memory cell having a transistor with a first source/drain region, a second source/drain...
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WO/2021/122358A1 |
An aspect of the invention relates to an elementary cell (100) comprising a device and a non-volatile resistive memory (102) mounted in a series, the device (101) comprising: - an upper selector electrode (1013), - a lower selector elect...
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WO/2021/116804A1 |
A bottom electrode(110) is deposited on top of a substrate(105). A dielectric material layer(115) is deposited on top of the bottom electrode(110). A hole is created in the dielectric material layer(115). A lift off layer(116) is spun on...
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WO/2021/118415A1 |
The group of inventions relates to technology for operating a memristor having a filamentary switching mechanism, and can be used for controlling the stable operation of such a memristor by automatically adjusting the duration of voltage...
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WO/2021/108405A1 |
Disclosed is a tunable inductor device having a substrate, a planar spiral conductor having a plurality of spaced-apart turns disposed over the substrate, and a phase change switch (PCS) having a patch of a phase change material (PCM) di...
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WO/2021/102789A1 |
Local word line driver device, memory device, and fabrication method are provided. A local word line driver device includes a substrate and an array of transistor structures formed on the substrate. The transistor structures are configur...
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WO/2021/099798A1 |
A method for manufacturing a memory resistor device. A first layer of a dielectric material is deposited onto a first electrode. A subsection of the first layer of the dielectric material is removed to expose one or more edges of the die...
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WO/2021/099309A1 |
An aspect of the invention concerns an OxRAM resistive memory cell (50) comprising a lower electrode (2), an upper electrode (53) and an active layer (54) which extends between the lower electrode and the upper electrode. The active laye...
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WO/2021/101436A1 |
Various embodiments may provide an electronic synapse device. The electronic synapse device may include a body including a doped chalcogenide layer including a chalcogenide material and a dopant. The electronic synapse device may also in...
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WO/2021/092943A1 |
A phase change memory (1) comprises a lower electrode (20), a heating component (30), a phase change layer (50), and an upper electrode (70). The heating component (30) is coupled to the lower electrode (20). The phase change layer (50) ...
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WO/2021/096674A1 |
Methods, systems, and devices for a low resistance crosspoint architecture are described. A manufacturing system may deposit a thermal barrier material, followed by a first layer of a first conductive material, on a layered assembly incl...
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WO/2021/095974A1 |
A memcapacitor may comprise: a first electrode of a metal-doped perovskite composition; a second electrode on the first electrode; and a dielectric thin film of a perovskite composition, which is disposed between the first electrode and ...
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WO/2021/097374A1 |
Disclosed is a reconfigurable transistor device having a substrate, a plurality of first transistor fingers disposed in a first region over the substrate, and a phase change switch (PCS) having a patch of a phase change material (PCM) di...
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WO/2021/096288A1 |
An objective of the present invention is to provide, in connection with a memory element containing a chalcogen compound, a composition for stable operation of the memory element, a memory structure suitable for the composition, a method...
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WO/2021/091429A1 |
Use: for evaluating the activation energies of oxygen ion diffusion inside memristor filaments. The essence of the invention lies in the fact that the present method for evaluating the activation energies of oxygen ion diffusion in a mem...
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WO/2021/083934A1 |
The invention relates to a process for the production of a molecular layer on a substrate using atomic layer deposition (ALD) techniques, for use in electronic components, in particular in memory elements of the ReRAM type. The present i...
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WO/2021/084408A1 |
A low forming voltage NVM device is provided by forming a pair of sacrificial conductive pads on an interconnect dielectric material layer that embeds a pair of second electrically conductive structures and a patterned material stack. On...
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WO/2021/082808A1 |
The present invention provides a new doped Ge-Sb-based phase change material, a phase change memory (PCM) for the material, and a specific method for operating the PCM. The chemical general formula of the doped Ge-Sb-based material is Mx...
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WO/2021/086556A1 |
An electronic device comprising a stack structure comprising one or more stacks of materials and a metal oxide material adjacent to the stacks of materials. The materials of the stacks comprise one or more chalcogenide materials. The met...
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WO/2021/083010A1 |
A superlattice phase-change thin film with a low density change, a phase-change memory and a preparation method. The superlattice phase-change thin film comprises first phase-change layers (7) and second phase-change layers (8) that are ...
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WO/2021/077389A1 |
A memory element array, including a plurality of bit lines, a plurality of word lines and a plurality of transistors. The plurality of word lines intersect and are electrically insulated from the bit lines; each of the plurality of trans...
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WO/2021/078699A1 |
The present invention relates to an electronic switching device comprising an organic molecular layer in contact with a metal nitride electrode for use in memory, sensors, field-effect transistors or Josephson junctions. More particularl...
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WO/2021/072575A1 |
Three-dimensional (3D) memory devices and methods for forming the same. The 3D memory device includes parallel lower and upper bit lines (308A, 308B), parallel word lines (312), lower and upper memory cells (314A, 314B), a lower bit line...
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WO/2021/072576A1 |
A method for forming a 3D memory device is provided. A lower bit line contact and a lower bit line in contact with the lower bit line contact are formed (602). Lower memory cells are formed above and in contact with the lower bit line (6...
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