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Matches 1 - 50 out of 6,628

Document Document Title
WO/2021/083934A1
The invention relates to a process for the production of a molecular layer on a substrate using atomic layer deposition (ALD) techniques, for use in electronic components, in particular in memory elements of the ReRAM type. The present i...  
WO/2021/084408A1
A low forming voltage NVM device is provided by forming a pair of sacrificial conductive pads on an interconnect dielectric material layer that embeds a pair of second electrically conductive structures and a patterned material stack. On...  
WO/2021/082808A1
The present invention provides a new doped Ge-Sb-based phase change material, a phase change memory (PCM) for the material, and a specific method for operating the PCM. The chemical general formula of the doped Ge-Sb-based material is Mx...  
WO/2021/086556A1
An electronic device comprising a stack structure comprising one or more stacks of materials and a metal oxide material adjacent to the stacks of materials. The materials of the stacks comprise one or more chalcogenide materials. The met...  
WO/2021/083010A1
A superlattice phase-change thin film with a low density change, a phase-change memory and a preparation method. The superlattice phase-change thin film comprises first phase-change layers (7) and second phase-change layers (8) that are ...  
WO/2021/077389A1
A memory element array, including a plurality of bit lines, a plurality of word lines and a plurality of transistors. The plurality of word lines intersect and are electrically insulated from the bit lines; each of the plurality of trans...  
WO/2021/078699A1
The present invention relates to an electronic switching device comprising an organic molecular layer in contact with a metal nitride electrode for use in memory, sensors, field-effect transistors or Josephson junctions. More particularl...  
WO/2021/072575A1
Three-dimensional (3D) memory devices and methods for forming the same. The 3D memory device includes parallel lower and upper bit lines (308A, 308B), parallel word lines (312), lower and upper memory cells (314A, 314B), a lower bit line...  
WO/2021/072576A1
A method for forming a 3D memory device is provided. A lower bit line contact and a lower bit line in contact with the lower bit line contact are formed (602). Lower memory cells are formed above and in contact with the lower bit line (6...  
WO/2021/071629A1
The disclosed technology generally relates to a barrier layer comprising titanium silicon nitride, and more particularly to a barrier layer for nonvolatile memory devices, and methods of forming the same. In one aspect, a method of formi...  
WO/2021/056749A1
An artificial nerve synaptic device and a preparation method therefor. The artificial nerve synaptic device comprises a first electrode layer (11), a second electrode layer (13), and a functional layer (12) provided between the first ele...  
WO/2021/054737A1
A resistive switching element is disclosed. The resistive switching element comprises: a first oxide layer and a second oxide layer stacked to each other so as to form an interface, and made of different metal oxides; a two-dimensional e...  
WO/2021/054898A1
Herein provided is a multilayered structure including one or more nanocrystalline layers each comprising a transition metal dichalcogenide, one or more substantially amorphous electrically insulating layers each comprising a transition m...  
WO/2021/054004A1
A storage element according to one embodiment comprises: a first electrode; a second electrode; a storage layer provided between the first electrode and the second electrode and containing at least copper, aluminum, zirconium and telluri...  
WO/2021/048522A1
A correlated electron material (CEM) device capable of switching between impedance states is disclosed, wherein the CEM is formed from one or more post transition metal oxide (PTMO) or post transition metal chalcogenide (PTMC) compounds ...  
WO/2021/042422A1
A three-dimensional stacked phase change memory and a preparation method therefor. The preparation method specifically comprises: first preparing, on a substrate, a multi-layer structure formed by alternately providing horizontal electro...  
WO/2021/039988A1
A conductive-bridge memory device comprises a memory cell that includes: a first metal layer 11; a second metal layer 12; a first insulation body layer 13 having a first surface 13a facing the first metal layer 11 and a second surface 13...  
WO/2021/038198A1
Fabrication of a correlated electron material (CEM) device includes application of rapid thermal annealing to at least one doped metal oxide layer, preferably of carbon doped nickel oxide by a nanosecond laser pulse, either before or aft...  
WO/2021/032947A1
A composition comprising: a non-ordered substrate and a metal chalcogenide present on at least one surface of the substrate is disclosed. A method of forming a metal chalcogenide on ordered substrates is also disclosed.  
WO/2021/021863A1
Methods of depositing an encapsulation stack without damaging underlying layers are discussed. The encapsulation stacks are highly conformal, have low etch rates, low atomic oxygen concentrations, good hermeticity and good adhesion. Thes...  
WO/2021/018515A1
The quantum device comprises a transmission structure, wherein based on its geometrical arrangement, interference and quantum collapse, the transmission structure is designed such that quantum waves emitted by at least two bodies, for ex...  
WO/2021/014810A1
This non-volatile memory cell is configured of a non-volatile memory element 50 of a variable resistance type and a transistor TR for selection, wherein one terminal of the non-volatile memory element 50 is connected to one source/drain ...  
WO/2021/003904A1
The present invention provides a phase change memory and a manufacturing method thereof. The phase change memory comprises a substrate, multiple phase change memory cells, and an isolation material layer. The multiple phase change memory...  
WO/2021/003683A1
Disclosed are a silicon oxide-based memristor based on a solution method, and a preparation method and application thereof, said method comprising: (1) preparing a lower electrode on a substrate, or providing or directly preparing a lowe...  
WO/2021/003028A1
Methods, systems, and devices for memory device with a split pillar architecture are described. A memory device may include a substrate arranged with conductive contacts in a pattern and openings through alternative layers of conductive ...  
WO/2021/002992A1
Methods, systems, and devices for split pillar architectures for memory devices are described. A memory device may include a substrate arranged with conductive contacts in a pattern and openings through alternative layers of conductive a...  
WO/2020/263360A1
A phase change memory cell includes a first electrode, a second electrode located over the first electrode, a vertical pillar structure located between the first and second electrodes, the pillar structure containing a first phase change...  
WO/2020/261736A1
In the present invention, with regard to a selection element that is provided with a plurality of switch layers and that performs selection control in accordance with an applied voltage, the usage-possible period of the selection element...  
WO/2020/256785A1
A memory device includes a plurality of memory cells, and an isolation material portion located between the memory cells. The isolation material portion includes at least one ovonic threshold switch material portion.  
WO/2020/256777A1
A perpendicular spin transfer torque MRAM memory cell includes a magnetic tunnel junction stack comprising a pinned layer having a fixed direction of magnetization, a free layer having a direction of magnetization that can be switched, a...  
WO/2020/249697A1
The invention relates to a method for determining at least one value (tTE_opt, tOX_opt, Xopt) of at least one production parameter (tTE, tOX, x) for a resistive memory cell, the resistive memory cell comprising a thin-film stack, said me...  
WO/2020/251621A1
The switching device includes three terminals including an inner surface, an oxide layer on the inner surface of the third terminal, and a chalcogenide pillar extending through the oxide layer and the third terminal, the pillar being in ...  
WO/2020/251636A1
First elongated loop-shaped conductive material portions are formed over a substrate. A two-dimensional array of memory pillar structures is formed over the first elongated loop-shaped conductive material portions. Second elongated loop-...  
WO/2020/251747A1
Exemplary semiconductor structures for neuromorphic applications may include a first layer overlying a substrate material. The first layer may be or include a first oxide material. The structures may include a second layer disposed adjac...  
WO/2020/249699A1
The invention concerns a method for manufacturing an OxRAM resistive memory cell comprising a layer of silicon oxide, said method comprising the following steps: - determining values of manufacturing parameters enabling the resistive mem...  
WO/2020/251637A1
A phase change memory material and a vertical bit line are formed within each of the memory openings that extend through an alternating stack of insulating layers and sacrificial material layers. The phase change memory material can be f...  
WO/2020/247038A1
A phase change memory device includes a phase change material portion located between a first electrode and a second electrode, and a crystallization template material portion located between the first electrode and the second electrode ...  
WO/2020/240603A1
The present invention refers to a quantum diode for transforming an alternating current, in particular a high frequency alternating current, into a direct current, comprising: a first conductive metal layer (1) behaving as a first electr...  
WO/2020/243417A1
A method of controlling the forming voltage of a dielectric film in a resistive random access memory (ReRAM) device. The method includes depositing a dielectric film contains intrinsic defects on a substrate, forming a plasma-excited tre...  
WO/2020/235591A1
The purpose of the present invention is to provide a novel variable resistance device, the resistance state of which is variable. Consequently, one of typical variable resistance devices according to the present invention is provided w...  
WO/2020/231581A1
Some embodiments include a method of forming an arrangement. A first tier is formed to include CMOS circuitry. A second tier is formed to include an assembly which has first and second sets of memory cells on opposing sides of a coupling...  
WO/2020/231531A1
A semiconductor device includes a first level having a plurality of transistor devices, and a first wiring level positioned over the first level. The first wiring level includes a plurality of conductive lines extending parallel to the f...  
WO/2020/231533A1
A semiconductor device includes a first level having a plurality of transistor devices, and a first wiring level positioned over the first level. The first wiring level includes a plurality of conductive lines extending parallel to the f...  
WO/2020/229752A1
The present description relates to a selector (33) for a memory cell (3), which selector is intended to switch from a resistive state to a conducting state so as to respectively prevent or allow access to the memory cell, characterized i...  
WO/2020/231494A1
First electrically conductive lines, first pillar structures, second electrically conductive lines, second pillar structures, third electrically conductive lines, third pillar structures, fourth electrically conductive lines, and fourth ...  
WO/2020/225521A1
Various implementations described herein are directed to a device having a multi-layered structure formed on a substrate. The multi- layered structure has a switching layer (112), and the switching layer is formed with correlated electro...  
WO/2020/227001A1
Exemplary methods of forming a memory structure may include forming a layer of a transition-metal-and-oxygen-containing material overlying a substrate. The substrate may include a first electrode material. The methods may include anneali...  
WO/2020/226797A1
Architectures of 3D memory arrays, systems, and methods regarding the same are described. An array may include a substrate arranged with conductive contacts in a geometric pattern and openings through alternative layers of conductive and...  
WO/2020/223032A1
A transistor comprises a channel region between a source region and a drain region, a dielectric material adjacent to the channel region, an electrode adjacent to the dielectric material, and an electrolyte between the dielectric materia...  
WO/2020/222992A1
Some embodiments include an arrangement having a memory tier with memory cells on opposing sides of a coupling region. First sense/access lines are under the memory cells, and are electrically connected with the memory cells. A conductiv...  

Matches 1 - 50 out of 6,628