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WO/2013/179089A1 |
A sequential logic circuit comprising a first latch component comprising a data input arranged to receive an input signal, a data output arranged to output a current logical state of the first latch component and a clock input arranged t...
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WO/2012/038882A9 |
A method performed in a memory controller for maintaining segmented counters split into primary and secondary memories, the primary memory faster. Events occur that require incrementing one of the segmented counters and the memory contro...
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WO/2013/155352A1 |
A frequency divider circuit having two stages of transistors has improved performance at low supply voltages. The circuit may include cross-coupled PMOS (112a, 112b) and NMOS transistors (114a, 114b), in which the input signal to be freq...
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WO/2013/128334A1 |
There is provided a method of controlling a CPRI monitor port of a remote radio equipment following a powering cycle. Access to the CPRI monitor port is first detected. An absence timer decrementing process is started when the CPRI monit...
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WO/2013/098127A1 |
A high speed clock frequency divider circuit is provided that uses a first shift register loop-back circuit and a second shift-register loop-back circuit to shift a predetermined array of bits therethrough. The first shift register loop-...
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WO/2013/060134A1 |
The present invention provides a time-resolved single-photon or ultra-weak light multi-dimensional imaging system and method. In one aspect, to achieve coarse time resolution, the present invention provides a time-resolved single-photon ...
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WO/2013/057060A1 |
A programmable high-speed frequency divider architecture is provided to provide a substantially 50% duty cycle signal output regardless of whether the division ratio is odd or even. The programmable frequency divider circuit receives an ...
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WO/2013/048525A1 |
A digital fractional frequency divider for fractionally dividing a digital frequency signal can include a plurality of clock division counter modules, a plurality of sampling modules, and a summing module. The plurality of clock division...
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WO/2012/161003A1 |
A semiconductor device with low power consumption and a small area is provided. By using a transistor including an oxide semiconductor for a channel as a transistor included in a flip-flop circuit, a divider circuit in which the number o...
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WO/2012/112671A2 |
A single stage divider is adapted to operate at very high frequencies. A differential input signal (INP, INM) (for example, with about 120GHz frequency) is divided by divider (100) to provide a differential output signal (OUTP, OUTM) wit...
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WO/2012/042044A2 |
High-speed RF differential, Quadrature, divide-by-2 clock divider designs are based on inverters and clocking circuits connected in a serial ring formation. In one embodiment, only NMOS transistors are used in the inverters, and only PMO...
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WO/2012/041917A2 |
A duty-cycle correction circuit comprises a plurality of AC-coupled, independently-biased inverter stages connected in series. A periodic signal is applied to an input of the plurality of inverter stages. Each inverter stage comprises an...
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WO/2012/025191A1 |
The invention relates to a method for measuring a period of time between a first event and a second event using a hardware counter (2) and a software counter (3). The invention also relates to a digital counter (1) using such a method.
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WO/2011/130052A1 |
In a particular embodiment, a single step increment calculation module is responsive to a first ramp control value and a second ramp control value. The single step increment calculation module generates a single step frequency adjustment...
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WO/2011/103103A1 |
A divide-by-three circuit includes a chain of three dynamic flip-flops and a feedback circuit of combinatorial logic. The divide-by-three circuit receives a clock signal that synchronously clocks each dynamic flip-flop. The feedback circ...
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WO/2011/100032A2 |
Conventional retimers generally consume too much power, are too noisy, and are too large. Additionally, phase noise and jitter are generally a function of retiming. In a described apparatus, a preconditioner 204 has logic 206 mapped to o...
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WO/2011/008999A1 |
A method for dividing the frequency of a signal using a configurable dividing ratio is disclosed. An input signal with a first frequency is received at clocked switches in a frequency divider with a configurable dividing ratio. Non-clock...
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WO/2010/090968A1 |
A method for dividing a frequency includes the steps of receiving a first signal having a first frequency as a clock input to a first digital counter and outputting a second signal as a clock input to a second digital counter having a hi...
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WO/2010/070830A1 |
A clock frequency divider circuit for generating a clock signal that allows an expected correct communication operation to be performed in communication with a circuit that operates on a clock having a different frequency. The clock fre...
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WO/2010/064888A1 |
There is disclosed a frequency divider, comprising: a clock input (CLK) adapted to receive a clock signal; a reset input (RST) adapted to receive a reset signal; a division circuit (30, 40) adapted to divide the clock signal by a factor ...
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WO/2010/042764A1 |
Design techniques for a low-power asynchronous counter. In an exemplary embodiment, the clock inputs and signal outputs of a plurality of flip-flops are serially concatenated to implement an asynchronous counting mechanism. The signal ou...
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WO/2009/151285A2 |
The present invention discloses a low-power frequency divider and a low-power phase-locked loop which keep power consumption to a minimum. The low-power frequency divider generates a frequency-divided signal with frequency equal to the f...
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WO/2009/115865A1 |
A latch module comprising a sense pair of transistor elements (T1 , T2) coupled together for sensing a differential input signal at input terminals (D, Dn), a level-shift module (T5, T6) for producing a differential output signal at outp...
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WO/2009/116398A1 |
A clock signal division circuit includes a mask circuit (10) and a mask control circuit (20). The mask circuit (10) masks a clock pulse of a clock S in accordance with an inputted mask signal (50) so as to generate a clock B for output. ...
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WO/2009/116399A1 |
A clock signal division circuit includes a mask circuit (10B) and a mask control circuit (20B). The mask circuit (10B) masks a clock pulse of a clock S in accordance with an inputted mask signal (50B) so as to generate a clock B. The mas...
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WO/2008/144917A1 |
Systems and methods related to digital frequency locked looping to synchronize frequencies between the local signal from a local oscillator and a reference clock signal from a remote oscillator. A reference counter increments its count f...
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WO/2008/129362A2 |
A device (100) for state retention power gating, the device (100) includes a group of circuits (110 (1) - 110 (4) ) , each circuit is characterized by a reset state, wherein the device (100) is characterized by including: a first memory ...
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WO/2008/092738A2 |
A series (FA) of scanning values (AW) is transformed into a series (FT) of transformation values (TW) by adding one respective transformation value (TW) representing a current scanning value (AW) of the series (FA) of scanning values (AW...
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WO/2008/073744A2 |
Generating an output signal having a frequency of 1 /(M+F) of the frequency of the input signal, wherein M represents an integer and F represents a non-zero fraction. Assuming F equals (Q/R) in one embodiment, wherein Q and R are integer...
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WO/2008/065869A1 |
[PROBLEMS] To provide a rational number frequency dividing circuit wherein the variations in cycle times of frequency-divided clock signals are small, there are many occasions in which the minimum cycle time of frequency-divided clock si...
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WO/2008/056871A1 |
An adaptive equalizer including n filters in parallel with one another to output signals generated from filtered input data; n error generation units, in parallel with one another, to respectively generate errors with respect to the sign...
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WO/2008/056551A1 |
A rational number frequency divider circuit wherein the cycle time of a frequency-divided clock signal is constant and wherein the power consumption, layout area and design/test costs are small. A clock signal frequency divider circuit, ...
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WO/2008/022582A1 |
A general counter for increment type encoder, consists of a Complex Programmable Logic Device (4) and a data storage part, a data input part, a data output part and a pulse signal input part which are connected with the Complex Programma...
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WO/2007/076492A2 |
A memory system that incorporates methods of amplifying the lifetime of a counter made up of memory elements, such as EEPROM cells, having finite endurance. A relatively small memory made up of a number of individually accessible write s...
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WO/2007/057213A1 |
It is the aim of the present invention to improve the properties and the speed of readout electronic significantly without losing accuracy of the counting in photon-counting imaging devices. This aim is achieved according to the present ...
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WO/2007/004182A2 |
A multiphase divider comprises several differential latches connected in a ring. The number of latches in the ring is equal to the number of phases produced and the divisor applied to the input clock. The differential Q-outputs of one la...
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WO/2006/084361A1 |
A transmit diversity single frequency network (SFN) is provided having a distribution network, a head end system, and two or more transmitter circuits. The head end system is configured to provide a signal containing timing information t...
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WO/2006/020033A1 |
In one embodiment, a local oscillator and mixer architecture may include a frequency divider (30) having I and Q channel master storage elements (32, 36) formed of devices of a first size, and I and Q channel slave storage elements (34, ...
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WO/2006/017519A1 |
A synchronous prescaler is provided that has an input line for receiving an input signal, which is synchronized to a low order dual modulus prescaler. The dual modulus prescaler generally divides responsive to a mode command line, but ma...
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WO/2005/114842A1 |
The present invention provides for state correction of a frequencydivider. A first flip-flop is coupled to a second flip flop. A state correction circuit is coupled to the output of the second flip-flop. A third flip-flop is coupled to t...
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WO/2005/114841A1 |
A gateless digital circuit and method for generating a second clock with a frequency of N/M of the frequency of a first clock, wherein N and M are integers, N≤ M/2. The gateless digital circuit having a modulo M function, a register an...
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WO/2005/096501A1 |
Methods, systems and components for use with or as a phase frequency detector. The phase frequency detector stretches its output pulse, allowing the detector to operate in a more linear region. As part of the invention, a new configurati...
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WO/2005/086366A1 |
Conventional multimode radio devices have a frequency dividing section of a large circuit scale because as many frequency dividers as the radio systems are required. A frequency dividing section (22) comprises a frequency divider (19) fo...
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WO/2005/071839A1 |
There is provided an IF counting method for realizing an IF counter having a smaller circuit configuration. The IF counter includes: a down-count type IF counting unit (1) for counting IF signals which have been divided; an IF counting p...
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WO/2005/048002A1 |
A method for operating an electronic counter with reduced power consumption has been developed. The electronic counter is divided into multiple segments that are ordered according to their numerical value. As the counter is updated, it b...
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WO/2005/029720A1 |
A multi-band transceiver (100) for receiving or transmitting signals situated in substantially different frequency ranges comprising first transceiver (1) coupled to an input/output terminal (In/Out) via a first pair of switches (SWI, SW...
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WO/2004/112250A1 |
A statistical counter device (100) consisting of a plurality of statistical counters for counting statistical information. In order to reduce the hardware size and power consumption by dynamically controlling the bit count of the statist...
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WO/2004/109921A1 |
The invention relates to an integrated circuit comprising the following features: a first circuit unit (SE1), which can be switched to an energy saving mode by a control device (SV), whereby said unit (SE1) is switched to a predetermined...
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WO/2004/077676A1 |
The invention relates to a phase-locking circuit (1, 5, 7, 14), wherein a frequency counter (10) is provided in addition to a phase divider (5) which is preferably programmable and which is arranged in the feedback path of the PLL, said ...
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WO/2004/068273A2 |
A digital counter (e.g., Fig. 1) that uses non-volatile memories (12, 14, 16, 18, …) as storage cells, wherein the storage cells are sub-divided into two groups, one for the implementation of a rotary counter (20, 22) that keeps track ...
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