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JP5240850B2 |
To provide a rational frequency dividing circuit wherein the variations in cycle times of frequency divided clock signals are small, there are many occasions in which the minimum cycle time of frequency divided clock signals and test cos...
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JP5235372B2 |
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JP5221441B2 |
A semiconductor integrated circuit includes a mixer circuit unit having a first single gate mixer configured to receive a first input signal having a first frequency and a second input signal having a second frequency as inputs, a second...
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JP5221528B2 |
In a radiation detector (10) for a time of flight positron emission tomography (PET) scanner (2), a radiation sensitive member (20) generates a signal (22) indicative of a radiation detection event. A time to digital converter (34) inclu...
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JP2013115529A |
To switch an output clock without glitch occurrence and clock output stop.First and second frequency-divided clocks obtained by dividing the frequency of a reference clock (Base_CLK) are inputted to a multiplexer MUXO. On the other hand,...
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JP2013115690A |
To provide a clock frequency division circuit (1) with an n-bit counter which outputs frequency-divided outputs at constant timings irrespective of a division ratio.A decoder (4) serves to select a desired division ratio 1/m, and an n-bi...
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JP2013109436A |
To eliminate a period during which all of output clock signals do not change when the plurality of output clock signals having different division ratios are output from an input clock.A clock generation circuit is for emulation of a semi...
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JP5191231B2 |
A wide-range multi-phase clock generator having a first clock generating circuit, a frequency divider circuit, and a plurality of multiplexers. The first clock generating circuit generates a plurality of first clock signals, each having ...
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JP5190767B2 |
An apparatus includes a current source, a current monitor circuit which monitors a current amount of the current source, and outputs a current amount signal corresponding to the current amount being monitored, a counter circuit which cou...
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JP5187618B2 |
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JP5184680B2 |
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JP5180627B2 |
A system includes a memory and a counter circuit associated with the memory and configured to receive a clock signal and a plurality of input bits, and configured to output a plurality of output bits to the memory. The counter circuit in...
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JP5169601B2 |
In a frequency dividing device, a 1/P frequency divider subjects an input clock signal to 1/P frequency division. A phase shifter shifts the phase of the 1/P frequency signal and outputs multiple different Q-phase signals. A switch contr...
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JP5170136B2 |
To provide a data count method that surely detects data corruption when executing counting operation by using a plurality of count addresses, and an image forming device.The data count method is configured to execute the following steps:...
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JP5157461B2 |
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JP2013046268A |
To match frequency division action start timings of a plurality of frequency division circuits under loose constraint conditions.A gate signal generation circuit 14 receives at an input point F a reset signal to be input into reset signa...
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JP5106583B2 |
To reduce power consumption of a TDC circuit with high resolution.The TDC according to the present invention includes: a ring oscillator 10 having a delay line with a plurality of delay elements 11 for delaying an input signal connected ...
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JP5090324B2 |
The circuit (1) has two NAND gates (15, 16) arranged in negative feedback between two dynamic D-type flip flops (12, 13) which are clocked by an input clock signal (CK) to supply a divided output signal (OUT) whose frequency is matched w...
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JP5082952B2 |
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JP5077815B2 |
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JP2012227766A |
To solve the problem in which an addition to or loss in pulses indicating a flow rate owing to noise between a flowmeter and a control device that controls filling leads to an inaccurate determination of flow rate by the control device a...
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JP2012222793A |
To provide a variable frequency division device that is compliant with a fast clock signal.A variable frequency division circuit 101 inputs a clock signal Clk_a, and outputs a signal Do1 that is a frequency division of the clock signal C...
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JP5059828B2 |
A counter for synthesizing clock signals with minimal jitter analyzes an ongoing count to determine whether the rising edge of an output clock should be triggered by the rising edge or falling edge of an input clock signal and to further...
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JP2012199604A |
To provide a counter circuit that precisely counts pulses included in an input signal during a measurement period.The counter circuit includes: a first counter for counting pulses of an input signal during a set measurement period to out...
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JP5035119B2 |
To provide a re-timing circuit and a frequency dividing system capable of preventing malfunction when the timing of a synchronous edge in a clock signal coincides with that of an edge in an input signal. The re-timing circuit including a...
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JP2012169891A |
To provide a counter circuit that performs double precision measurement while using a smaller circuit scale and/or lower power consumption than before.The counter circuit includes: a first circuit for counting pulses in synchronism with ...
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JP5005821B2 |
A frequency divider comprises a cascade of at least two triggered delay elements (FF1, FF2, ...), a reference frequency input (FIN) and a clock output (FOUT). The triggered delay elements (FF1, FF2) are configured to forward a state of a...
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JP2012151617A |
To provide a semiconductor integrated circuit with a self-diagnostic circuit and a method of inspection thereof which, in inspecting a frequency-divided signal, inspect not only the frequency thereof but also a first interval length and ...
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JP4984687B2 |
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JP4945800B2 |
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JP4909507B2 |
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JP2012054828A |
To provide a divider circuit preventing oscillation of a frequency divider.A divider circuit 1 for preventing oscillation of a frequency divider comprises: a frequency divider 20 that divides a clock signal Vc with a predetermined divisi...
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JPWO2010004747A1 |
Inverted data signal using, for example, two clock signals out of eight-phase clock signals so as to provide a frequency divider circuit for the multi-phase clock signal that can secure sufficient data latch time even for a multi-phase c...
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JP4824768B2 |
A time-to-digital converting circuit and a pressure sensing device using the same are provided. The circuit includes: a delay time-varying unit generating a reference signal having a fixed delay time, and a sensing signal having a variab...
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JP4826433B2 |
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JP2011197910A |
To reduce the power consumption of a circuit which periodically corrects a low accuracy clock outputted from a low accuracy clock oscillation circuit by using a high accuracy clock outputted from a high accuracy clock oscillation circuit...
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JP4780144B2 |
Circuits and methods and for dividing a frequency of an input signal by an integer divider value. The circuit generally comprises (a) a first frequency divider, including a first plurality of serially connected delay elements receiving t...
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JP2011188076A |
To provide a frequency counter for counting a frequency more accurately, and to provide a count method for the frequency counter.The frequency counter includes a count time measurement circuit 2 for measuring a fixed period from a basic ...
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JP2011188075A |
To provide a frequency counter for counting a frequency more accurately, and to provide a count method for the frequency counter.The frequency counter includes a count time measurement circuit 2 for measuring a fixed period from a basic ...
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JP2011188026A |
To reduce power consumption by reducing an operation voltage in a clock frequency divider circuit.The clock frequency divider circuit includes: a counter for counting an input clock signal to form a D-ary count value; a counter for count...
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JP4756135B2 |
A frequency divider comprising, a first latch circuit and a second latch circuit, the second latch circuit being crossed-coupled to the first latch circuit. Each latch comprises a respective sense amplifier coupled to a respective latch....
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JP4734510B2 |
A frequency divider includes a first latch and a second latch. The first latch is configured to receive a clock signal. The first latch is cross-coupled to the second latch. The second latch includes a circuit configured as a low-pass fi...
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JP4724794B2 |
A radio FM receiver is provided with a voltage-controlled oscillator which can be connected via a frequency 2-divider to a quadrature combination circuit for transforming down the frequencies of received radio signals and for supplying q...
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JP4717233B2 |
A single-phase clock CLK0 is divided into a clock signal CLK1 to drive nMOS transistor and a clock signal CLK2 to drive pMOS transistor, and the resulting clock signals are inputted to DFF circuits 1 to 3 constituting a frequency dividin...
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JP4686108B2 |
A digital variable clocking circuit is provided. The variable clocking circuit is configured to receive an input clock signal and to generate an output clock signal having an output clock frequency equal to the frequency of the input clo...
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JP4668430B2 |
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JP2011066618A |
To provide an easy-to-handle counter circuit as digital logic circuitry, wherein the mounting area of the circuit is reduced, and also to provide a counting method.The counter circuit alternately connects: a plurality of flip-flop circui...
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JP2011024199A |
To provide a frequency divider capable of reducing current consumption while ensuring a performance as a frequency divider.Frequency divider circuits 10, 30, 50 are connected in series and in order to reduce current consumption of an ent...
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JP2010282399A |
To solve a problem wherein a conventional clock switch circuit can not handle a switching of a high-speed clock signal.A clock switch circuit includes a frequency divide circuit 10 which divides a frequency of a basic clock CLK to genera...
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JP2010273044A |
To provide a frequency-divider circuit capable of balancing improvement of stability of circuit operation with reduction of power consumption, and to provide a semiconductor device.This frequency-divider circuit: includes an FF circuit 1...
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