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JP4416396B2 |
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JP4418614B2 |
A digital compensation filtering technique is provided that enables indirect phase locked loop modulation with a digital modulation data stream having a bandwidth that exceeds, perhaps by an order of magnitude, the bandwidth characterist...
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JP2010501155A |
A frequency synthesizer capable of high speed, low power, wideband operation including a method of gain compensation, and a method of fast voltage controlled oscillator (VCO) band calibration. In addition, the frequency synthesizer may i...
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JP2010011389A |
To achieve a frequency divider, in a simple configuration and with high accuracy, such as a baud rate generator that does not use any dedicated oscillator, wherein an error of a frequency to be divided is allowed.As a frequency divider, ...
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JP4390353B2 |
Clock generating circuitry includes a frequency dividing circuit for dividing the frequency of an input clock by each of a plurality of predetermined frequency dividing ratios which differ from each other to generate a plurality of frequ...
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JP4383876B2 |
A programmable-divider provides a lower-speed transition signal to effect a synchronized load of a new divisor value during a safe-load period of the programmable-divider, such that the division occurs using either the prior divisor valu...
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JP4386725B2 |
An apparatus for generating an output signal whose frequency is lower than the frequency of an input signal is disclosed. The apparatus includes a chain of frequency dividing cells where each cell has a definable division ratio. Furtherm...
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JP2009290641A |
To provide a DDS circuit capable of improving resolution, without increasing the bit length of a tuning word, and to oprovide an electronic appliance.This DDS circuit has a DDS part 11 to output a sign-wave signal from a tuning word, bas...
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JP4371046B2 |
A clock frequency divider circuit including: a storing section for storing an input signal in synchronism with an input clock signal; a supplying section for supplying, as the input signal, one of a first value obtained by adding a value...
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JP4367342B2 |
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JP4362430B2 |
To provide a frequency division circuit of which the operation speed can be increased. A master circuit 10 comprises a differential amplification circuit 10a for taking in an output of the frequency division circuit in response to a cloc...
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JP4357692B2 |
A non-integer frequency divider that is capable of dividing an original clock frequency by a non-integer number into a desired target clock frequency. By this non-integer frequency divider, a phase-shifting circuit is first used to conve...
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JP2009246969A |
To provide a frequency diverse discrete-time phase-lock device.The frequency diverse discrete-time phase-lock device is provided with an analog section which includes a digital-to-analog converter (DAC) and an oscillator which operates t...
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JP2009232072A |
To provide a PLL circuit capable of quickly making an unlocked state of a frequency of an oscillation signal, while providing the PLL circuit with a plurality of VCOs which have mutually different oscillation frequency bands.The PLL circ...
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JP2009212736A |
To prevent deterioration in imprint characteristics of a ferroelectric capacitor in a semiconductor integrated circuit in which data signals of a latch circuit are held in the ferroelectric capacitor.The semiconductor integrated circuit ...
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JP2009194560A |
To provide a frequency dividing circuit having reduced power consumption.The frequency dividing circuit uses a ring oscillator that connects outputs of a logic inverting circuit in a ring shape, and the logic inverting circuit is operate...
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JP2009188748A |
To provide an inverter circuit comprising transistors of the same conductivity type.The inverter circuit includes a NOT logic constitution portion and an output circuit portion and the output circuit portion includes two transistors of t...
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JP2009188749A |
To provide an inverter circuit configured such that narrowing of a width of a maximum amplitude of output is reducible.One source/drain region of a first transistor is connected to one source/drain region of a second transistor, the othe...
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JP4309392B2 |
In a delay locked loop and a semiconductor memory device having the same, the delay locked loop includes a phase detecting and control signal generator for detecting a phase difference between a clock signal and a feedback clock signal a...
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JP4305317B2 |
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JP4304124B2 |
In a circuit in which a signal arrival time with respect to a register is different in accordance with the change of a delay time of the circuit, a mechanism capable of adjusting a clock signal of the register is previously provided to d...
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JP2009164929A |
To provide a signal generating circuit for generating wide-bandwidth signals while reducing power consumption.The signal generating circuit 1 includes a reference signal source 51 for outputting a reference signal (a), a phase comparator...
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JP4299850B2 |
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JP4298685B2 |
The present invention provides a solid state image sensor and a camera using such a solid state image sensor, in which all of stage registers of the shift register can be reset efficiently without increasing the number of pads and/or sen...
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JP4292425B2 |
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JP4289206B2 |
An asynchronous counter that is capable of switching count mode includes flip-flops, and three-input single-output tri-value switches respectively provided between the adjacent pairs of the flip-flops. The tri-value switches switch among...
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JP2009130760A |
To improve flexibility in setting of decimal frequency division, regarding a frequency divider circuit.The circuit includes a clock input terminal; first and second flip-flop circuits to each of which a clock from the clock input termina...
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JP4275844B2 |
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JP2009124532A |
To solve the following problem: when a clock signal becomes a high frequency, a setup time cannot be secured among the clock signal CLK, a chip select signal CS that is a control signal, a read/write signal nRW and a byte write signal EN...
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JP4251640B2 |
The present invention generates an output clock signal CLKreq having a frequency freq between the frequency fref/A of a divided clock signal CKL1 and the frequency fref/(A+1) of a divided clock signal CLK2. A clock divider circuit select...
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JP4240657B2 |
A hold/reset mode selection counter includes a counter unit composed of a plurality of counter blocks to perform a counting operation, a mode selection unit that detects a count enable signal length, and a control unit that enables or di...
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JP4230665B2 |
A multi-divide frequency divider, includes a chain of serially-connected frequency divider units, each responding to a first state of received control signals by using the reference clock signal to generate an output signal having a freq...
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JP2009033503A |
To obtain a frequency divider by which a plurality of output waves are easily and efficiently acquired.The frequency divider is provided with: a frequency division circuit 1 of which the number of frequency division is N (N: an integer 2...
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JP2009017153A |
To reduce the time to transfer a count value between circuits which have clock signals with different frequency.In count signals CNT to CNT3 of a gray code counter 11 which is operated by a transmitting side clock signal CLKA, a changed ...
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JP2009502103A |
There is provided a true single phase logic clock divider that is configured to selectively divide a clock signal by increments of two, three, four, or six. Because the true single phase logic clock divider is based on true single phase ...
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JP4199664B2 |
The double divider mode counter has two divide by two circuits (10,12) with a phase selector block (11) between them and commands (13) provided by the command unit. The command unit provides command signals (S0,S1,S2) to the selector blo...
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JP4197532B2 |
A master latch (1) is formed from a static circuit, and a slave latch (2) is formed from a dynamic circuit. The number of circuit elemen
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JP2008301017A |
To provide a digital pulse width modulation apparatus capable of improving the resolution of pulse width modulation without using a clock of a high frequency.The pulse width modulation apparatus using two clocks, i.e. a clock A (100) hav...
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JP2008545321A |
A multiphase divider comprises several differential latches connected in a ring. The number of latches in the ring is equal to the number of phases produced and the divisor applied to the input clock. The differential Q-outputs of one la...
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JP2008545320A |
A multi-bit, programmable, modular digital frequency divider divides an input frequency by an m-bit integer divisor to produce an output frequency. The integer divisor re-initializes m-number of flip-flop stages with the divisor input at...
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JP2008301325A |
To prevent timing of output signals from being deviated in a synchronous type counter circuit by taking layout into account.A counter circuit outputs count values Q0-Q15 of MN bits using M (e.g., four) pieces of N-bit (e.g., 4-bit) synch...
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JP2008545322A |
A multi-phase frequency divider comprises dynamic inverters connected in a ring and the intermediate nodes around the ring are stabilized with cross-coupled latches. Clock input pulses enable each dynamic inverter's output and will force...
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JP2008271593A |
To provide a prescaler which shortens an operation delay time of an extender unit and is capable of sufficiently ensuring a marginal time, with respect to a malfunction, of a frequency dividing ratio switching operation.A prescaler 21b i...
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JP4150092B2 |
A frequency divider circuit, and a digital PLL circuit including the same, which can suppress jitter occurring in an output signal, including a first circuit module which drives D-FFs connected in series using an input signal as a refere...
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JP4149634B2 |
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JP2008206038A |
To provide a frequency divider circuit which has a wide operation frequency range, and is small in size and low in power consumption without using any special switching circuit or control circuit.In the frequency divider circuit includin...
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JP2008196917A |
To provide an asynchronous type counter circuit performing verification to a supply pass of a clock signal without complicating a circuit, and improving a failure detection rate.This circuit is equipped with: a plurality of flip-flop cir...
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JP2008193235A |
To provide a phase-compensated clock divider circuit controlling the frequency-divided clock to be always synchronized with a synchronizing signal, and preventing malfunction or delay in operation.The phase-compensated clock divider circ...
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JP2008172649A |
To share a counter among a plurality of dividers with different division ratios and phases, and to reduce a logical amount and the power consumption of the whole divider circuit by making the division ratio and the phase of the divider i...
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JP2008172512A |
To provide a frequency synthesizer capable of realizing frequency division of high precision while suppressing circuit increase, without using a PLL of a conventional configuration, and to provide a clock generation method.The frequency ...
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