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WO/2001/011784A1 |
The invention relates to a frequency synthesiser which functions on the principle of fractional frequency synthesis. It consists of an integral frequency divider which can be regulated, and a control device in which a desired broken frac...
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WO/2001/010028A1 |
The present invention, generally spreading, achieves noise spreading within a PLL using a dual-modulus prescaler by interleaving the division moduli. Within a given cycle, 'ones' and 'tens' are not all counted consecutively. Instead, one...
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WO2000025426A9 |
A loadable counter circuit which is able to perform multiple contiguous counts. The loadable counter circuit uses a counter (12) for monitoring a number of specified events. A data storage device (14) is coupled to the counter (12) for l...
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WO2000019611A9 |
A prescaler circuit for a frequency synthesizer includes two circuit blocks, each having an OR gate coupled with a master-slave flip-flop. An input clock signal having a frequency FN is supplied to the flip-flop of each circuit block, an...
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WO/2000/030259A1 |
A digital delay generator device is based on a series arrangement of cells, wherein each cell has a first input for receiving a single-phase clock signal, a second input for receiving a delayable signal for thereto imparting a cell delay...
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WO/2000/008790A1 |
Either a set of frequency divisor data representing at least one frequency divisor which is an integer larger than the ratio (fa/fb) of the frequency (fa) of an input clock to a target frequency (fb) of the output clock or a set of frequ...
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WO/2000/008761A1 |
A rational frequency divider for producing an integer frequency from a rational frequency, consisting of a memory for storing first and second divider constants; a selector device for selecting the stored divider constants; a first count...
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WO/2000/001071A1 |
The invention relates to a static frequency divider with a modifiable divider ratio for maximum frequencies and with a minimal overall power consumption. In a first divider stage, a T-flip-flop is provided with modified D-flip-flops whic...
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WO/1999/060702A1 |
A low power counter for cycling through a predetermined sequence of states in response to pulses on an input line ($i(en)), including a number of counter blocks, corresponding to the number of bits of the counter, connected in series. Th...
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WO/1999/050793A1 |
A counting device, comprising: an input (105, 107) for receiving an input signal having at least three distinct input states; memory means (810) for storing a count; and means (620) responsive to a predetermined sequence of input states ...
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WO/1999/031805A1 |
A multi-divide frequency divider, includes a chain of serially-connected frequency divider units, each responding to a first state of received control signals by using the reference clock signal to generate an output signal having a freq...
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WO/1999/027651A1 |
A circuit is disclosed for sampling analog signals at a rate which is a rational, non-integer fraction of a clock frequency. The analog signal is sampled at non-equidistant sampling points, with the distances between successive points fo...
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WO/1999/022449A1 |
A fractional frequency synthesizer (100) includes a symmetrical divider (165) having an output frequency signal (135) fractionalized based on half cycles of its input frequency signal (130). The divider (165) is provided with a divisor (...
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WO/1999/018668A2 |
A frequency divider circuit is provided having an even number of amplifier stages connected in series with the output of the last amplifier stage connected to the input of the first amplifier stage; and modulating means responsive to an ...
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WO/1999/018669A1 |
The invention concerns the field of variable modulo frequency dividers. In order to obtain a quick variable modulo on a wide operating range the invention proposes the use of twin flip-flops (1, 2; 3, 4; 5, 6; 7, 8) for feedback's. The a...
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WO/1999/003207A1 |
The invention relates to a digital phase locked loop for synchronizing an output clock signal with a reference clock signal, comprising a numerically controlled oscillator (2), which can be programmed, specially in relation to a desired ...
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WO/1998/039845A2 |
A counter circuit includes a series of registers driven by two phase shifted clocks. A clock generator in the counter circuit generates four asymmetrical clock signals to drive each of the registers. The registers are formed from input a...
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WO/1998/020407A1 |
In a semiconductor integrated circuit provided with a clock generating circuit using a PLL circuit and a serial communication circuit, a clock having a frequency which is a power of 2 is inputted into the clock generating circuit as a re...
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WO/1998/015061A1 |
The subject-matter of the application relates to a device in which a high-frequency clock signal (CLK8) can be converted to a low-frequency clock signal (CLK5) whereby a strobe signal (STI) is shifted through a shift register (Reg 1....R...
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WO/1998/009379A1 |
A frequency-dividing circuit comprises a digital accumulator capable of performing signed arithmetic and means for adding of a predetermined numerator to the content of the accumulator. Means are provided for subtracting a predetermined ...
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WO/1997/049186A1 |
The invention relates to fast serial-parallel and parallel-serial converters, and in them included frequency dividers. The serial-parallel converter comprises a shift register (51), an output register (52) and a frequency divider (40). T...
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WO/1997/014210A1 |
Self-oscillation of a prescalar circuit is avoided by including offset generators on the inputs of the prescalar circuit. This ensures that when the transistors in one differential pair in the prescalar circuit transition from ON to OFF,...
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WO/1996/037962A1 |
An analog comparator compares an analog signal to be converted with an analog ramp signal. The output of the comparator enables a digital latch having a binary Gray code counter input. When the analog ramp equals the analog signal, the d...
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WO/1996/030821A1 |
In a clock generator for supplying clocks to a unit (31) operating by a high speed clock CLK0 or a low speed clock CLK1 and to a unit (32) operating by CLK0 or CLK1, a variable clock generator of this invention includes a switch signal c...
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WO/1996/021278A1 |
A counter system has a first counter (1) seeded by several input signals and a second counter (2) seeded by at least a first output from the first counter. A selection signal is input to the second counter to select the use of either an ...
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WO/1996/015484A2 |
A monolithic integrated circuit for providing enhanced audio performance in personal computers is disclosed. The monolithic circuit includes a wavetable synthesizer; a full function stereo coding and decoding circuit (CODEC) including an...
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WO/1995/021078A1 |
The proposal is for a device for operating a windscreen wiper in intermittent and continuous modes. To this end, there is at least one sensor (12) emitting signals depending on the degree of wetting or quantity of rain on a windscreen to...
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WO/1995/020269A1 |
A phase-locked-loop frequency synthesizer with adjustable frequency has a signal source of predetermined reference frequency of 10, 100 or 1,000 Hz, and a comparator with a first input receiving the reference frequency signal, a second i...
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WO/1993/013601A1 |
A high resolution digitally controlled oscillator is in the form of a digital frequency divider (10), which uses calculation logic (14) to utilize both the rising edge and the falling edge (start edge and stop edge) of the input clock pu...
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WO/1992/011589A1 |
A pulse frequency divider for two opposed pulse trains comprises an up/down counter and a comparator which tracks the net counts of the combined (and oppositely sensed) pulse trains. Means are provided for separating the counting loop po...
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WO/1991/018449A1 |
A scaler comprising a plurality of flip-flops (31-34), varies its frequency division to correct phase by 0.5 clock cycle. Each flip-flop (31-34) is continuously and synchronously responsive to either a rising (31, 33) or a falling (32, 3...
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WO/1991/011726A1 |
A binary counter (60) provides for resolution doubling by producing a wavetrain (Q0) which represents the zero-order bit of the counter and has the same frequency as the clock input (REFCLOCK).
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WO/1991/011860A1 |
A frequency divider (10) receives a first frequency signal (CKT) and at least one clock signal (CKI) of a sub-multiple of the first frequency. The first frequency signal (CKT) charges a storage terminal (42) once each first frequency cyc...
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WO/1991/002410A1 |
An apparatus is described for the dual modulus prescaling of a high frequency signal. The apparatus comprises a dual modulus divider (4), second divider (5), synchronization circuit (6) for providing a first modulus control signal (7) to...
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WO/1990/008428A1 |
A high speed CMOS divide by 4/5 prescaler circuit comprises first, second, third, fourth, and fifth inverter stages (outputs at 10, 12, 14, 16, 18). When a modulas control signal (MC) is low, the prescaler operates as five clocked invert...
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WO/1990/007232A1 |
A programmable counter or frequency divider includes the combination of a fixed modulus prescaler (110) and a programmable divider (120, 130, 140, 150, 160) in which the prescaler provides more than a single clock phase to the programmab...
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WO/1990/005413A1 |
A high speed digital programmable frequency divider (10') capable of frequency division by even and odd integers is disclosed herein. The frequency divider (10') of the present invention includes a waveform generator (20') for providing ...
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WO/1990/001832A1 |
An N stage Gray code counter includes an N stage binary counter (11-14) having an input for receiving clock pulses to be counted and providing N outputs (B0-B3) forming an N bit binary code. N minus 1 storage stages (21-23) capable of be...
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WO/1989/010028A1 |
In a logic network consisting of a number of cascode connected modules (TF) for processing digital signals, carry signals which propagate as a ripple signal from one module to another often represent a serious limitation as regards the m...
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WO/1989/005546A1 |
A D-type, master-slave, flip-flop is described for use as a divide-by-two frequency divider in which a frequency to be divided is input as a clock signal and the Q output is connected to the D(Boolean not) input, and in which the master ...
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WO/1988/000775A1 |
An electronic counter such as for use in the odometer of a motor vehicle is provided comprising an array (10) of m rows and n columns of single flip-flop data latches and a central shifting unit (CSU) (14). The CSU (14) comprises a row o...
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WO/1987/005453A1 |
A counting circuit which counts the number of pulses asynchronously input during a predetermined period of time includes a counter (C') which counts the number of input pulses, a register (D) which stores the pulses emitted from the coun...
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WO/1987/000365A1 |
A frequency dividing arrangement (5) comprises a frequency divider (6) coupled to an active filter (7) which is operative to suppress output radiation from the frequency dividing arrangement. The arrangement (5) may be incorporated into ...
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WO/1986/003633A1 |
A method and apparatus for dividing a clock pulse frequency Cl in a ratio A/B, where the quotient between B and A is the whole number C and the remainder D. A pulse train is generated, which includes (A-D) half pulses with a pulse length...
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WO/1986/003078A1 |
A logic circuit for use in a variable frequency divider (8) includes a driver (T1, T2), a latch (T3, T4), and an enabling switch (T5, T6) each comprising a pair of emitter coupled transistors. The driver (T1, T2) is coupled to the latch ...
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WO/1986/002793A1 |
A frequency divider (50) for converting an n-bit periodic counting stream (each period containing a single zero or one bit, respectively, followed by n-1 one or zero bits) into a 2n-bit counting stream includes a two-input NOR gate (51) ...
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WO/1986/002216A1 |
A counter apparatus which counts the number of pulse signals and outputs on ON/OFF state previously stored at an address corresponding to the count thereof. When a signal corresponding to a set mode is output from a mode changeover devic...
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WO/1986/000985A1 |
An electronic odometer (10) which is field presettable within limits after it is installed in a vehicle. A microprocessor (14) is utilized to store a total accumulated mileage (odometer) signal in a non-volatile random access memory (RAM...
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WO/1985/004297A1 |
A counting apparatus wherein an output indication is provided in response to a predetermined number, N, of input voltage or current transitions. The apparatus is constructed with a plurality of subcounters each one of which responds to t...
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WO/1985/003176A1 |
An improved multiple frequency digital phase-locked loop circuit (10). The improved digital phase-locked loops utilizes a single circuit (12) to effect both phase and frequency adjustments. The multiple frequency digital phase-locked loo...
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