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WO/2016/202896A1 |
The method is used for transmitting signals and data during at least one first and one second transmission phase (TP1, TP2), which follow one another synchronously or asynchronously, between a first communication unit (L) and at least on...
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WO/2016/203491A2 |
The present disclosure envisages an asynchronous clock gating circuitry and a method for designing the asynchronous clock gating circuitry. The asynchronous clock gating circuitry could be placed at the very beginning of the clock networ...
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WO/2016/204962A1 |
Phase compensation in an I/O (input/output) circuit includes variable, programmable slope. A phase compensation circuit can apply phase compensation of one slope and dynamically change the slope of the phase compensation to allow for bet...
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WO/2016/203235A2 |
A voltage monitor circuit comprises: a monitored voltage input (42); a reference capacitor (32) arranged to be able to store a value of the monitored voltage as a reference capacitor voltage; a timeout capacitor (34) arranged to be able ...
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WO/2016/198302A1 |
The invention relates to a compensator device for compensating signal dependent delay variations, including dead time and reverse recovery time, causing un-linearity in a Class-D amplifier where the compensator device comprises: a first ...
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WO/2016/199522A1 |
A signal transmission circuit is provided with: first and second lines L1, L2 to which signals complementary to each other are inputted; first and second buffer circuits BA11, BA21; a first inverter BA12 which connects a first input-side...
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WO/2016/196848A1 |
A programmable delay line comprises a delay stage responsive to an analog control signal and responsive to one or more digital control signals. The delay stage generates an output signal that is delayed relative to an input signal by a d...
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WO/2016/190956A1 |
A pulse generator includes a latch module for storing first/second states, a pulse clock module for generating a clock pulse, and a delay module for delaying the clock pulse at a second latch-module input. The latch module has a first la...
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WO/2016/188311A1 |
An electronic driver circuit for use with a modulator such as a segmented Mach-Zehnder Modulator (MZM) is provided. The electronic driver circuit includes a first delay buffer implemented as a first complementary metal-oxide-semiconducto...
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WO/2016/186756A1 |
A glitch-free digitally controlled oscillator (DCO) code update may be achieved by synchronizing the transfer of the DCO code update to a logic state transition of a pulse in the DCO clock output signal such that the code update may be a...
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WO/2016/186930A1 |
In one example, a driver circuit includes a differential transistor pair (504) configured to be biased by a current source (502) and including a differential input (516) and a differential output (512). The driver circuit further include...
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WO/2016/176534A1 |
A comparator system (100) may include a comparator circuit (102) and input circuitry (104) coupled to a communication line (120, 122). The circuitry may include resistors (RA, RB) that are used to generate input voltages supplied to inpu...
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WO/2016/174384A1 |
A transition detection circuit (20) and method of operation of such a circuit are provided, the transition detection circuit (20) having pulse generation circuitry (25) to receive an input signal (10) and to generate a pulse signal in re...
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WO/2016/169377A1 |
A PWM control voltage compensation method comprises the following steps: S1, generating, by a microcontroller I/O port P01, a corresponding PWM according to a target voltage Vt, generating an initial voltage by the PWM, and loading the i...
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WO/2016/169652A1 |
The invention relates to a method for synchronising at least one slave control circuit, controlled by a slave control signal (2S) having pulse width modulation, with a master control circuit, controlled by a master control signal (2M) ha...
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WO/2016/167973A1 |
A method and an apparatus are provided. The apparatus may includes a clock recovery circuit having a plurality of input latches configured to assume a first state when a first pulse is received in one or more of a plurality of input sign...
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WO/2016/167903A1 |
Automatic voltage switching circuits for providing a higher voltage of multiple supply voltages are disclosed. In one aspect, an automatic voltage switching circuit (100) is configured to generate a compare signal (116) indicating which ...
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WO/2016/163228A1 |
This technology relates to a solid-state image capturing device, an electronic instrument, and an AD converting device which make it possible to suppress the occurrence of errors in AD conversion results. The solid-state image capturing ...
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WO/2016/161504A1 |
Master clock redundancy is provided for a digital phase locked loop having a digital controlled oscillator (DCO) driven by a master clock source, for example, a crystal oscillator. One of a plurality of a crystal oscillators generating c...
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WO/2016/158691A1 |
This electronic circuit is provided with: a bistable circuit which is connected between a positive power source to which a power source voltage is supplied, and a negative power source, and in which a first inverter and a second inverter...
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WO/2016/154761A1 |
A universal input buffer has a pair of input pins. A first input of a multiplexer is coupled to the second input pin and a second input of the multiplexer receives a common mode voltage of a differential signal applied to the first pin. ...
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WO/2016/150586A1 |
The present invention relates to a method for regulating a dead time in a synchronous converter (100), in which method a control switch (2) and a synchronous switch (3) are cyclically switched, wherein the control switch (2) is switched ...
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WO/2016/144735A2 |
A three input voltage comparator provides termination of a pulse width modulation (PWM) output in a switched mode power supply. Shutdown of the PWM signal occurs when a sense current from the switching transistors exceeds either or both ...
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WO/2016/138706A1 |
Disclosed is a clock switching method. The clock switching method comprises the following steps: receiving a selection instruction, and acquiring a selection signal value; if the selection signal value is a first preset value, then gatin...
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WO/2016/137605A1 |
Systems and methods for powering up circuits are described herein. In one embodiment, a method for power up comprises comparing a voltage of a first supply rail (INT) with a voltage of a second supply rail (EXT), and determining whether ...
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WO/2016/134841A2 |
The invention relates to a method for processing a main signal produced by a sensor for detecting the rotation of a rotating target having voltage levels. The main signal includes pulses having, for a rotation speed of the given target, ...
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WO/2016/136448A1 |
The present disclosure relates to a comparator, an AD converter, a solid-state imaging apparatus, an electronic device, a comparator control method, a data writing circuit, a data reading circuit, and a data transferring circuit that all...
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WO/2016/137600A1 |
A duty cycle adjustment apparatus (200) includes a duty cycle adjustment determination module (204) configured to determine an adjustment to a duty cycle of a clock signal (203), and includes a clock delay module (232, 240) configured to...
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WO/2016/128164A1 |
The invention relates to a method for operating a pulse generator (1) for generating measuring pulses for a capacitive sensor having an adjustable pulse time in the range from 10 ns to 200 ns, having a controllable delay circuit (2) whic...
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WO/2016/128225A1 |
The invention relates to a circuit assembly for protecting a unit to be operated from a supply network against overvoltage, comprising an input having a first and a second input connection, which are connected to the supply network, an o...
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WO/2016/124334A1 |
The invention relates to an electronic circuit for controlling a half H bridge, said half split H bridge including first (7) and second (8) MOSFET transistors of different respective types, with sources connected respectively to a supply...
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WO/2016/122801A1 |
Clock skew compensation with adaptive body biasing in three-dimensional (3D) integrated circuits (ICs) (3DICs) is disclosed. In one aspect, a sensor is placed on each tier of a 3DIC to evaluate a speed characteristic of each tier relativ...
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WO/2016/123284A1 |
In a method (400) of providing clock data recovery (CDR) in a receiver, the method includes: receiving a Phase Amplitude Modulation (PAM) signal (402); on startup, using a non-return-to-zero (NRZ)-based phase frequency detector (PFD) (40...
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WO/2016/117410A1 |
A signal transmission device, wherein transformers 22a, 22b and a reception circuit 24 are formed in one and the sample chip, and an electrostatic discharge (ESD) protection element connected to the transformer connection terminal of the...
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WO/2016/109815A1 |
In described examples of a method of frequency estimation, a clock output from a frequency synthesizer (110) is received at an input of a ring encoder (121). The ring encoder (121) generates outputs, including a ring encoder output clock...
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WO/2016/108989A1 |
A transition tracking circuit (106) may be configured to receive a first input signal (VA) and a second input signal (VAB) from a level shifter (102). The transition tracking circuit (106) may be configured to track earlier falling trans...
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WO/2016/104464A1 |
[Problem] To shrink circuit scale and to reduce power consumption. [Solution] A phase digital converter is provided with a counter for counting the number of cycles of a first signal, a first phase difference detector for generating a ph...
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WO/2016/103929A1 |
The purpose of the present invention is to improve maintenance operations by changing the output time of a warning alarm in response to an overheated state. A semiconductor device (1-1) is provided with a semiconductor switch (1a) and a ...
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WO/2016/103845A1 |
In the present invention, a signal detector is equipped with an input signal amplifying circuit, a reference signal amplifying circuit, and a comparator in order to accurately detect the presence of a signal. The input signal amplifying ...
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WO/2016/097709A1 |
A differential comparator has a first input and a second input (22, 24) and comprises: • first and second transistors (10, 12) arranged as a differential pair connected to the first and second inputs (22, 24) respectively; and • a co...
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WO/2016/097699A1 |
A relaxation oscillator (2) comprises: a comparator (4) comprising: a differential pair of transistors (140, 142, 144. 40, 42, 44); a static current source (32); and a dynamic current source (32); and at least one energy storage componen...
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WO/2016/094196A1 |
A method, an apparatus, and a computer program product are provided. The apparatus outputs a sinusoidal signal according to a first clock frequency, generates, a first digital signal having a 25% duty cycle based on the sinusoidal signal...
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WO/2016/091100A1 |
Apparatus and methods are taught for quickly determining whether a Loss of Signal (LOS) condition has occurred for a receiver which includes an internal reference clock, a LOS circuit and a Clock and Data Recovery (CDR) circuit. The CDR ...
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WO/2016/091886A1 |
The invention proposes a method for distributing a signal over each block Bj of a series of N adjacent blocks of identical design of an electronic circuit. It proposes, in an identical manner for each of the N blocks, placing a time dela...
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WO/2016/085600A1 |
A method and an apparatus are provided. The apparatus may includes a clock recovery circuit having a comparator that provides a comparison signal indicating whether an input signal matches a level-latched instance of the input signal, a ...
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WO/2016/076139A1 |
The present technology pertains to a signal-processing device configured so that it is possible to suppress an increase in power consumption, a control method, an image-capture element, and an electronic device. This signal processing de...
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WO/2016/076419A1 |
This phase measuring device is provided with: a first AD converter 2 for digitizing a first periodic input signal X at each predetermined sampling timing, and outputting the digitized signal as a digital signal Xd; a first zero crossing ...
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WO/2016/071813A2 |
A digitally controlled oscillator architecture is natively digital and therefore not dependent upon any particular technology process for the manufacture thereof, and basically it comprises: a chain of delay elements having each at least...
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WO/2016/072600A1 |
A delay line-based time-to-digital converter according to an embodiment of the present invention comprises: a coarse counter for counting pulses of a timing clock so as to measure the time when an edge of an input signal is detected; a f...
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WO/2016/073078A1 |
An organic light-emitting diode display may have an array of pixel circuits. Each pixel circuit may contain an organic light-emitting diode that emits light, a drive transistor that controls current flow through the diode, and additional...
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