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WO/2020/032915A1 |
Networks, methods, and circuitries are provided that propagate an actuator signal to a plurality of devices in a respective plurality of voltage domains (VD1-VD4). An exemplary network (310) includes a first signal path between an actuat...
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WO/2020/025941A1 |
This application relates to time-encoding modulators (TEMs). A TEM (100) receives an input signal(SIN) and outputs a time encoded signal (SPWM). A comparator (101) is located within a forward signal path of a feedback loop of the TEM. Al...
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WO/2020/024149A1 |
Methods and apparatus for generating a delayed output signal from an input signal applied to an RC delay circuit of a semiconductor device during an active mode. The RC delay circuit is configured to pull up a voltage level on a node res...
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WO/2020/023974A1 |
Some embodiments include a high voltage pulsing power supply. A high voltage pulsing power supply may include: a high voltage pulser having an output that provides pulses with an amplitude greater than about 1 kV, a pulse width greater t...
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WO/2020/022388A1 |
[Problem] To achieve a configuration that does not include a diode susceptible to temperature. [Solution] The present invention is provided with: a capacitor 42c wherein one end section thereof has a difference signal Vd0 input thereto a...
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WO/2020/021392A1 |
An encoder for modulating data on level transitions of a signal transmitted on a wired communication channel to increase channel data throughput, comprising a circuitry configured for receiving a signal transmitted by a transmitting comm...
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WO/2020/023965A1 |
A high voltage power system is disclosed. In some embodiments, the high voltage power system includes a high voltage pulsing power supply; a transformer electrically coupled with the high voltage pulsing power supply; an output electrica...
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WO/2020/022387A1 |
[Problem] To generate a code identifying signal that can identify a code corresponding to a logic signal transmitted to a communication channel without being connected to the communication channel via a connector. [Solution] The present ...
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WO/2020/013916A1 |
A desirable feature of a SERDES design is power savings. One way to achieve power savings is by keeping the CDR circuit OFF during most of the time when a link is active between a transmitter and a receiver. However, due to voltage suppl...
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WO/2020/012943A1 |
The present technology relates to a comparator and an imaging device which make it possible to easily change an operation point potential of the comparator. A pixel signal output from a pixel and a reference signal the voltage of which c...
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WO/2020/013226A1 |
A signal processing circuit (13) having: a plurality of first circuits (41-1) each having a first interval signal output circuit (51) for outputting a first interval signal representing a time interval between a first timing at which a f...
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WO/2020/014444A1 |
A millimeter wave (MMW) circuitry includes a phase modulation circuitry, a plurality of amplifier multiplier chain circuitries and a power combiner circuitry. The phase modulation circuitry is configured to receive input data and a plura...
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WO/2020/013101A1 |
A signal processing circuit (12) outputs a first output signal at a first timing, at which a first input signal changes, and outputs a second output signal at a second timing, at which a second input signal changes, when the first timing...
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WO/2020/005438A1 |
Techniques and mechanisms for determining a delay to be applied to a clock signal for synchronizing data communication. In an embodiment, a delay is applied to a first clock signal to generate a second clock signal, which is then communi...
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WO/2020/003980A1 |
Provided is a solid-state imaging device with which it is possible to improve the dynamic range of an ADC and thereby improve imaging characteristics. Provided is a solid-state imaging element (11) comprising a pixel array (12) having a ...
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WO/2019/237366A1 |
Disclosed in the present invention is a reference clock duty ratio calibration circuit, comprising a low-noise low-dropout regulator, an oscillation circuit, a duty ratio adjustment circuit and a duty ratio calibration circuit. The duty ...
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WO/2019/238144A1 |
Disclosed are a data signal detection apparatus, and a mobile industry processor interface radio frequency front-end slave device and system, the apparatus comprising: a first acquisition circuit, a second acquisition circuit and an outp...
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WO/2019/239984A1 |
This semiconductor device comprises: first through N-th PLL circuits which operate in synchronization with a common reference clock signal and which respectively output first through N-th clock signals; a majority circuit that carries ou...
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WO/2019/237114A1 |
Technologies are provided for generation of programmable pulse signals using inverse chaotic maps, without reliance on a clocking signal. Some embodiments of the technologies include an apparatus that can receive a sequence of bits havin...
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WO/2019/234412A2 |
The present invention relates to a handheld device for detecting a partial discharge event, the device comprising: a first probe having a first partial discharge sensor disposed within; and a second probe having a second partial discharg...
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WO/2019/234037A1 |
The invention relates to a comparator circuit (1), which has an input stage for a first voltage and for a second voltage and which is designed for comparing the first voltage and the second voltage, and which is designed to generate a di...
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WO/2019/234484A1 |
A system and method for generating a waveform having a burst modulated ultrasound sweep carrier wave with encapsulated sonic artefacts is disclosed. The system includes a transducer; and a microcontroller operatively connected to the tra...
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WO/2019/231338A1 |
Disclosed is a method for modelling a distorted energy spectrum in a multi-energy x-ray CT imaging system using probability distribution functions, the method including taking open beam measurements across a range of fluxes, estimating t...
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WO/2019/231489A1 |
Apparatuses and methods for setting a duty cycler adjuster for improving clock duty- cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smalle...
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WO/2019/231574A1 |
A system is disclosed. The system includes a first stage (M12, M14) configured to receive an input voltage (VIN) and a reference voltage (VREF), the first stage including an input transistor pair (M12, M14), wherein the input voltage is ...
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WO/2019/226698A1 |
An RF frontend IC device includes an RF transceiver to transmit and receive RF signals and a frequency synthesizer to perform frequency synthetization to operate within a predetermined frequency band. The frequency synthesizer generates ...
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WO/2019/226256A1 |
In certain aspects of the disclosure, an apparatus (100) comprises a latching element (110) having a data input (118b), a first feedback input (118a), a second feedback input (118c), and an output (140). A pull-up input block (122) is co...
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WO/2019/222373A1 |
System and method of adapting thresholds for constellation selection based on statistic distributions of received data symbols. An expected ratio of received symbols with values in a certain range is preset based on an expected statistic...
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WO/2019/216587A1 |
The present invention relates to a freshness preserving apparatus which discharges a low frequency wave in order to generate a low frequency electric field, the apparatus comprising a high voltage low frequency circuit (500) which compri...
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WO/2019/212343A1 |
The invention relates to an asynchronous comparator that presents low average power consumption and short propagation delay. The comparator bias current is dependent on the differential input voltage in a way that the current increases w...
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WO/2019/212785A1 |
An apparatus is disclosed that includes a voltage-controlled delay generator (136-1). The apparatus includes voltage-controlled timing circuitry (402), duty cycle detection circuitry (404), and output circuitry (406). The voltage-control...
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WO/2019/212683A1 |
Certain aspects of the present disclosure provide an input clock switching system, including: a clock source configured to output a reference clock signal; a clock generator circuit connected to the clock source and configured to output ...
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WO/2019/207093A1 |
The invention is referred to an electronic assembly (1) for an automotive lighting device (10). This electronic assembly (1) comprises a first pattern generation unit (3), arranged in direct electric contact with the input (2), a first s...
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WO/2019/203968A1 |
Aspects generally relate to reducing delay, or phase jitter, in high speed signals transmission. Variations in power supply to ground potential changes the amount of delay introduced by transmit circuity into the signal being transmitted...
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WO/2019/197480A1 |
The invention relates to a synchronization device (26i) designed to be inserted into a reception channel of a multichannel radio signal reception system between an interfacing module (10i) and a digital signal processing module (12i), th...
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WO/2019/195252A1 |
An example delay circuit is described that includes an input node to receive a first signal, a first circuit path, a second circuit path, an output buffer, and an output node. The first circuit path includes at least one first buffer and...
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WO/2019/191455A1 |
Some embodiments include apparatus having sampling circuitry, a first circuit path, a second circuit path, and a digitally controlled oscillator (DCO). The sampling circuit samples an input signal and provide data information and phase e...
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WO/2019/191377A1 |
A method for detecting a floating signal input terminal includes providing a common-mode input voltage to a first amplifier (204) coupled to the signal input terminal (234), and providing an output signal (230) generated by the first amp...
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WO/2019/182697A1 |
An apparatus is provided which comprises: a frequency locked loop (FLL) comprising an oscillator including a plurality of delay stages, wherein an output of each delay stage is counted to determine a frequency of the FLL; and one or more...
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WO/2019/182511A1 |
Various embodiments may provide a comparator circuit arrangement. The comparator circuit arrangement may include a preamplifier having a first input configured to be coupled to a first input voltage, a second input configured to be coupl...
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WO/2019/178988A1 |
Provided is a high speed, low noise dynamic comparator, comprising: an input unit, comprising input NMOS transistors (M1, M2) and input PMOS transistors (M6, M9); and a latch unit, comprising latch NMOS transistors (M4, M5) and latch PMO...
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WO/2019/171273A1 |
In certain embodiments, a system for detecting a peak laser pulse includes a laser, a photodiode configured to detect pulses emitted by the laser, and circuitry for detecting a peak pulse timing of the laser. The circuitry is configured ...
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WO/2019/171418A1 |
A drive assist circuit (20) is provided with a pulse generation circuit (201) that, when an assist signal (SA) has performed a first transition corresponding to a high-to-low transition of a gate signal (SG1), outputs a pulse for control...
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WO/2019/167670A1 |
The present art relates to a phase-locked loop circuit that enables power consumption to be reduced. The phase-locked loop circuit comprises: an SAR-ADC that includes two capacitors and outputs a comparison result of voltages occurring a...
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WO/2019/168983A1 |
A clock divider (200) includes a clock delay line (210), delay elements (250), a clock delay selector (220) coupled to the clock delay line (210) and configured to select one of the delay elements (250), and a bit pattern source (230, 24...
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WO/2019/164663A1 |
Apparatuses and methods for duty cycle distortion correction of clocks are disclosed. An example apparatus includes a clock circuit configured to receive complementary input clocks and a control signal and to provide multiphase clocks re...
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WO/2019/146177A1 |
According to the present invention, power consumption is suppressed in a time-to-digital converting circuit (TDC) used in a phase-locked loop. The time-to-digital converting circuit is provided with an analog-to-digital converting circui...
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WO/2019/137652A1 |
The invention relates to a radar sensor arrangement for transmitting and receiving radar waves, comprising a first subsensor with at least one first antenna for transmitting and receiving radar waves and with at least one first antenna c...
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WO/2019/140246A1 |
In at least one example, a current source (232) is coupled to a channel input of a switch (234), and an output of the switch (234) is coupled to a positive (140) or a negative data line (150) in a USB 2.0 communication system (200). Also...
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WO/2019/139216A1 |
The present invention relates to a pulse width modulation (PWM) control method and apparatus for keeping a direct current-side current constant in a three-level converter, which can control, according to a PWM scheme, such that a direct ...
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