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WO/2019/137652A1 |
The invention relates to a radar sensor arrangement for transmitting and receiving radar waves, comprising a first subsensor with at least one first antenna for transmitting and receiving radar waves and with at least one first antenna c...
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WO/2019/140246A1 |
In at least one example, a current source (232) is coupled to a channel input of a switch (234), and an output of the switch (234) is coupled to a positive (140) or a negative data line (150) in a USB 2.0 communication system (200). Also...
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WO/2019/139216A1 |
The present invention relates to a pulse width modulation (PWM) control method and apparatus for keeping a direct current-side current constant in a three-level converter, which can control, according to a PWM scheme, such that a direct ...
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WO/2019/133977A1 |
A comparator (104) includes a pair of back-to-back negative-AND (NAND) gates (254/260/264 and 256/262/266) and a delay circuit (202, 204) coupled to the pair of back-to-back NAND gates (254/260/264 and 256/262/266). The delay circuit (20...
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WO/2019/133336A1 |
Methods, systems, and devices for jitter cancellation with automatic performance adjustment are described. Within a clock distribution system in an electronic device (e.g., a memory device), a jitter cancellation system may be configured...
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WO/2019/133001A1 |
A flip-flop circuit is disclosed. The flip-flop circuit includes a single-input inverter, a dual -input inverter, a single-input tri-state inverter, a dual -input tri-state inverter, and two single-event transient (SET) filters. The sing...
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WO/2019/123825A1 |
[Problem] To provide a signal generating device used particularly in a ToF camera system employing an indirect method, the signal generating device being capable of handling various modulation frequencies by a simple structure. [Solution...
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WO/2019/125646A1 |
Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes an electrical circuit die having clock distortion ca...
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WO/2019/123828A1 |
[Problem] To provide a signal generation device that is used, in particular, for an indirect-type ToF camera system, wherein the occurrence of a ranging error that arises when multiple cameras are used to range the same object can be pre...
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WO/2019/123831A1 |
[Problem] To provide a pulse generator used particularly in a ToF camera system employing an indirect method, the pulse generator being capable of handling setting of various frequencies or phases using a simple structure. [Solution] Pro...
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WO/2019/125781A1 |
The disclosed circuit arrangements include a logic circuit (105), input register logic (104) coupled to the logic circuit and including a first plurality of bistable circuits (202) and a control circuit (102) coupled to the input registe...
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WO/2019/120991A1 |
Method for activating a feature of a chip(10) having an interface (20) comprising at least two power pins (GND, VCC). The method comprises the following steps: -the chip measures a series of voltage values between said power pins, -the c...
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WO/2019/123830A1 |
[Problem] To provide a signal generator used particularly for a ToF camera system adopting an indirect method, the signal generator being capable of suppressing cyclic errors using a simple configuration. [Solution] Provided is a signal ...
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WO/2019/125948A1 |
Apparatuses and methods for duty cycle error correction of clock signals are disclosed. An example method includes detecting a clock period error between a first clock signal and a third clock signal and adjusting a timing of the first o...
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WO/2019/118095A1 |
A method for offset calibration of a voltage comparator (1710) is disclosed according to certain aspects of the present disclosure. The method includes applying a first bias voltage (Ofst p) to a gate of a first compensation transistor (...
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WO/2019/114043A1 |
An on-chip reference clock automatic selection circuit, comprising an on-chip reference clock module, an off-chip clock signal, an input power supply, a power-on reset module, a clock counting module, and a clock selecting module, where ...
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WO/2019/118470A1 |
A comparator circuit (300) includes: a first transistor (MPl) configured to receive a first input (Vinp); and a second transistor (MP2) configured to receive a second input (Vinm). The comparator circuit (300) further includes a third tr...
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WO/2019/116764A1 |
The purpose of the present invention is to control, in an oscillator circuit using a comparator, the charging/discharging of a mirror capacitance between gate and drain of a MOSFET used as an amplifier in a gain section of the comparator...
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WO/2019/118223A1 |
Apparatuses and methods for data transmission offset values in burst transmissions. An example apparatus may include offset logic configured to provide offset values associated with a receiver circuit of a memory device coupled to a sign...
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WO/2019/112849A1 |
A system and method for generating a radio frequency (RF) waveform are described. The method includes defining a train of on-off pulses separated by an off state having no on- off pulses. The method further includes applying a multi-leve...
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WO/2019/106225A1 |
A digital value obtained from a preceding circuit element is temporarily stored and made available for a subsequent circuit element at a controlled moment of time. The digital value is received through a data input. A triggering signal i...
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WO/2019/106226A1 |
Digital values obtained from an output of a preceding circuit element are temporarily stored and made available for a subsequent circuit element at a controlled moment of time. A digital value is received for temporary storage, as well a...
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WO/2019/102785A1 |
The present invention realizes a digital noise filter with which it is possible to reduce jitter. A digital noise filter (11) for removing noise from an input signal, the input signal being an Off signal or an On signal, wherein the digi...
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WO/2019/096661A1 |
The invention relates to a circuit assembly for monitoring a sinusoidal alternating voltage signal (l_k) having a comparator (8), to which a sinusoidal alternating voltage signal (l_k) to be monitored or a signal obtained therefrom may b...
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WO/2019/093312A1 |
A measurement unit (3) generates, at every period of a reference clock, a period measured value representing the period of the reference clock as a number of passage stages, which is the number of stages at which a circulating signal pas...
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WO/2019/091110A1 |
The present disclosure relates to a receiver and to a method implemented in the receiver for recovering a signal clock from a received data signal. Successive edge transitions between successive data samples of the received data signal a...
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WO/2019/092440A1 |
A circuit portion (100) is provided which comprises a phase expansion portion (111) arranged to receive an oscillating input signal (202) with a first frequency and output a first digital signal (206) having a plurality of parts each hav...
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WO/2019/079116A1 |
A clock monitor includes a test clock input, as a reference clock input, another clock input, a measurement circuit, and control logic. The measurement circuit generates a measurement of a frequency or a duty cycle of the test clock inpu...
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WO/2019/079030A1 |
A quadrature clock correction (QCC) circuit includes: a first pair of clock correction circuits (304i, 3042) that output in-phase and anti-in-phase clock signals (cki, cki_b), respectively, of a four-phase clock signal (122); a second pa...
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WO/2019/073840A1 |
A sequence circuit 1 comprises: a detection unit (2) that detects the occurrence of an event on the basis of an input signal; an acceptance unit (4) that accepts the event the occurrence of which has been detected by the detection unit; ...
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WO/2019/074708A1 |
Apparatuses and methods for providing multiphase clock signals are described. An example apparatus includes first, second, third and fourth clocked inverters, first and second clock terminals, and first and second latch circuits. An inpu...
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WO/2019/074727A1 |
An example digital-to-time converter (DTC) (102) includes: a delay chain circuit (301) having a plurality of delay cells (302) coupled in sequence, the delay chain circuit including a first input (Fref) to receive a first clock signal an...
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WO/2019/068465A1 |
The invention relates to a method for monitoring a sensor clock signal (STS) in a sensor unit (10), which is generated and output for a data transfer between the sensor unit (10) and a control unit with a predefined period duration, wher...
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WO/2019/070196A1 |
Various embodiments may relate to a clocking circuit arrangement. The clocking circuit arrangement may include a clock source, as well as a global monitoring circuit arrangement including a monitoring tunable clock buffer, a reference cl...
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WO/2019/068460A1 |
The invention relates to a method for correcting at least one transmission parameter for data transmission between a sensor unit (10) and a control unit, wherein a sensor timing signal (STS) is generated by a sensor oscillator (14) with ...
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WO/2019/063117A1 |
Techniques facilitating reduction and/or mitigation of crosstalk in quantum bit gates of a quantum computing circuit are provided. A system can comprise a memory that stores computer executable components and a processor that executes th...
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WO/2019/066157A1 |
In order to minimize a popping noise generated in a pest extermination device that outputs high frequencies at different pitches by varying the frequencies over time or in a mobile terminal provided with the pest extermination device, a ...
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WO/2019/061077A1 |
A pulse width modification circuit, pulse width modification method, and electronic apparatus, configured to solve an existing problem in which a pulse width of a clock signal received by a digital clock does not meet a requirement. The ...
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WO/2019/054981A1 |
Method, systems, and circuitries are provided for generating an output signal with reduced spurs by dithering. A method to generate an output signal having a desired frequency based on a reference signal having a reference frequency incl...
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WO/2019/049320A1 |
Provided is a signal output device capable of appropriately outputting a signal even when a received signal amount is low. A signal output device 1 is provided with: a high-side comparator 30; a low-side comparator 40; a high-side AC cou...
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WO/2019/046442A1 |
For producing a low-power, low-phase noise oscillating signal, using an oscillator (102), a signal is produced having a base frequency component and an Nth harmonic component (112). N is a selected integer, and N > 1. The signal is filte...
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WO/2019/029890A1 |
According to the invention, an input stage (50) for an LVDS receiver circuit (100) is provided, comprising at least one supply voltage connection (41) and a first and a second stage input (11, 12) for applying a differential input signal...
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WO/2019/030080A1 |
The invention relates to a transceiver (12; 120; 1200) for a bus system (1) and to a method for reducing an oscillation inclination upon transitioning between different bit states. The transceiver (12; 20; 1200) has a first driver (1211)...
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WO/2019/029819A1 |
An integrated circuit (10, 10a-d) is disclosed, which is configured to be connected to an antenna module (3) having multiple antenna elements (17). The integrated circuit (10, 10a-d) comprises a plurality of communications circuits (50 j...
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WO/2019/028595A1 |
An oscillator, an integrated circuit, a timing chip, and an electronic device. The oscillator comprises a bias circuit (100) and a current mode comparator (200). The bias circuit (100) is connected to the current mode comparator (200). T...
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WO/2019/030081A1 |
The invention relates to a transceiver (12; 120) for a bus system (1) and to a method for reducing an oscillation inclination upon transitioning between different bit states. The transceiver (12; 120) has a first driver (123, 124, 125) f...
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WO/2019/028335A1 |
An interleaved DAC configured to generate a set of second digital inputs responsive to a set of first digital inputs. Each second digital input is obtained by subtracting the other second digital inputs in the set from the corresponding ...
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WO/2019/022905A1 |
Systems and methods for processing radiofrequency signals using modulation duty cycle scaling. One system (100) includes a first receive path (110) configured to directly sample a first signal in a first frequency range. The system (100)...
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WO/2019/022825A2 |
An integrated circuit is disclosed for voltage histogram generation. In an example aspect, the integrated circuit includes multiple delay stages coupled in series and multiple counters. The multiple delay stages include a first signaling...
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WO/2019/009968A1 |
A quarter-rate clock signal (205 out) is doubled in a frequency doubler (210, 220, 235) to produce a half-rate clock signal used by a serializer/deserializer (SerDes) interface (215, 240) to serialize (215) and deserialize (240) data (25...
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