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Patent Searching and Data


Matches 701 - 750 out of 23,621

Document Document Title
WO/2017/154126A1
A conventional distortion pulse shifting circuit has a problem that an output timing of a pulse signal cannot be controlled without use of a reset signal. A pulse shifting circuit according to the present invention is provided with: an i...  
WO/2017/154532A1
A problem with conventional distortion pulse shift circuits is that the output timing of a pulse signal cannot be controlled unless a reset signal is used. This pulse shift circuit is provided with: an integrator which integrates an inpu...  
WO/2017/151198A1
The present disclosure is directed towards systems and method for actively tuning a phase locked loop based on vibration excitation levels experienced by the phase locked loop. A bandwidth of the phase locked loop can be actively increas...  
WO/2017/148240A1
A loss-of-lock detection system for a phase-locked loop. An input clock frequency of the phase-locked loop is smaller than an output clock frequency of the phase-locked loop. The system comprises a frequency divider, a trigger, and a cou...  
WO/2017/149978A1
[Problem] To provide a ring oscillator capable of controlling frequency according to the delay amount of a delay element, with a structure for which fine-level frequency setting is possible. [Solution] A reference signal generation devic...  
WO/2017/150241A1
The present technology relates to a phase synchronization circuit and a method for controlling same, with which power consumption is low and phase noise can be improved while suppressing an increase in circuit area. The phase synchroniza...  
WO/2017/146833A2
The present disclosure describes current steering phase control for current-mode logic (CML) circuits. In some aspects, a circuit for frequency division comprises a current sink connected to a ground rail. The circuit also includes first...  
WO/2017/141258A1
An enhanced jitter tolerant clock and data recovery circuit (CDR) comprises of the blind- oversampling CDR placed in a first order delay locked loop with the data. In the blind oversampling CDR the output clock's position is a function o...  
WO/2017/140651A1
Disclosed is a receiver circuit comprising an analog-to-digital converter (ADC) circuit having an analog input, a clock input, and a digital output, and a clock divider circuit having a reference clock input and a phase selector input, a...  
WO/2017/143252A1
A band-pass clock distribution circuit includes a clock tree circuit including at least one clock buffer circuit. The clock tree circuit may be configured to receive a first clock signal from a clock generator circuit and to generate a s...  
WO/2017/133980A1
A device (1) ) with an antenna that receives a target carrier signal (3) from a remote target (2) and transmits a device carrier signal (6) modulated with data to communicate data between the device (1) and the target (2), which device (...  
WO/2017/129824A1
A waveform synthesizer comprises a controllable oscillator for generating an oscillator waveform having an oscillator cycle; a reference input for accepting a reference signal having a reference cycle; and a waveform detector coupled to ...  
WO/2017/127419A1
The present disclosure is generally directed to a harmonics correction method and apparatus. In an embodiment, the method and apparatus are carried out in a light-emitting diode ("LED") lighting unit that includes a set or string of LED ...  
WO/2017/120307A1
A voltage controlled oscillator (VCO) is disclosed. The VCO includes an active device. The VCO comprises an active device, wherein the active device further includes an n-type transistor having a drain, gate and bulk; a p-type transistor...  
WO/2017/119183A1
The purpose of the present invention is to suppress malfunctions of a synchronization circuit that captures a data signal in synchronization with a periodic signal. This synchronization circuit is provided with a holding unit and a varia...  
WO/2017/112222A1
An apparatus includes a phase detector coupled to an output of a frequency multiplier. A digital loop filter is coupled to the phase detector, and a duty cycle correction circuit is coupled to the digital loop filter.  
WO/2016/069634A9
Systems and Methods for controlling one or more mechanical resonators and determining information from resonant shift of the reonator(s) behavior, including at least one mechanical resonator, an excitation element for driving the resonat...  
WO/2017/112791A1
In some examples, a phase-locked loop (PLL) system (100) includes a phase-frequency detector (PFD) (102) configured to compare a phase-frequency reference signal (114) and a feedback signal (136), a charge pump (CP) (104) electrically co...  
WO/2017/108100A1
A phase locked loop, for a particularly in a beamforming system comprises a loop filter (1) to provide a control signal (FC) to a controllable oscillator (2); a frequency divider (3) configured to provide a first feedback signal (FB) and...  
WO/2017/112320A1
A memory device performs DLL (delay locked loop) calibration in accordance with a DLL calibration mode configured for the memory device. A host controller can configure the calibration mode based on operating conditions for the memory de...  
WO/2017/110657A1
The objective of the invention is to provide a phase synchronization circuit wherein even if the frequency of an input signal becomes unstable, the frequency can be stabilized. A phase synchronization circuit 12 that corrects an error be...  
WO/2017/107901A1
A spread spectrum clock generation apparatus (10), comprising: a monitoring module (13) for monitoring the depth of a first-in-first-out (FIFO) memory (12) and feeding the depth of the FIFO memory (12) back to a spread spectrum clock gen...  
WO/2017/112819A1
In described examples, a loop filter with an active discrete-level loop filter capacitor (300) can be used in a VCO (such as for CDR). In described examples, a loop filter capacitor function is simulated by sensing input loop filter curr...  
WO/2017/105349A1
According to various embodiments, there is provided a method for synthesizing a frequency, the method including: generating a fractional frequency signal based on a reference signal using a fractional frequency signal generator including...  
WO/2017/099368A1
Disclosed is a high bandwidth digital phase-locked loop using a positive edge and a falling edge of a signal. The disclosed digital phase-locked loop controls a frequency of a digital voltage control oscillator by comparing both a phase ...  
WO/2017/095186A1
Disclosed is a clock and data recovery apparatus. Specifically, the clock and data recovery apparatus according to an embodiment of the present invention comprises: a linear phase detector for comparing a phase difference and a frequency...  
WO/2017/095502A1
Described is an apparatus which comprises: a time-to-digital converter (TDC) to receive a reference clock and a feedback clock, wherein the TDC is to generate a digital output code representing a time difference between the reference clo...  
WO/2017/094310A1
The present invention improves the operating range of a phase detector equipped with flip-flops and improves the jitter resistance of a reception circuit. This phase detector is provided with a retention unit and a detection unit. In the...  
WO/2017/091254A1
Techniques for enabling a rapid clock frequency transition are described. An example of a computing device includes a Central Processing Unit (CPU) that includes a core and noncore components. The computing device also includes a dual mo...  
WO/2017/084905A1
A method for estimating a fundamental component (A) of an AC voltage ( V pcc ) comprises: receiving a timely varying measurement signal of the AC voltage ( V pcc ); parametrizing a fundamental component (A) of the AC voltage ( V pcc ), t...  
WO/2017/085942A1
The present invention suppresses output noise. An adjustment circuit (4b) adjusts the oscillation frequency by changing, on the basis of a control signal (Vcnta), the capacitance values of variable capacitor elements (C1, C2) connected i...  
WO/2017/071003A1
An apparatus, comprising a first sampling circuit configured to sample a clock signal according to a data signal to produce a first sampled signal, a second sampling circuit configured to sample the clock signal according to a delay sign...  
WO/2017/075597A1
In described examples of a voltage controlled oscillator (VCO) (30) for providing an oscillating output signal (vout), the VCO (30) includes a first inductor (II), and the oscillating output signal (vout) is responsive to a changing curr...  
WO/2017/068629A1
In a comparison output unit, the frequency difference between a frequency of a frequency division signal from a variable integer frequency divider of a frequency synthesizer and the frequency of a reference signal to the frequency synthe...  
WO/2017/065510A1
Disclosed is a phase-locked loop having a high bandwidth using the rising edge and falling edge of a signal. The disclosed phase-locked loop controls the frequency of a voltage controlled oscillator by comparing both a phase difference b...  
WO/2017/056855A1
This receiver is provided with: an A/D converter (12) which performs analog-digital conversion of an input signal; an equalizer (13) which equalizes the output from the A/D converter, removes intersymbol interference and outputs data; a ...  
WO/2017/058410A1
Described herein are architectures, platforms and methods for implementing scalable power in a wireless device. Multiple radio access technology architectures running different operating clock frequencies are supported by providing a sca...  
WO/2017/052891A1
Certain aspects of the present disclosure provide methods and apparatus (e.g., a level shifter) for buffering an oscillating signal generated by an oscillator. One example apparatus generally includes an amplifier having a first amplific...  
WO/2017/053372A1
Apparatus and methods for fractional-N synthesizer phase-locked loops with multi-phase oscillators are provided. In certain configurations, a fractional-N PLL includes a time- to-digital converter (TDC), a digital loop filter, a multi-ph...  
WO/2017/052899A1
Certain aspects of the present disclosure provide techniques and apparatus for glitch-free bandwidth switching in a phase-locked loop (PLL). One example PLL generally includes a voltage-controlled oscillator (VCO) comprising a first vari...  
WO/2017/053019A1
A device and method for analog to digital conversion is disclosed. The device can have a first amplifier operable to receive an input voltage and output a first control signal. The device can also have a first voltage-controlled oscillat...  
WO/2017/045338A1
An automatic frequency band calibration method for rapid lock of a phase-locked loop system. An AFC module is used to calibrate the frequency band of a VCO, and automatically select a frequency band according to a target frequency point,...  
WO/2017/043254A1
This phase synchronization circuit is provided with: a detection unit that detects transition of an input clock signal; an oscillation unit that generates a clock signal having a frequency corresponding to a first control signal and chan...  
WO/2017/034702A1
Described is an apparatus which comprises: a first clocking source having a first divider; a second clocking source having a second divider, wherein the first and second clocking sources are inductively coupled; and calibration logic to ...  
WO/2017/030755A1
Methods and apparatus for synchronizing dividers in different LO paths using pulse swallowing. One example apparatus generally includes a first path having a first frequency divider configured to generate a first divided signal from a fi...  
WO/2017/030849A2
Certain aspects of the present disclosure provide methods and apparatus for implementing a fully differential charge pump circuit that eliminates a source of noise and power consumption by using a low-noise switched-capacitor common-mode...  
WO/2017/027132A1
In one embodiment, method for frequency division comprises propagating a modulus signal up a chain of cascaded divider stages from a last one of the divider stages to a first one of the divider stages, and, for each of the divider stages...  
WO/2017/023688A1
Embodiments include a hybrid frequency synthesizer comprising a direct digital synthesizer configured to generate a digital output signal having a frequency determined by an input signal received from an externally-generated signal sourc...  
WO/2017/019365A1
Techniques for correcting clock distortion. The techniques include use of circuitry for detecting and correcting duty cycle distortion and quadrature clock phase distortion. For phase detection, detection circuitry (100) is made simpler ...  
WO/2017/007522A1
Methods and apparatus are described for synchronously stepping at least one of a data phase interpolator (PI) code (306) or a crossing PI code (308) in a clock and data recovery (CDR) circuit (206) until one or more preset criteria are s...  

Matches 701 - 750 out of 23,621