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WO/2023/063581A1 |
In an embodiment, an electronic device may comprise: a first frequency synthesizing circuit for outputting, on the basis of a first clock signal, a second electrical signal for converting the frequency of a first electrical signal; and a...
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WO/2023/059231A1 |
The present disclosure relates to oscillator arrangement (1) comprising an output port (4) adapted to output an output signal (5) with an output frequency (fout), an in loop oscillator (6) that is adapted for an in loop oscillator freque...
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WO/2023/057629A1 |
The invention relates to a computer-assisted method for sizing and then producing a magnetron cavity for an atomic clock, in particular for a hydrogen maser, the cavity being substantially cylindrical and including at least two curved el...
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WO/2023/055388A1 |
Secure circuitry of an integrated circuit detects a duration of a clock cycle of a crystal oscillator external to the integrated circuit, using a digital ring oscillator internal to the integrated circuit and having a higher frequency th...
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WO/2023/051998A1 |
The invention relates to an integrated circuit arrangement (100) having a controllable current source (10) for producing an AC current (I) having an adjustable mean value, wherein the current source (10) comprises two respectively contro...
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WO/2023/051291A1 |
Provided in the present disclosure is a linearity calibration method for a digital time converter. The method comprises: acquiring a phase prediction parameter and a phase lock error; and calculating a control word of a digital time conv...
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WO/2023/049123A1 |
The present embodiments provide a solution for clock delivery, distribution to an entire waferscale system composed of many chiplets. A clock distribution scheme according to embodiments is also fault tolerant, i.e., the clock distributi...
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WO/2023/048957A1 |
A low-power clock generation circuit has a phase generator that receives an input clock signal and uses the input clock signal to generate multiple intermediate clock signals with different phase shifts, a phase rotator circuit that outp...
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WO/2023/042455A1 |
This DLL circuit comprises: a first delay line having a first delay buffer that applies a delay corresponding to a control voltage to an input clock signal, the first delay line outputting an output clock signal through the first delay b...
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WO/2023/043613A1 |
A clock generation circuit has an injection-locked oscillator, a frequency doubler circuit, low pass filters and a calibration circuit. The injection-locked oscillator has an input coupled to a half-rate clock signal. The frequency doubl...
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WO/2023/038685A1 |
Embodiments relate to updating spur cancellation at a victim integrated circuit (IC) in accordance with dynamic changes in the operating frequencies of an aggressor IC. The aggressor IC changes its operating frequencies at an update time...
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WO/2023/038752A1 |
A frequency divider functionality detection and adjustment circuit includes an auxiliary voltage controlled oscillator (VCO) coupled to a first multiplexer (MUX), a programmable divider coupled to the first MUX, a second MUX coupled to t...
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WO/2023/034003A1 |
A method of quantization noise cancellation in a phase-locked loop (PLL) is provided according to certain aspects. The PLL includes a phase detector having a first input configured to receive a reference signal and a second input configu...
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WO/2023/028859A1 |
The present disclosure provides a physical unclonable function (PUF) device and an operation method therefor, and an electronic device. The PUF device comprises: a first signal generation circuit, which is configured to generate a first ...
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WO/2023/027078A1 |
A PLL circuit (1) for generating an output clock signal is provided with: a selection circuit (70) for selecting one of a plurality of clock signals as a reference clock signal for the PLL circuit (1); and a control circuit (75) for temp...
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WO/2023/020677A1 |
A timing recovery lock detector circuit for a signal receiver apparatus is configured to receive a quantised signal from an analog-to-digital convertor, the quantised signal having a periodic unit interval (UI); generate at least one sam...
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WO/2023/016292A1 |
Systems and methods for clock recovery are disclosed. The method comprises generating, by a first dynamic phase interpolator, a first center clock signal, and generating, by a second dynamic phase interpolator, a second center clock sign...
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WO/2023/013101A1 |
The present invention addresses the problem of suppressing fluctuation of an output oscillation frequency in a PLL circuit.　According to the present invention, an oscillator oscillates at a predetermined oscillation frequency. An oscil...
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WO/2023/010206A1 |
A phase-frequency detector comprises first transistor branch generating a first intermediate signal based on an input frequency signal, another first transistor branch generating a second intermediate signal based on a reference frequenc...
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WO/2023/014459A2 |
A hybrid true single-phase clock (H-TSPC) circuit includes a first logic circuit comprising non-ratio (NR) logic, a first mode switching device coupled to an output of the first logic circuit, a second logic circuit comprising ratio (R) ...
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WO/2023/012341A1 |
Examples relate to a circuit arrangement, a time-mode arithmetic unit circuit arrangement, an all-digital phase-locked loop, and corresponding methods. A circuit arrangement is configured to discard charges from a capacitive circuit elem...
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WO/2023/010234A1 |
A transceiving circuit, comprising: a clock adjustment module (A), a phase/frequency detector (B) and a first phase-locked loop (C), wherein a first input end of the clock adjustment module (A) is coupled to an input end of the transceiv...
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WO/2023/009579A1 |
A system (100) includes a ring oscillator (108) including an odd number of inverters arranged in a ring. The system (100) also includes a time to digital converter (113) including an odd number of flops, where each of the flops is couple...
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WO/2023/005157A1 |
The present disclosure relates to a phase-locked loop circuit and a signal processing device. The phase-locked loop circuit comprises: a charge pump configured to have a charge pump current; and a loop filter connected to the charge pump...
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WO/2023/009986A1 |
Systems and methods are disclosed for adjusting clock frequencies of endpoint devices in a mesh network for narrowband and ultra-narrowband communications. An endpoint device receives a reference timing signal over a wireless network fro...
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WO/2023/002260A1 |
A quantum orchestration platform (QOP) comprises a collection of processing units and analog components that produce synchronized analog pulses, readouts, and computations that may be used for operations with qubits. All processing units...
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WO/2023/000245A1 |
Provided by the present invention are a PLL circuit and an electronic device. The PLL circuit comprises a charge pump and a current input module; the charge pump is used to receive a control signal, and the control signal is used to cont...
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WO/2023/287455A1 |
Methods of using vapor cells may involve providing a vapor cell including a body defining a cavity within the body. At least a portion of at least one surface of the vapor cell within the cavity may include at least one pore having an av...
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WO/2023/276294A1 |
[Problem] To propose a receiving device, an abnormality detecting method, and an abnormality detecting program capable of detecting an abnormality relating to a reference signal that has been output. [Solution] This receiving device comp...
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WO/2023/278083A2 |
Aspects of the disclosure relate to a ring oscillator (RO) frequency divider configured to frequency divide an input clock by a programmable divider ratio to generate an output clock. In this regard, the RO frequency divider receives the...
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WO/2022/267591A1 |
The present application provides a clock switching method and a clock switching apparatus, an electronic device, and a readable storage medium. The clock switching method comprises: when determined that a first reference clock is in a lo...
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WO/2022/271474A1 |
A system comprises a digital processing circuit (325), a frequency modulator (360), an amplitude modulator (370), and an adder (390). The digital processing circuit (325) receives an input signal and a correlation signal and generates a ...
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WO/2022/267792A1 |
A clock circuit and a control method therefor, and a communication device. The clock circuit comprises a phase-locked loop (100) and a trigger unit (200); the phase-locked loop (100) is used for receiving a reference clock signal and out...
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WO/2022/265315A1 |
A frequency multiplier is provided. A harmonic generator of the frequency multiplier comprises: a harmonic generating core unit; a first resonant tank which is connected to a first output terminal and a second output terminal of the harm...
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WO/2022/262995A1 |
A multi-carrier transceiver receives and transmits wireless communication signals on multiple carriers simultaneously. To generate Local Oscillator (LO) signals for mixers operating at different frequencies, a multi-frequency LO signal g...
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WO/2022/263704A1 |
Example embodiments relate to generation of qubit clock signals. A superconductive phase detector may receive a reference frequency signal across a boundary of a cryogenic environment. A superconductive oscillator may be configured to ge...
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WO/2022/263348A1 |
According to an aspect, there is provided an all-digital phase-locked loop, ADPLL, for a radio receiver, transmitter or transceiver. The ADPLL comprises a time-to-digital converter for generating a digital time signal based on an externa...
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WO/2022/266526A1 |
A direct digital synthesizer (DDS) circuit. The circuit includes a first input to receive a first fixed frequency clock signal having a first frequency, a second input to receive a second fixed frequency clock signal having a second freq...
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WO/2022/262668A1 |
A clock driver circuit for low powered clock driving may include: a multiple phase divider; a buffer supplying at least one of multiple phases to the multiple phase divider at a center frequency that is an integer multiple of an input fr...
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WO/2022/264462A1 |
The present invention shortens a lock time for a circuit provided with a phase comparator.　According to the present invention, a phase comparator compares the phase of an inputted reference clock signal and the phase of a feedback cloc...
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WO/2022/266419A1 |
An integrated circuit transceiver device includes a plurality of functional circuits, and clock circuitry for distributing synchronous, in-phase, phase-locked clock signals to all transceiver circuits. The clock circuitry includes a freq...
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WO/2022/256992A1 |
A diamond NV-15N coupled spin system-based atomic clock implementation method and apparatus. The method comprises: applying a pulse sequence to implement joint initialization of an NV electron spin and a 15N nuclear spin; performing Rams...
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WO/2022/257051A1 |
The embodiments of the present application relate to the technical field of communications, and can realize fast synchronization between a transmission signal of an NFC card device and a carrier of an NFC card reader. Provided are a near...
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WO/2022/260823A1 |
In certain aspects, a sampler includes a sampling capacitor, a precharge switch coupled to the sampling capacitor, one or more discharge circuits coupled to the sampling capacitor, and a reference-voltage circuit coupled to the sampling ...
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WO/2022/257638A1 |
A. phase locked loop having a charge pump is described. The charge pump has circuitry to select a mode for each semiconductor chip from a plurality of modes to enhance yield. Nine unique modes are defined from which a selection is made f...
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WO/2022/261396A1 |
In absence of electrical approaches for realization of highly stable RF oscillator, opto- electronic oscillators (OEO) techniques are provided, where self-forced oscillation techniques using long optical delays demonstrate significant sh...
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WO/2022/260757A1 |
A radio frequency (RF) generator incorporates an automatic level control (ALC) circuit to control the output level of the RF signal where the ALC circuit implements synchronized ADC sampling, pulse sample indexing, gated accumulation to ...
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WO/2022/260832A1 |
An aspect relates to an apparatus including an input buffer including an input configured to receive an input voltage; a ramp voltage generator including an input coupled to an output of the input buffer; an evaluation circuit including ...
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WO/2022/256990A1 |
An implementation method and apparatus for a diamond NV-14N coupling spin system-based atomic clock. The radio frequency (RF) frequency is locked by using 14N zero field splitting, and the RF frequency is outputted as a frequency standar...
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WO/2021/222202A9 |
A measurement system includes a source unit to provide a source signal to a sample and a voltage source and/or a current source and a memory. The system also includes a measurement unit configured to acquire from the sample an measuremen...
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