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WO/2022/240540A1 |
A system includes delay locked loop (DLL) including a phase detector having a first input coupled to an input of the DLL, and a first delay circuit and a second delay circuit coupled in series between the input of the DLL and a second in...
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WO/2022/241356A1 |
An apparatus is disclosed for a charge pump with voltage tracking. In an example aspect, the apparatus includes a locked loop having a charge pump, a filter, a second switch, and a buffer. The charge pump includes a first current source,...
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WO/2022/240600A1 |
An example digital to time converter (124) includes: a first switch (304) having a first terminal, a second terminal, and a first control terminal configured to receive a control signal (D). A second switch (310) having a third terminal ...
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WO/2022/232982A1 |
A variety of applications can include a phase frequency detector structured to track the falling edges of two input signals to detect a phase difference between the two signals and to generate one or more signals that can be used to adju...
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WO/2022/233457A1 |
A system for frequency regulation in a AC power supply system (10) is disclosed, wherein the system comprises an uninterruptible power supply (12) being electrically connected to the AC power supply system (10) and comprising a phase-loc...
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WO/2022/233832A1 |
The invention provides detection of harmonic conditions in a delay-locked loop. To this end, multiple delayed clock signals are evaluated within the delay-locked loop, and on the basis thereof, in particular on the basis of the times of ...
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WO/2022/231653A1 |
Apparatus and methods of automatically trimming a PCB-based LC circuit. The apparatus may comprise an interface to a printed circuit board (PCB). The PCB may include a PCB inductor and a PCB capacitor to form an LC circuit. The LC circui...
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WO/2022/229496A1 |
A high-frequency electronic module comprising a first silicon wafer with a waveguide, a second silicon wafer attached on top of the first silicon wafer and an electric circuit on the top surface of the second silicon wafer. The high-freq...
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WO/2022/229844A1 |
A digital clean-up oscillator and associated method are provided for cleaning jitter from a noisy clock signal, comprising receiving a reference clock oscillator signal and the noisy clock signal to be cleaned; measuring the frequency of...
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WO/2022/229972A1 |
Injection locked clock multiplier with an embedded phase interpolator and 2X frequency range. A wide range (2X) injection locked clock multiplier (ILCM) with an embedded phase interpolator multiplies a low-frequency clock to generate a h...
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WO/2022/222275A1 |
A local oscillator phase-lock frequency synthesizer, for example, a local oscillator phase-lock frequency synthesizer compatible with a C-band and a millimeter wave band. By introducing a voltage-controlled oscillator, a frequency multip...
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WO/2022/226498A1 |
One or more examples relate, generally to phase and frequency error processing. An apparatus includes a phase path and a frequency path. The phase path processes phase error of communications between network nodes. The phase path include...
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WO/2022/222917A1 |
Systems and methods are provided for performing quantum operations.The systems comprise of a vectorized quantum controller can receive a command from a computing device, the command indicating application of a quantum gate to a qubit of ...
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WO/2022/215424A1 |
A high-temperature tank (116) includes an optical window which transmits a laser (132) and is provided at one end, and a right-angle conical mirror (102) which is provided at the other end, has an opening (106) at the apex and which refl...
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WO/2022/215806A1 |
According to an aspect of the present invention, provided is a system for synchronizing phases, the system comprising: a first phase locked loop (PLL) unit which generates a first clock on the basis of a reference clock; and a second PLL...
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WO/2022/215076A1 |
Generation of a clock signal in a semiconductor integrated circuit (IC) is controlled using a Noise Modulation Agent (NMA), configured to measure the clock signal and output a parameter indicative of an effective cycle time of the clock ...
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WO/2022/215503A1 |
A clock generator 100 is provided with a plurality, N, of PLL circuits 200. A phase comparison circuit 210 generates a control signal S1 corresponding to a phase difference between a first clock CLKa input to a first terminal T1, and a s...
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WO/2022/212734A1 |
Methods and systems are described for generating early and late votes for a clock recovery system, each early or late vote associated with a detected transitional data pattern in a data stream, generating a first early-late vote measurem...
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WO/2022/212310A1 |
In at least one embodiment, a method includes generating a digital time code corresponding to an input clock signal using a time-to-digital converter responsive to a reference clock signal and a time-to-digital converter calibration sign...
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WO/2022/207964A1 |
A frequency reference device comprising a waveguide with a first end and a second end, a signal transmitter module for generating a high-frequency electromagnetic wave in the waveguide, and a signal receiver module for receiving the high...
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WO/2022/205171A1 |
A signal transmission method and apparatus, a storage medium and a chip system, which are used to transmit data of C-V2X and ETC frequency bands over one radio frequency transmission channel (33), such that the footprint of a transceiver...
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WO/2022/198339A1 |
An oscillator and method for maintaining a phase lock is provided. The oscillator may include an oscillator input port for receiving a reference signal, an oscillator output port for outputting an oscillator output, an unlocked oscillato...
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WO/2022/199852A1 |
An integrated, distributed, multiple Phase Locked Loop (multi-PLL) system locks the frequency and phase of multiple secondary PLLs to that of a primary PLL. The VCOs in all PLLs receive both first and second control signals. The primary ...
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WO/2022/198434A1 |
The present application discloses a sensing system, a related apparatus, and a method for obtaining a working clock signal. The sensing system comprises at least one chip cascade branch; in the chip cascade branch, a clock integration ci...
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WO/2022/188354A1 |
An interleaved signal generating circuit is provided, comprising: an interleaved pulse generating circuit (300) which generates a first pulse signal (ActClk) according to a first control signal (ActEn) and generates a second pulse signal...
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WO/2022/190694A1 |
The present invention addresses the problem of providing a highly versatile substrate, a production method for the substrate, and a production method for a unit cell using the substrate. This problem is solved by providing a substrate ch...
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WO/2022/191014A1 |
The light source driving circuit pertaining to the present disclosure comprises a first delay circuit (10) that imparts a delay at a first time resolution on the basis of a clock signal to an inputted signal, and a second delay circuit (...
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WO/2022/183774A1 |
A clock data recovery circuit and a clock data recovery method. The clock data recovery circuit comprises a time delay loop (100), a frequency locking loop (200) and a deserializer (300), wherein the time delay loop (100) is configured t...
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WO/2022/176115A1 |
This voltage setting circuit (11) comprises: a frequency comparator (14) for comparing the oscillation frequency of a first distributed voltage-controlled oscillator (13_1) and that of a second distributed voltage-controlled oscillator (...
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WO/2022/173522A1 |
In one aspect, a method of adjusting a first oscillating signal, includes generating a relationship prediction responsive to a deep learning model configured to predict a relationship between a fundamental quantity of a first oscillating...
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WO/2022/168210A1 |
This phase interpolation circuit generates, on the basis of a first input clock signal and a second input clock signal having a first phase difference, an output clock signal having a phase in accordance with a phase interpolation code, ...
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WO/2022/165021A1 |
Aspects of the technology described herein relate to an ultrasound device that may has a phase-locked loop (PLL) that includes a digitally-controlled oscillator (DCO). The DCO includes a plurality of current source unit cells with respec...
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WO/2022/161193A1 |
Disclosed in the present invention is a low-power-consumption fractional frequency-division phase-locked loop circuit, comprising a phase discrimination module, a voltage-to-current conversion module, a loop filter, a voltage-controlled ...
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WO/2022/148210A1 |
Disclosed is a microstrip structure-based subminiature atomic frequency standard microwave cavity, comprising a cavity body. One end of the cavity body is a light outlet; the other end is a light inlet. A line groove is provided in the c...
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WO/2022/147137A1 |
An integrated circuit device [200] is provided. In some examples, the integrated circuit device [200] includes a first re-timer [216] configured to receive a reference clock signal [201] and a voltage controlled oscillator (VCO) output s...
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WO/2022/133925A1 |
Provided in the present disclosure are a frequency calibration apparatus and method for a voltage-controlled oscillator, and a storage medium. The apparatus comprises: a frequency divider connected to a voltage-controlled oscillator, a t...
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WO/2022/134925A1 |
Disclosed in the present invention are a spread spectrum clock generator and an electronic device. The spread spectrum clock generator comprises a modulation period module circuit, a spread spectrum depth module circuit, and a clock circ...
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WO/2022/139891A1 |
A circuit for processing a data stream is described. The circuit comprises a burst phase detector configured to receive a data input signal; a clocking circuit coupled to the burst phase detector, wherein the clocking circuit is configur...
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WO/2022/138025A1 |
In a first phase synchronization circuit (10A), a phase comparison unit (13) receives, as inputs, a detection signal and a driving signal of a first vibration system (20A), and outputs a signal indicating a phase difference between the i...
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WO/2022/126891A1 |
A SerDes module clock network architecture, comprising a reference clock input port, a plurality of data transmission channels, several user logic interfaces, several frequency division branches and a phase locked loop. The reference loc...
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WO/2022/126894A1 |
Provided is a frequency selection circuit. The frequency selection circuit comprises a voltage-controlled oscillator, a feedback frequency divider, a frequency selection unit and a register set, wherein the voltage-controlled oscillator ...
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WO/2022/132414A1 |
A digital phase-frequency detector characterizes a delay between two input clock signals using a ring oscillator. A cycle count of a ring oscillator signal circulating through a loop in the ring oscillator during the delay provides a coa...
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WO/2022/128049A1 |
An apparatus is disclosed for provision of an indication of an angular difference between first and second input signals. The apparatus comprises a phase frequency detector (PFD) configured to receive the first and second input signals a...
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WO/2022/126097A1 |
Apparatus and methods for control and calibration of external oscillators are provided herein. In certain embodiments, an electronic oscillator system includes a semiconductor die and a controllable oscillator that is external to the sem...
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WO/2022/118440A1 |
This phase interpolation circuit includes: a first buffer circuit (201) for generating a first input clock signal by adjusting a rise time or a fall time of a first reference clock signal on the basis of a first control signal; a second ...
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WO/2022/115650A1 |
A circuit and method are described for generating a low-jitter output clock having an arbitrary non-integer divide ratio relative to a high-frequency clock. Integer divide ratios of the high-frequency clock may be achieved by dividing th...
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WO/2022/111340A1 |
A clock calibration circuit (200), comprising: a clock generation module (20), a clock frequency division module (30), and a modem (40) which are connected to each other. When the modem (40) is switched to a sleep mode, the modem (40) ou...
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WO/2022/107668A1 |
An oscillator according to the present technology functions as a transformer-based LC oscillator and comprises: a first capacitor group that is connected in parallel to a primary-side winding of a transformer and forms a first LC tank to...
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WO/2022/103652A1 |
An atomic clock employs hybrid long/short quantum clock frequency regulation wherein each of a series of regulation cycles includes a relatively long (four Ramsey- cycle) combination error signal (CES) cycle and plural relatively short (...
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WO/2022/100755A1 |
Disclosed in the present invention are a low-temperature coefficient ring oscillator, a chip, and a communication terminal. The low-temperature coefficient ring oscillator comprises a temperature tracking compensation circuit, an inverte...
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