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WO/2022/107668A1 |
An oscillator according to the present technology functions as a transformer-based LC oscillator and comprises: a first capacitor group that is connected in parallel to a primary-side winding of a transformer and forms a first LC tank to...
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WO/2022/103652A1 |
An atomic clock employs hybrid long/short quantum clock frequency regulation wherein each of a series of regulation cycles includes a relatively long (four Ramsey- cycle) combination error signal (CES) cycle and plural relatively short (...
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WO/2022/100755A1 |
Disclosed in the present invention are a low-temperature coefficient ring oscillator, a chip, and a communication terminal. The low-temperature coefficient ring oscillator comprises a temperature tracking compensation circuit, an inverte...
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WO/2022/097557A1 |
A manufacturing method according to the present invention comprises: attaching a first glass plate (11) to a first surface (10p) of a cell body (10) to form a lid on a gas generation part (20) and a droplet port (16); injecting a raw mat...
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WO/2022/095323A1 |
Disclosed are a clock and data recovery circuit, method and apparatus. The circuit comprises: a receiving module for receiving an analog signal; a first equalization module connected to the receiving module, the first equalization module...
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WO/2022/095404A1 |
The present disclosure relates to the technical field of voltage controlled oscillation, and provides a voltage controlled oscillator and a control method thereof, and a P2P interface circuit and an electronic device. The voltage control...
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WO/2022/093344A1 |
Systems and methods related to calibrating a phase interpolator by amplifying timing differences are described. An example system includes a calibration stage configured to output a calibration code for a phase interpolator. The system f...
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WO/2022/089085A1 |
Provided are an oscillator and a clock generation circuit. The oscillator comprises: a first ring-shaped topological structure, wherein a plurality of first inverters (11) are connected in an end-to-end mode, so as to propagate an oscill...
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WO/2022/088782A1 |
Provided in the embodiments of the present application are an oscillation circuit and a clock producing circuit, the oscillation circuit comprising: a power source producing module configured to produce a positive temperature coefficient...
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WO/2022/086883A1 |
An integrated circuit is described. This integrated circuit may include an input connector, coupled to a signal line, that conveys an input signal corresponding to encoded data, where the encoded data is encoded using a BMC, and the inpu...
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WO/2022/083638A1 |
A chip clock frequency adjustment method and apparatus, a chip, and an electronic device. The chip comprises an RC oscillator. The RC oscillator is used for outputting a clock signal, and comprises an RC frequency selection network consi...
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WO/2022/080947A1 |
The present disclosure relates to: a communication technique for convergence of IoT technology and a 5th generation (5G) or a pre-5G communication system for supporting a higher data transmission rate beyond a 4th generation (4G) communi...
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WO/2022/077987A1 |
A clock synchronization circuit, a control method, a printed circuit board and a communication device. The clock synchronization circuit comprises a first frequency divider, and an external reference signal processing module, a phase det...
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WO/2022/073617A1 |
An analog PLL employs digital circuitry for calibration and characterization, precisely setting and maintaining the bandwidth of the PLL. A digital calibration circuit calibrates the value of the resistor or capacitor in the loop filter ...
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WO/2022/071999A1 |
A circuit includes a phase-locked loop configured to receive a reference clock signal and to generate a first clock signal having a first frequency. A secondary clock generation circuit is configured to generate a second clock signal hav...
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WO/2022/064893A1 |
This DLL circuit (110) comprises a phase delay circuit (114), a selection circuit (115), a detection circuit (117), and a clock stopping circuit (116). The phase delay circuit (114) generates a plurality of delay signals having respectiv...
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WO/2022/062094A1 |
A clock source circuit (10), a computer case (20), and a multi-computer case cascaded system (30). The clock source circuit (10) comprises a reference signal generation circuit (110), a clock signal generation circuit (120), a programmab...
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WO/2022/060447A1 |
An example power control apparatus includes a phase locked loop (PLL) to provide a clock signal of a phase-locked frequency, a switching circuit to output a set voltage, and a controller to generate a clock signal of a target frequency f...
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WO/2022/059400A1 |
An oscillator circuit (10) is provided with a plurality of oscillators (11) and wires (12) that connect the plurality of oscillators (11). The wires (12) are disposed so as to form a closed circuit that passes once through each of the pl...
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WO/2022/060887A1 |
A system includes, in part, a first optical modulator adapted to modulate a first optical signal with a first data to generate a first modulated optical signal, a second optical modulator adapted to modulate a second optical signal with ...
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WO/2022/057867A1 |
A loop filter, and a timing recovery method and apparatus. The loop filter comprises: N input terminals, configured to receive N first signals, wherein N is any integer greater than or equal to two; a source filter, comprising an integra...
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WO/2022/059398A1 |
[Problem] To adjust oscillator characteristics. [Solution] This oscillating device is provided with: a plurality of delay elements which sequentially delay an input signal and which return at least some of the delayed signals to a previo...
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WO/2022/053592A1 |
An electrical circuit, comprising: an oscillating element configured to provide a clock signal; and a clock synchronization unit configured to adapt the clock signal based on a reference signal; wherein the clock synchronization unit is ...
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WO/2022/051875A1 |
An oscillator has a feedback loop with a signal output, a multi-pole resonator, and a gain block. The gain block applies a gain sufficient to generate a stable oscillation signal at the signal output; and the multi-pole resonator is tuna...
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WO/2022/052594A1 |
An oscillating circuit, comprising a constant voltage providing module (11) for outputting a constant voltage; a constant current providing module (12) for outputting a constant current; and an oscillation module (13) connecting the cons...
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WO/2022/051904A1 |
A phase locking method, a related phase-locked loop (100), a chip and an electronic device. A phase locking process comprises a frequency locking stage and a phase locking stage, wherein the phase locking stage comprises a loading period...
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WO/2022/051903A1 |
The present application discloses a phase-based frequency divider and a related phase-locked loop (100), a chip, an electronic device and a clock generation method. The phase-locked loop comprises: a phase error generator (102) for gener...
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WO/2022/055854A1 |
Described herein are apparatus and methods for highly linear phase rotators with continuous rotation. A method includes generating a first code and a second code based on a desired offset to match a first and second frequency, respective...
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WO/2022/046339A1 |
An apparatus is disclosed that implements a phase-locked loop (PLL) that uses multiple error determiners as part of a feedback loop. In an example aspect, an apparatus for generating a frequency includes a PLL. The PLL includes a loop fi...
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WO/2022/046304A1 |
A memory system (10) is provided. The memory system (10) includes a memory system (22) and a data bus (24) electrically coupled to the memory system (22). The memory system (10) further includes one or more memory devices (12, 14, 16) co...
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WO/2022/041277A1 |
A phase-locked loop (10) and a radio frequency transceiver, which relate to the field of wireless communications, and are used for reducing noise from a divider (35) and a charge pump (32), and reducing phase noise from the phase-locked ...
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WO/2022/037216A1 |
A detection circuit and a detection method. The detection circuit is used for detecting phase information between two clock signals having different frequencies, and the two clock signals comprise a low-frequency clock signal and a high-...
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WO/2022/040645A1 |
Circuitry for implementation in RF transmitters and receivers is described. In an implementation the circuitry can include a clock signal generator, a logic gate control signal generator, a baseband signal processor, a mixer coupled to a...
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WO/2022/033005A1 |
The present invention relates to a delay locked loop circuit, comprising: a variable delay line for delaying an initial clock signal to generate a delayed clock signal; and a control circuit, which is connected to the variable delay line...
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WO/2022/035432A1 |
An assembly includes one or more high temperature vapor cells positioned along an axis of the assembly, a vacuum envelope encasing the one or more high temperature vapor cells, and one or more sets of low thermal conductivity mounting st...
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WO/2022/034943A1 |
The present disclosure provides the structure of a voltage controlled oscillator (VCO) of a receiver included in a terminal and a base station in a wireless communication system. According to an embodiment applicable to the present discl...
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WO/2022/029526A1 |
A system comprises quantum control interconnect circuitry configured to receive a plurality of fixed-frequency signals, a variable-frequency signal, a quantum control pulse, a quantum element readout pulse, and a quantum element return p...
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WO/2022/029125A1 |
The invention describes a control unit (2, 21) for generating a plurality of synchronized radio frequency (RF) output signals (RFout,i) each having a respective output frequency (fi), phase (ΦL), and amplitude (Ai), comprising: a signal...
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WO/2022/026356A1 |
An apparatus (102) includes a phase frequency detector (302) having a detector output and first and second inputs, the phase frequency detector configured to provide a phase difference signal at the detector output responsive to the firs...
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WO/2022/025972A1 |
Ovens for atomic clocks may include a body including a cavity within the body. Heating elements may be distributed around the body, the heating elements including coils of electrically conductive material. Those coils configured to gener...
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WO/2022/017033A1 |
Provided are a clock signal production circuit, a clock signal production method, and an electronic device, relating to the technical field of communications. In the clock signal production circuit, by digital circuits such as a control ...
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WO/2022/018951A1 |
The objective of the present invention is to provide an atomic cell, and a method for manufacturing the same, which enable an alkali metal to be disposed more easily, and with which productivity can be improved. This atomic cell is cha...
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WO/2022/014156A1 |
Provided is a hermetic container, and a method for manufacturing the same, with which optical transparency is not impaired even if a mode is adopted enabling an effective increase in hermeticity, such as thermocompression bonding. The ...
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WO/2022/007782A1 |
The disclosed systems, structures, and methods are directed to a low jitter phase-lock loop (PLL) based frequency synthesizer, comprising a first frequency divider, a phase frequency detector, a charge pump, a low-pass filter, a voltage ...
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WO/2022/009701A1 |
[Problem] To provide an atomic frequency obtaining device which enables an improvement in mass-productivity and a reduction in size, and an atomic clock which uses the atomic frequency obtaining device. [Solution] A laser light source 20...
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WO/2022/010754A1 |
A system and method for protecting against a voltage glitch are provided. Generally, the system includes a reset-detector coupled to a supply voltage (VCC) and to a power-on-reset (POR) block, and a glitch-detector coupled to VCC and the...
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WO/2022/005905A1 |
An apparatus implements a multiplying delay-locked loop (MDLL) including a sampler to be calibrated. In an example aspect, an apparatus includes an MDLL and a sampler calibrator. The MDLL includes a locked-loop feedforward path with a sa...
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WO/2022/001940A1 |
Disclosed in the present application are a phase jitter compensation method, a phase jitter compensation module and a digital phase-locked loop. The phase jitter compensation method comprises: acquiring a phase error signal of the digita...
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WO/2021/259324A1 |
A clock sending apparatus and method, and a clock receiving apparatus and method. The clock sending apparatus comprises: an input unit (102), configured to input a first input clock and a second input clock; a sampling unit (104), config...
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WO/2021/259235A1 |
The present disclosure relates to a method for boosting the frequency of a clock signal, a clock circuit, and a digital processing device. More specifically, provided is a method for boosting the frequency of a clock signal, comprising: ...
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